board: toradex: colibri_vf: Add DCU support for Colibri Vybrid
The Vybrid SoC family has the same display controller unit (DCU)
like the LS1021A SoC. This patch adds platform data, pinmux defines
and clock control to enable the driver for Toradex Colibri Vybrid
module.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h
index a46e396..73b1dd2 100644
--- a/arch/arm/include/asm/arch-vf610/crm_regs.h
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -9,6 +9,8 @@
#ifndef __ASSEMBLY__
+#include <linux/types.h>
+
/* Clock Controller Module (CCM) */
struct ccm_reg {
u32 ccr;
@@ -150,6 +152,9 @@
#define CCM_CACRR_ARM_CLK_DIV_MASK 0x7
#define CCM_CACRR_ARM_CLK_DIV(v) ((v) & 0x7)
+#define CCM_CSCMR1_DCU1_CLK_SEL (1 << 29)
+#define CCM_CSCMR1_DCU0_CLK_SEL (1 << 28)
+
#define CCM_CSCMR1_QSPI0_CLK_SEL_OFFSET 22
#define CCM_CSCMR1_QSPI0_CLK_SEL_MASK (0x3 << 22)
#define CCM_CSCMR1_QSPI0_CLK_SEL(v) (((v) & 0x3) << 22)
@@ -174,6 +179,13 @@
#define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK (0xf << 20)
#define CCM_CSCDR2_ESDHC1_CLK_DIV(v) (((v) & 0xf) << 20)
+#define CCM_CSCDR3_DCU1_EN (1 << 23)
+#define CCM_CSCDR3_DCU1_DIV_MASK (0x7 << 20)
+#define CCM_CSCDR3_DCU1_DIV(v) (((v) & 0x7) << 20)
+#define CCM_CSCDR3_DCU0_EN (1 << 19)
+#define CCM_CSCDR3_DCU0_DIV_MASK (0x7 << 16)
+#define CCM_CSCDR3_DCU0_DIV(v) (((v) & 0x7) << 16)
+
#define CCM_CSCDR3_NFC_PRE_DIV_OFFSET 13
#define CCM_CSCDR3_NFC_PRE_DIV_MASK (0x7 << 13)
#define CCM_CSCDR3_NFC_PRE_DIV(v) (((v) & 0x7) << 13)
@@ -193,6 +205,7 @@
#define CCM_CCGR0_DSPI1_CTRL_MASK (0x3 << 26)
#define CCM_CCGR1_USBC0_CTRL_MASK (0x3 << 8)
#define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14)
+#define CCM_CCGR1_TCON0_CTRL_MASK (0x3 << 26)
#define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28)
#define CCM_CCGR2_QSPI0_CTRL_MASK (0x3 << 8)
#define CCM_CCGR2_IOMUXC_CTRL_MASK (0x3 << 16)
@@ -203,6 +216,7 @@
#define CCM_CCGR2_PORTE_CTRL_MASK (0x3 << 26)
#define CCM_CCGR3_ANADIG_CTRL_MASK 0x3
#define CCM_CCGR3_SCSC_CTRL_MASK (0x3 << 4)
+#define CCM_CCGR3_DCU0_CTRL_MASK (0x3 << 16)
#define CCM_CCGR4_WKUP_CTRL_MASK (0x3 << 20)
#define CCM_CCGR4_CCM_CTRL_MASK (0x3 << 22)
#define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24)
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h
index cac68ef..ca97462 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -69,6 +69,7 @@
#define USB_PHY0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050800)
#define USB_PHY1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050C00)
#define SCSC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000)
+#define DCU0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00058000)
#define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00060000)
#define SPDIF_BASE_ADDR (AIPS0_BASE_ADDR + 0x00061000)
#define ESAI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00062000)
@@ -98,6 +99,7 @@
#define USBC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00034000)
#define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x00050000)
#define ENET1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00051000)
+#define DCU1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00058000)
#define NFC_BASE_ADDR (AIPS1_BASE_ADDR + 0x00060000)
#define QSPI0_AMBA_BASE 0x20000000
diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
index a140be0..5af071a 100644
--- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h
+++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
@@ -40,6 +40,8 @@
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH)
#define VF610_DSPI_SIN_PAD_CTRL (PAD_CTL_IBE_ENABLE | PAD_CTL_DSE_20ohm | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH)
+#define VF610_DCU_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_SRE | \
+ PAD_CTL_DSE_37ohm | PAD_CTL_OBE_ENABLE)
enum {
VF610_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL),
@@ -166,6 +168,35 @@
VF610_PAD_PTC28__NF_CLE = IOMUX_PAD(0x0194, 0x0194, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
+ VF610_PAD_PTE0__DCU0_HSYNC = IOMUX_PAD(0x01a4, 0x01a4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE1__DCU0_VSYNC = IOMUX_PAD(0x01a8, 0x01a8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE2__DCU0_PCLK = IOMUX_PAD(0x01ac, 0x01ac, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE4__DCU0_DE = IOMUX_PAD(0x01b4, 0x01b4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE5__DCU0_R0 = IOMUX_PAD(0x01b8, 0x01b8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE6__DCU0_R1 = IOMUX_PAD(0x01bc, 0x01bc, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE7__DCU0_R2 = IOMUX_PAD(0x01c0, 0x01c0, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE8__DCU0_R3 = IOMUX_PAD(0x01c4, 0x01c4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE9__DCU0_R4 = IOMUX_PAD(0x01c8, 0x01c8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE10__DCU0_R5 = IOMUX_PAD(0x01cc, 0x01cc, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE11__DCU0_R6 = IOMUX_PAD(0x01d0, 0x01d0, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE12__DCU0_R7 = IOMUX_PAD(0x01d4, 0x01d4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE13__DCU0_G0 = IOMUX_PAD(0x01d8, 0x01d8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE14__DCU0_G1 = IOMUX_PAD(0x01dc, 0x01dc, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE15__DCU0_G2 = IOMUX_PAD(0x01e0, 0x01e0, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE16__DCU0_G3 = IOMUX_PAD(0x01e4, 0x01e4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE17__DCU0_G4 = IOMUX_PAD(0x01e8, 0x01e8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE18__DCU0_G5 = IOMUX_PAD(0x01ec, 0x01ec, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE19__DCU0_G6 = IOMUX_PAD(0x01f0, 0x01f0, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE20__DCU0_G7 = IOMUX_PAD(0x01f4, 0x01f4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE21__DCU0_B0 = IOMUX_PAD(0x01f8, 0x01f8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE22__DCU0_B1 = IOMUX_PAD(0x01fc, 0x01fc, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE23__DCU0_B2 = IOMUX_PAD(0x0200, 0x0200, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE24__DCU0_B3 = IOMUX_PAD(0x0204, 0x0204, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE25__DCU0_B4 = IOMUX_PAD(0x0208, 0x0208, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE26__DCU0_B5 = IOMUX_PAD(0x020c, 0x020c, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE27__DCU0_B6 = IOMUX_PAD(0x0210, 0x0210, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+ VF610_PAD_PTE28__DCU0_B7 = IOMUX_PAD(0x0214, 0x0214, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+
VF610_PAD_DDR_RESETB = IOMUX_PAD(0x021c, 0x021c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h
index 7587cbb..ba0ed43 100644
--- a/arch/arm/include/asm/imx-common/iomux-v3.h
+++ b/arch/arm/include/asm/imx-common/iomux-v3.h
@@ -165,7 +165,10 @@
#define PAD_CTL_ODE (1 << 10)
#define PAD_CTL_DSE_150ohm (1 << 6)
+#define PAD_CTL_DSE_75ohm (2 << 6)
#define PAD_CTL_DSE_50ohm (3 << 6)
+#define PAD_CTL_DSE_37ohm (4 << 6)
+#define PAD_CTL_DSE_30ohm (5 << 6)
#define PAD_CTL_DSE_25ohm (6 << 6)
#define PAD_CTL_DSE_20ohm (7 << 6)
diff --git a/board/toradex/colibri_vf/Makefile b/board/toradex/colibri_vf/Makefile
index c7e5134..4d6287f 100644
--- a/board/toradex/colibri_vf/Makefile
+++ b/board/toradex/colibri_vf/Makefile
@@ -5,3 +5,4 @@
#
obj-y := colibri_vf.o
+obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o
diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c
index 7b74eb7..46dd15b 100644
--- a/board/toradex/colibri_vf/colibri_vf.c
+++ b/board/toradex/colibri_vf/colibri_vf.c
@@ -17,6 +17,7 @@
#include <mmc.h>
#include <fdt_support.h>
#include <fsl_esdhc.h>
+#include <fsl_dcu_fb.h>
#include <jffs2/load_kernel.h>
#include <miiphy.h>
#include <mtd_node.h>
@@ -295,6 +296,49 @@
}
#endif
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
+static void setup_iomux_fsl_dcu(void)
+{
+ static const iomux_v3_cfg_t dcu0_pads[] = {
+ VF610_PAD_PTE0__DCU0_HSYNC,
+ VF610_PAD_PTE1__DCU0_VSYNC,
+ VF610_PAD_PTE2__DCU0_PCLK,
+ VF610_PAD_PTE4__DCU0_DE,
+ VF610_PAD_PTE5__DCU0_R0,
+ VF610_PAD_PTE6__DCU0_R1,
+ VF610_PAD_PTE7__DCU0_R2,
+ VF610_PAD_PTE8__DCU0_R3,
+ VF610_PAD_PTE9__DCU0_R4,
+ VF610_PAD_PTE10__DCU0_R5,
+ VF610_PAD_PTE11__DCU0_R6,
+ VF610_PAD_PTE12__DCU0_R7,
+ VF610_PAD_PTE13__DCU0_G0,
+ VF610_PAD_PTE14__DCU0_G1,
+ VF610_PAD_PTE15__DCU0_G2,
+ VF610_PAD_PTE16__DCU0_G3,
+ VF610_PAD_PTE17__DCU0_G4,
+ VF610_PAD_PTE18__DCU0_G5,
+ VF610_PAD_PTE19__DCU0_G6,
+ VF610_PAD_PTE20__DCU0_G7,
+ VF610_PAD_PTE21__DCU0_B0,
+ VF610_PAD_PTE22__DCU0_B1,
+ VF610_PAD_PTE23__DCU0_B2,
+ VF610_PAD_PTE24__DCU0_B3,
+ VF610_PAD_PTE25__DCU0_B4,
+ VF610_PAD_PTE26__DCU0_B5,
+ VF610_PAD_PTE27__DCU0_B6,
+ VF610_PAD_PTE28__DCU0_B7,
+ };
+
+ imx_iomux_v3_setup_multiple_pads(dcu0_pads, ARRAY_SIZE(dcu0_pads));
+}
+
+static void setup_tcon(void)
+{
+ setbits_le32(TCON0_BASE_ADDR, (1 << 29));
+}
+#endif
+
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[1] = {
{ESDHC1_BASE_ADDR},
@@ -431,6 +475,11 @@
CCM_CSCDR3_NFC_PRE_DIV(3));
clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
CCM_CSCMR2_RMII_CLK_SEL(2));
+
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
+ setbits_le32(&ccm->ccgr1, CCM_CCGR1_TCON0_CTRL_MASK);
+ setbits_le32(&ccm->ccgr3, CCM_CCGR3_DCU0_CTRL_MASK);
+#endif
}
static void mscm_init(void)
@@ -470,6 +519,11 @@
setup_iomux_dspi();
#endif
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
+ setup_tcon();
+ setup_iomux_fsl_dcu();
+#endif
+
return 0;
}
@@ -478,22 +532,6 @@
{
struct src *src = (struct src *)SRC_BASE_ADDR;
- /* Default memory arguments */
- if (!getenv("memargs")) {
- switch (gd->ram_size) {
- case 0x08000000:
- /* 128 MB */
- setenv("memargs", "mem=128M");
- break;
- case 0x10000000:
- /* 256 MB */
- setenv("memargs", "mem=256M");
- break;
- default:
- printf("Failed detecting RAM size.\n");
- }
- }
-
if (((src->sbmr2 & SRC_SBMR2_BMOD_MASK) >> SRC_SBMR2_BMOD_SHIFT)
== SRC_SBMR2_BMOD_SERIAL) {
printf("Serial Downloader recovery mode, disable autoboot\n");
@@ -541,6 +579,7 @@
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd)
{
+ int ret = 0;
#ifdef CONFIG_FDT_FIXUP_PARTITIONS
static struct node_info nodes[] = {
{ "fsl,vf610-nfc", MTD_DEV_TYPE_NAND, }, /* NAND flash */
@@ -550,6 +589,11 @@
puts(" Updating MTD partitions...\n");
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
#endif
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
+ ret = fsl_dcu_fixedfb_setup(blob);
+ if (ret)
+ return ret;
+#endif
return ft_common_board_setup(blob, bd);
}
diff --git a/board/toradex/colibri_vf/dcu.c b/board/toradex/colibri_vf/dcu.c
new file mode 100644
index 0000000..3fa6a76
--- /dev/null
+++ b/board/toradex/colibri_vf/dcu.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2017 Toradex AG
+ *
+ * FSL DCU platform driver
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_dcu_fb.h>
+#include "div64.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int dcu_set_pixel_clock(unsigned int pixclock)
+{
+ struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+ unsigned long long div;
+
+ clrbits_le32(&ccm->cscmr1, CCM_CSCMR1_DCU0_CLK_SEL);
+ clrsetbits_le32(&ccm->cscdr3,
+ CCM_CSCDR3_DCU0_DIV_MASK | CCM_CSCDR3_DCU0_EN,
+ CCM_CSCDR3_DCU0_DIV(0) | CCM_CSCDR3_DCU0_EN);
+ div = (unsigned long long)(PLL1_PFD2_FREQ / 1000);
+ do_div(div, pixclock);
+
+ return div;
+}
+
+int platform_dcu_init(unsigned int xres, unsigned int yres,
+ const char *port,
+ struct fb_videomode *dcu_fb_videomode)
+{
+ fsl_dcu_init(xres, yres, 32);
+
+ return 0;
+}
diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig
index 0474abc..1f0f929 100644
--- a/configs/colibri_vf_defconfig
+++ b/configs/colibri_vf_defconfig
@@ -52,3 +52,7 @@
CONFIG_G_DNL_VENDOR_NUM=0x1b67
CONFIG_G_DNL_PRODUCT_NUM=0x4000
CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_FSL_DCU_FB=y
+CONFIG_SYS_CONSOLE_FG_COL=0x00
+CONFIG_SYS_CONSOLE_BG_COL=0x00
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index 73b43bd..5dc5ed0 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -25,6 +25,17 @@
#define CONFIG_MXC_OCOTP
#endif
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
+#define CONFIG_CMD_BMP
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_SYS_FSL_DCU_LE
+
+#define CONFIG_SYS_DCU_ADDR DCU0_BASE_ADDR
+#define DCU_LAYER_MAX_NUM 64
+#endif
+
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
@@ -130,6 +141,8 @@
"setupdate=run setsdupdate || run setusbupdate\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0" \
"dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \
+ "video-mode=dcufb:640x480-16@60,monitor=lcd\0" \
+ "splashpos=m,m\0" \
SD_BOOTCMD \
NFS_BOOTCMD \
UBI_BOOTCMD