| commit | 8376e0e6f74c5e86a821cb81990f2b9429a364f3 | [log] [tgz] |
|---|---|---|
| author | Marek Vasut <marek.vasut+renesas@gmail.com> | Thu May 31 19:06:02 2018 +0200 |
| committer | Marek Vasut <marek.vasut+renesas@gmail.com> | Fri Jun 01 09:42:13 2018 +0200 |
| tree | 17e9764522803d82ccfcf66cfadaabc74d9f9e56 | |
| parent | 15e091828592bf87d09a6e780eb9310628a9d79b [diff] |
clk: renesas: Pass clock rate around as 64bit number internally The PLL rate could be in the GHz range, which could overflow a 32bit data type. Since the hardware is 64bit anyway, pass the clock rates as 64bit number internally to avoid this. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>