[Blackfin][PATCH] code cleanup
diff --git a/cpu/bf533/cache.S b/cpu/bf533/cache.S
index 5dcc24f..03aebe4 100644
--- a/cpu/bf533/cache.S
+++ b/cpu/bf533/cache.S
@@ -11,7 +11,7 @@
P0 = R2;
P1 = R1;
CSYNC;
- 1:
+1:
IFLUSH[P0++];
CC = P0 < P1(iu);
IF CC JUMP 1b(bp);
@@ -41,10 +41,10 @@
P0.H = (IMEM_CONTROL >> 16);
R7 =[P0];
-/*
- * Clear the IMC bit , All valid bits in the instruction
- * cache are set to the invalid state
- */
+ /*
+ * Clear the IMC bit , All valid bits in the instruction
+ * cache are set to the invalid state
+ */
BITCLR(R7, IMC_P);
CLI R6;
/* SSYNC required before invalidating cache. */
@@ -80,10 +80,10 @@
P0.H = (DMEM_CONTROL >> 16);
R7 =[P0];
-/*
- * Clear the DMC[1:0] bits, All valid bits in the data
- * cache are set to the invalid state
- */
+ /*
+ * Clear the DMC[1:0] bits, All valid bits in the data
+ * cache are set to the invalid state
+ */
BITCLR(R7, DMC0_P);
BITCLR(R7, DMC1_P);
CLI R6;
@@ -118,11 +118,11 @@
CC = P0 < P1(iu);
IF CC JUMP 1b(bp);
-/*
- * If the data crosses a cache line, then we'll be pointing to
- * the last cache line, but won't have flushed/invalidated it yet, so do
- * one more.
- */
+ /*
+ * If the data crosses a cache line, then we'll be pointing to
+ * the last cache line, but won't have flushed/invalidated it yet, so do
+ * one more.
+ */
FLUSHINV[P0];
SSYNC;
RTS;