* Patches by Travis Sawyer, 12 Mar 2004:
- Fix Gigabit Ethernet support for 440GX
- Add Gigabit Ethernet Support to MII PHY utilities
* Patch by Brad Kemp, 12 Mar 2004:
Fixes for drivers/cfi_flash.c:
- Better support for x8/x16 implementations
- Added failure for AMD chips attempting to use CFG_FLASH_USE_BUFFER_WRITE
- Added defines for AMD command and address constants
* Patch by Leon Kukovec, 12 Mar 2004:
Fix get_dentfromdir() to correctly handle deleted dentries
* Patch by George G. Davis, 11 Mar 2004:
Remove hard coded network settings in TI OMAP1610 H2
default board config
* Patch by George G. Davis, 11 Mar 2004:
add support for ADS GraphicsClient+ board.
diff --git a/drivers/cfi_flash.c b/drivers/cfi_flash.c
index 7a7575b..df6cb73 100644
--- a/drivers/cfi_flash.c
+++ b/drivers/cfi_flash.c
@@ -101,9 +101,14 @@
#define AMD_CMD_WRITE 0xA0
#define AMD_CMD_ERASE_START 0x80
#define AMD_CMD_ERASE_SECTOR 0x30
+#define AMD_CMD_UNLOCK_START 0xAA
+#define AMD_CMD_UNLOCK_ACK 0x55
#define AMD_STATUS_TOGGLE 0x40
#define AMD_STATUS_ERROR 0x20
+#define AMD_ADDR_ERASE_START 0x555
+#define AMD_ADDR_START 0x555
+#define AMD_ADDR_ACK 0x2AA
#define FLASH_OFFSET_CFI 0x55
#define FLASH_OFFSET_CFI_RESP 0x10
@@ -377,7 +382,8 @@
case CFI_CMDSET_AMD_STANDARD:
case CFI_CMDSET_AMD_EXTENDED:
flash_unlock_seq (info, sect);
- flash_write_cmd (info, sect, 0x555, AMD_CMD_ERASE_START);
+ flash_write_cmd (info, sect, AMD_ADDR_ERASE_START,
+ AMD_CMD_ERASE_START);
flash_unlock_seq (info, sect);
flash_write_cmd (info, sect, 0, AMD_CMD_ERASE_SECTOR);
break;
@@ -479,24 +485,6 @@
#ifdef CFG_FLASH_USE_BUFFER_WRITE
int buffered_size;
#endif
- int x8mode = 0;
-
- /* special handling of 16 bit devices in 8 bit mode */
- if ((info->interface == FLASH_CFI_X8X16)
- && (info->chipwidth == FLASH_CFI_BY8)) {
- switch (info->vendor) {
- case CFI_CMDSET_INTEL_STANDARD:
- case CFI_CMDSET_INTEL_EXTENDED:
- x8mode = info->portwidth;
- info->portwidth >>= 1; /* XXX - Need to test on x9/x16 in parallel. */
- /*info->portwidth = FLASH_CFI_8BIT; */ /* XXX - Need to test on x9/x16 in parallel. */
- break;
- case CFI_CMDSET_AMD_STANDARD:
- case CFI_CMDSET_AMD_EXTENDED:
- default:
- break;
- }
- }
/* get lower aligned address */
/* get lower aligned address */
wp = (addr & ~(info->portwidth - 1));
@@ -560,10 +548,6 @@
flash_add_byte (info, &cword, (*(uchar *) cp));
}
- /* special handling of 16 bit devices in 8 bit mode */
- if (x8mode) {
- info->portwidth = x8mode;;
- }
return flash_write_cfiword (info, wp, cword);
}
@@ -847,8 +831,8 @@
static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect)
{
- flash_write_cmd (info, sect, 0x555, 0xAA);
- flash_write_cmd (info, sect, 0x2AA, 0x55);
+ flash_write_cmd (info, sect, AMD_ADDR_START, AMD_CMD_UNLOCK_START);
+ flash_write_cmd (info, sect, AMD_ADDR_ACK, AMD_CMD_UNLOCK_ACK);
}
/*-----------------------------------------------------------------------
@@ -1078,6 +1062,9 @@
tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT);
info->write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WMAX_TOUT))) / 1000;
info->flash_id = FLASH_MAN_CFI;
+ if ((info->interface == FLASH_CFI_X8X16) && (info->chipwidth == FLASH_CFI_BY8)) {
+ info->portwidth >>= 1; /* XXX - Need to test on x8/x16 in parallel. */
+ }
}
flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
@@ -1131,7 +1118,7 @@
case CFI_CMDSET_AMD_EXTENDED:
case CFI_CMDSET_AMD_STANDARD:
flash_unlock_seq (info, 0);
- flash_write_cmd (info, 0, 0x555, AMD_CMD_WRITE);
+ flash_write_cmd (info, 0, AMD_ADDR_START, AMD_CMD_WRITE);
break;
}
@@ -1182,6 +1169,10 @@
int retcode;
volatile cfiptr_t src;
volatile cfiptr_t dst;
+ /* buffered writes in the AMD chip set is not supported yet */
+ if((info->vendor == CFI_CMDSET_AMD_STANDARD) ||
+ (info->vendor == CFI_CMDSET_AMD_EXTENDED))
+ return ERR_INVAL;
src.cp = cp;
dst.cp = (uchar *) dest;