arm: add support for PDU001
This patch adds support for the PDU001 board.
Signed-off-by: Felix Brack <fb@ltec.ch>
Reviewed-by: Tom Rini <trini@konsulko.com>
diff --git a/board/eets/pdu001/Kconfig b/board/eets/pdu001/Kconfig
new file mode 100644
index 0000000..6217a8f
--- /dev/null
+++ b/board/eets/pdu001/Kconfig
@@ -0,0 +1,66 @@
+# Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+if TARGET_PDU001
+
+config SYS_BOARD
+ default "pdu001"
+
+config SYS_VENDOR
+ default "eets"
+
+config SYS_SOC
+ default "am33xx"
+
+config SYS_CONFIG_NAME
+ default "pdu001"
+
+config CONS_INDEX
+ int "UART used for console"
+ range 1 6
+ default 4
+ help
+ The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced
+ in documentation, etc) available to it. The best choice for the
+ PDU001 is UART3 as it is wired to the header K2; enter 4 here to
+ use UART3. UART0 is connected to the EIA-485 transceiver. If you
+ really need to use it, you are advised to remove the transceiver U14
+ from the board. UART1 is wired to the backplane and therefore
+ accessible from there or by the backplane connector K1 of the PDU.
+ Any other UART then UART3 (enter 4 here), UART1 (enter 2 here) or
+ UART0 (enter 1 here) are not sensible since they are not wired to
+ any connector and therefore difficult to access.
+
+choice
+ prompt "State of Run LED"
+ default PDU001_RUN_LED_RED
+ help
+ The PDU001 has a bi-color (red/green) LED labeled 'Run' which
+ can be used to indicate the operating state of the board. By
+ default it will be lit red by U-Boot. Later in the start-up
+ process it can be changed to green (or heartbeat or anything else)
+ by the kernel or some other software.
+
+config RUN_LED_RED
+ bool
+ prompt "Red"
+ help
+ Lit Run LED red.
+
+config RUN_LED_GREEN
+ bool
+ prompt "Green"
+ help
+ Lit Run LED green.
+
+config RUN_LED_OFF
+ bool
+ prompt "Off"
+ help
+ Do not lit Run LED.
+
+endchoice
+
+endif
diff --git a/board/eets/pdu001/MAINTAINERS b/board/eets/pdu001/MAINTAINERS
new file mode 100644
index 0000000..95295dd
--- /dev/null
+++ b/board/eets/pdu001/MAINTAINERS
@@ -0,0 +1,6 @@
+PDU001 BOARD
+M: Felix Brack <fb@ltec.ch>
+S: Maintained
+F: board/eets/pdu001/
+F: include/configs/pdu001.h
+F: configs/am335x_pdu001_defconfig
diff --git a/board/eets/pdu001/Makefile b/board/eets/pdu001/Makefile
new file mode 100644
index 0000000..08c6d53
--- /dev/null
+++ b/board/eets/pdu001/Makefile
@@ -0,0 +1,13 @@
+#
+# Makefile
+#
+# Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
+obj-y := mux.o
+endif
+
+obj-y += board.o
diff --git a/board/eets/pdu001/README b/board/eets/pdu001/README
new file mode 100644
index 0000000..50e7154
--- /dev/null
+++ b/board/eets/pdu001/README
@@ -0,0 +1,35 @@
+# Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+Summary
+=======
+
+This document covers the PDU001 target.
+
+Hardware
+========
+
+The PDU-001 (Processor and Display Unit) is a plugin card for 19" racks. It is
+manufactured by EETS GmbH (https://www.eets.ch). The core of the board is a m2
+SOM from bytes at work (https://www.bytesatwork.ch) which in turn is based on
+AM3352 SOC from TI (http://www.ti.com).
+
+Customization
+=============
+
+As usual the console serial interface is set by CONFIG_CONS_INDEX. Best choice
+is 4 here since UART3 is wired to the connector K2.
+The Run LED on the PDU-001 can be turned on red by setting CONFIG_RUN_LED_RED
+or green by setting CONFIG_RUN_LED_GREEN. Setting CONFIG_RUN_LED_OFF will turn
+off the Run LED.
+
+Booting
+=======
+
+The system boots from either eMMC or SD card cage. It will first try to boot
+from the SD card cage. If this fails (missing or unbootable SD card) it will
+try to boot from the internal eMMC. The root file system is always expected to
+be located in the second partition of the device (eMMC or SD card) that pro-
+vided the boot loader.
diff --git a/board/eets/pdu001/board.c b/board/eets/pdu001/board.c
new file mode 100644
index 0000000..416bd93
--- /dev/null
+++ b/board/eets/pdu001/board.c
@@ -0,0 +1,276 @@
+/*
+ * board.c
+ *
+ * Board functions for EETS PDU001 board
+ *
+ * Copyright (C) 2018, EETS GmbH, http://www.eets.ch/
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <i2c.h>
+#include <environment.h>
+#include <watchdog.h>
+#include <debug_uart.h>
+#include <dm/ofnode.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define I2C_ADDR_NODE_ID 0x50
+#define I2C_REG_NODE_ID_BASE 0xfa
+#define NODE_ID_BYTE_COUNT 6
+
+#define I2C_ADDR_LEDS 0x60
+#define I2C_REG_RUN_LED 0x06
+#define RUN_LED_OFF 0x0
+#define RUN_LED_RED 0x1
+#define RUN_LED_GREEN (0x1 << 2)
+
+#define VDD_MPU_REGULATOR "regulator@2"
+#define VDD_CORE_REGULATOR "regulator@3"
+#define DEFAULT_CORE_VOLTAGE 1137500
+
+/*
+ * boot device save register
+ * -------------------------
+ * The boot device can be quired by 'spl_boot_device()' in
+ * 'am33xx_spl_board_init'. However it can't be saved in the u-boot
+ * environment here. In turn 'spl_boot_device' can't be called in
+ * 'board_late_init' which allows writing to u-boot environment.
+ * To get the boot device from 'am33xx_spl_board_init' to
+ * 'board_late_init' we therefore use a scratch register from the RTC.
+ */
+#define CONFIG_SYS_RTC_SCRATCH0 0x60
+#define BOOT_DEVICE_SAVE_REGISTER (RTC_BASE + CONFIG_SYS_RTC_SCRATCH0)
+
+#ifdef CONFIG_SPL_BUILD
+static void save_boot_device(void)
+{
+ *((u32 *)(BOOT_DEVICE_SAVE_REGISTER)) = spl_boot_device();
+}
+#endif
+
+u32 boot_device(void)
+{
+ return *((u32 *)(BOOT_DEVICE_SAVE_REGISTER));
+}
+
+/* Store the boot device in the environment variable 'boot_device' */
+static void env_set_boot_device(void)
+{
+ switch (boot_device()) {
+ case BOOT_DEVICE_MMC1: {
+ env_set("boot_device", "emmc");
+ break;
+ }
+ case BOOT_DEVICE_MMC2: {
+ env_set("boot_device", "sdcard");
+ break;
+ }
+ default: {
+ env_set("boot_device", "unknown");
+ break;
+ }
+ }
+}
+
+static void set_run_led(struct udevice *dev)
+{
+ int val = RUN_LED_OFF;
+
+ if (IS_ENABLED(CONFIG_RUN_LED_RED))
+ val = RUN_LED_RED;
+ else if (IS_ENABLED(CONFIG_RUN_LED_GREEN))
+ val = RUN_LED_GREEN;
+
+ dm_i2c_reg_write(dev, I2C_REG_RUN_LED, val);
+}
+
+/* Set 'serial#' to the EUI-48 value of board node ID chip */
+static void env_set_serial(struct udevice *dev)
+{
+ int val;
+ char serial[2 * NODE_ID_BYTE_COUNT + 1];
+ int n;
+
+ for (n = 0; n < sizeof(serial); n += 2) {
+ val = dm_i2c_reg_read(dev, I2C_REG_NODE_ID_BASE + n / 2);
+ sprintf(serial + n, "%02X", val);
+ }
+ serial[2 * NODE_ID_BYTE_COUNT] = '\0';
+ env_set("serial#", serial);
+}
+
+static void set_mpu_and_core_voltage(void)
+{
+ int mpu_vdd;
+ int sil_rev;
+ struct udevice *dev;
+ struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+ /*
+ * The PDU001 (more precisely the computing module m2) uses a
+ * TPS65910 PMIC. For all MPU frequencies we support we use a CORE
+ * voltage of 1.1375V. For MPU voltage we need to switch based on
+ * the frequency we are running at.
+ */
+
+ /*
+ * Depending on MPU clock and PG we will need a different VDD
+ * to drive at that speed.
+ */
+ sil_rev = readl(&cdev->deviceid) >> 28;
+ mpu_vdd = am335x_get_mpu_vdd(sil_rev, dpll_mpu_opp100.m);
+
+ /* first update the MPU voltage */
+ if (!regulator_get_by_devname(VDD_MPU_REGULATOR, &dev)) {
+ if (regulator_set_value(dev, mpu_vdd))
+ debug("failed to set MPU voltage\n");
+ } else {
+ debug("invalid MPU voltage ragulator %s\n", VDD_MPU_REGULATOR);
+ }
+
+ /* second update the CORE voltage */
+ if (!regulator_get_by_devname(VDD_CORE_REGULATOR, &dev)) {
+ if (regulator_set_value(dev, DEFAULT_CORE_VOLTAGE))
+ debug("failed to set CORE voltage\n");
+ } else {
+ debug("invalid CORE voltage ragulator %s\n",
+ VDD_CORE_REGULATOR);
+ }
+}
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+static const struct ddr_data ddr2_data = {
+ .datardsratio0 = MT47H128M16RT25E_RD_DQS,
+ .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
+ .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr2_cmd_ctrl_data = {
+ .cmd0csratio = MT47H128M16RT25E_RATIO,
+ .cmd1csratio = MT47H128M16RT25E_RATIO,
+ .cmd2csratio = MT47H128M16RT25E_RATIO,
+};
+
+static const struct emif_regs ddr2_emif_reg_data = {
+ .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
+ .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
+ .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
+ .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
+ .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
+ .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
+};
+
+#define OSC (V_OSCK / 1000000)
+const struct dpll_params dpll_ddr = {
+ 266, OSC - 1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_ddr_evm_sk = {
+ 303, OSC - 1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_ddr_bone_black = {
+ 400, OSC - 1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+ struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+ /* Get the frequency */
+ dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+
+ /* Set CORE Frequencies to OPP100 */
+ do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+ /* Set MPU Frequency to what we detected now that voltages are set */
+ do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+
+ /* save boot device for later use by 'board_late_init' */
+ save_boot_device();
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+ enable_i2c0_pin_mux();
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+
+ return &dpll_ddr;
+}
+
+void set_mux_conf_regs(void)
+{
+ /* done first by the ROM and afterwards by the pin controller driver */
+ enable_i2c0_pin_mux();
+}
+
+const struct ctrl_ioregs ioregs = {
+ .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
+ .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
+ .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
+ .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
+ .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
+};
+
+void sdram_init(void)
+{
+ config_ddr(266, &ioregs, &ddr2_data,
+ &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
+}
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+
+#ifdef CONFIG_DEBUG_UART
+void board_debug_uart_init(void)
+{
+ /* done by pin controller driver if not debugging */
+ enable_uart_pin_mux(CONFIG_DEBUG_UART_BASE);
+}
+#endif
+
+/*
+ * Basic board specific setup. Pinmux has been handled already.
+ */
+int board_init(void)
+{
+#ifdef CONFIG_HW_WATCHDOG
+ hw_watchdog_init();
+#endif
+
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ struct udevice *dev;
+
+ set_mpu_and_core_voltage();
+ env_set_boot_device();
+
+ /* second I2C bus connects to node ID and front panel LED chip */
+ if (!i2c_get_chip_for_busnum(1, I2C_ADDR_LEDS, 1, &dev))
+ set_run_led(dev);
+ if (!i2c_get_chip_for_busnum(1, I2C_ADDR_NODE_ID, 1, &dev))
+ env_set_serial(dev);
+
+ return 0;
+}
+#endif
diff --git a/board/eets/pdu001/board.h b/board/eets/pdu001/board.h
new file mode 100644
index 0000000..3474e6a
--- /dev/null
+++ b/board/eets/pdu001/board.h
@@ -0,0 +1,38 @@
+/*
+ * board.h
+ *
+ * EETS GmbH PDU001 board information header
+ *
+ * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * We have two pin mux functions that must exist. First we need I2C0 to
+ * access the TPS65910 PMIC located on the M2 computing module.
+ * Second, if we want low-level debugging or a early UART (ie. before the
+ * pin controller driver is running), we need one of the UART ports UART0 to
+ * UART5 (usually UART3 since it is wired to K2).
+ * In case of I2C0 access we explicitly don't rely on the the ROM but we could
+ * do so as we use the primary mode (mode 0) for I2C0.
+ * All other multiplexing and pin configuration is done by the DT once it
+ * gets parsed by the pin controller driver.
+ * However we relay on the ROM to configure the pins of MMC0 (eMMC) as well
+ * as MMC1 (microSD card-cage) since these are our boot devices.
+ */
+void enable_uart0_pin_mux(void);
+void enable_uart1_pin_mux(void);
+void enable_uart2_pin_mux(void);
+void enable_uart3_pin_mux(void);
+void enable_uart4_pin_mux(void);
+void enable_uart5_pin_mux(void);
+void enable_uart_pin_mux(u32 addr);
+void enable_i2c0_pin_mux(void);
+
+#endif
diff --git a/board/eets/pdu001/mux.c b/board/eets/pdu001/mux.c
new file mode 100644
index 0000000..bf2c8df
--- /dev/null
+++ b/board/eets/pdu001/mux.c
@@ -0,0 +1,120 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart1_pin_mux[] = {
+ {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
+ {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart2_pin_mux[] = {
+ {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
+ {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart3_pin_mux[] = {
+ {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
+ {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart4_pin_mux[] = {
+ {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
+ {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
+ {-1},
+};
+
+static struct module_pin_mux uart5_pin_mux[] = {
+ {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
+ {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
+ {-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+ {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
+ {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
+ {-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_uart1_pin_mux(void)
+{
+ configure_module_pin_mux(uart1_pin_mux);
+}
+
+void enable_uart2_pin_mux(void)
+{
+ configure_module_pin_mux(uart2_pin_mux);
+}
+
+void enable_uart3_pin_mux(void)
+{
+ configure_module_pin_mux(uart3_pin_mux);
+}
+
+void enable_uart4_pin_mux(void)
+{
+ configure_module_pin_mux(uart4_pin_mux);
+}
+
+void enable_uart5_pin_mux(void)
+{
+ configure_module_pin_mux(uart5_pin_mux);
+}
+
+void enable_uart_pin_mux(u32 addr)
+{
+ switch (addr) {
+ case CONFIG_SYS_NS16550_COM1:
+ enable_uart0_pin_mux();
+ break;
+ case CONFIG_SYS_NS16550_COM2:
+ enable_uart1_pin_mux();
+ break;
+ case CONFIG_SYS_NS16550_COM3:
+ enable_uart2_pin_mux();
+ break;
+ case CONFIG_SYS_NS16550_COM4:
+ enable_uart3_pin_mux();
+ break;
+ case CONFIG_SYS_NS16550_COM5:
+ enable_uart4_pin_mux();
+ break;
+ case CONFIG_SYS_NS16550_COM6:
+ enable_uart5_pin_mux();
+ break;
+ }
+}
+
+void enable_i2c0_pin_mux(void)
+{
+ configure_module_pin_mux(i2c0_pin_mux);
+}