rockchip: clk: rk3328: add ciu_clk entry for eMMC/SDMMC
The genunie bus clock is sclk_x for eMMC/SDMMC, add support for it.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c
index 0ff1e30..8ec1574 100644
--- a/drivers/clk/rockchip/clk_rk3328.c
+++ b/drivers/clk/rockchip/clk_rk3328.c
@@ -397,9 +397,11 @@
switch (clk_id) {
case HCLK_SDMMC:
+ case SCLK_SDMMC:
con_id = 30;
break;
case HCLK_EMMC:
+ case SCLK_EMMC:
con_id = 32;
break;
default:
@@ -423,9 +425,11 @@
switch (clk_id) {
case HCLK_SDMMC:
+ case SCLK_SDMMC:
con_id = 30;
break;
case HCLK_EMMC:
+ case SCLK_EMMC:
con_id = 32;
break;
default:
@@ -483,6 +487,8 @@
return 0;
case HCLK_SDMMC:
case HCLK_EMMC:
+ case SCLK_SDMMC:
+ case SCLK_EMMC:
rate = rk3328_mmc_get_clk(priv->cru, clk->id);
break;
case SCLK_I2C0:
@@ -511,6 +517,8 @@
return 0;
case HCLK_SDMMC:
case HCLK_EMMC:
+ case SCLK_SDMMC:
+ case SCLK_EMMC:
ret = rk3328_mmc_set_clk(priv->cru, clk->id, rate);
break;
case SCLK_I2C0: