commit 862e2e75e8f317ff8bd660550d7da3fede2ead09
author Lukas Auer <lukas.auer@aisec.fraunhofer.de> Thu Nov 22 11:26:12 2018 +0100
committer Andes <uboot@andestech.com> Mon Nov 26 13:57:29 2018 +0800
tree 1c7affaf8b45a246101e92d149e5abc1c85267c1
parent 17f2ffea36bf9d2ef7238cfd52b8872cbb50034a

riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I

RISC-V defines the base integer instruction sets as RV32I and RV64I.
Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_RV64I to
match this convention.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>

configs/qemu-riscv64_defconfig

diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig
index d6c1a5d..60b647e 100644
--- a/configs/qemu-riscv64_defconfig
+++ b/configs/qemu-riscv64_defconfig
@@ -1,6 +1,6 @@
 CONFIG_RISCV=y
 CONFIG_TARGET_QEMU_VIRT=y
-CONFIG_CPU_RISCV_64=y
+CONFIG_ARCH_RV64I=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DISPLAY_CPUINFO=y
 CONFIG_DISPLAY_BOARDINFO=y