| commit | 882f80b993f3719cce5bfa7f1bca9b1b23062b5f | [log] [tgz] |
|---|---|---|
| author | Aneesh V <aneesh@ti.com> | Thu Aug 11 04:35:44 2011 +0000 |
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | Sun Sep 04 11:36:16 2011 +0200 |
| tree | ba83eab86729a1871261d10512178ccc1d2c9a65 | |
| parent | 13d4f9bd7477b3b409f3e267b3b3d6fed5bd3e30 [diff] |
armv7: stronger barrier for cache-maintenance operations set-way operations need a DSB after them to ensure the operation is complete. DMB may not be enough. Use DSB after all operations instead of DMB. Signed-off-by: Aneesh V <aneesh@ti.com>