clk: microchip: mpfs: fix periph clk parentage
Not all "periph" clocks are children of the AHB clock, some have the AXI
clock as their parent & the mtimer clock is derived from the external
reference clock directly. Stop assuming the AHB clock to be the parent
of all "periph" clocks and define their correct parents instead.
Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
diff --git a/drivers/clk/microchip/mpfs_clk.c b/drivers/clk/microchip/mpfs_clk.c
index f16f716..08f8bfc 100644
--- a/drivers/clk/microchip/mpfs_clk.c
+++ b/drivers/clk/microchip/mpfs_clk.c
@@ -19,7 +19,6 @@
static int mpfs_clk_probe(struct udevice *dev)
{
struct clk *parent_clk = dev_get_priv(dev);
- struct clk clk_ahb = { .id = CLK_AHB };
struct clk clk_msspll = { .id = CLK_MSSPLL };
void __iomem *base;
void __iomem *msspll_base;
@@ -56,8 +55,7 @@
if (ret)
return ret;
- clk_request(dev, &clk_ahb);
- ret = mpfs_clk_register_periphs(base, &clk_ahb);
+ ret = mpfs_clk_register_periphs(base, dev);
return ret;
}