* Code cleanup:
- remove trailing white space, trailing empty lines, C++ comments, etc.
- split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c)
* Patches by Kenneth Johansson, 25 Jun 2003:
- major rework of command structure
(work done mostly by Michal Cendrowski and Joakim Kristiansen)
diff --git a/board/csb226/Makefile b/board/csb226/Makefile
index e6bf4ea..ac94642 100644
--- a/board/csb226/Makefile
+++ b/board/csb226/Makefile
@@ -29,7 +29,7 @@
SOBJS := memsetup.o
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+ $(AR) crv $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
diff --git a/board/csb226/config.mk b/board/csb226/config.mk
index 939ffff..2354392 100644
--- a/board/csb226/config.mk
+++ b/board/csb226/config.mk
@@ -13,4 +13,3 @@
# for the addresses _after_ relocation to RAM!! Otherwhise the
# .bss segment is assumed in flash...
TEXT_BASE = 0xa1fe0000
-
diff --git a/board/csb226/csb226.c b/board/csb226/csb226.c
index a79d168..bf9b4f8 100644
--- a/board/csb226/csb226.c
+++ b/board/csb226/csb226.c
@@ -32,15 +32,15 @@
# define SHOW_BOOT_PROGRESS(arg)
#endif
-/**
+/**
* misc_init_r: - misc initialisation routines
*/
int misc_init_r(void)
{
-#if 0
+#if 0
uchar *str;
-
+
/* determine if the software update key is pressed during startup */
/* not ported yet... */
if (GPLR0 & 0x00000800) {
@@ -52,15 +52,15 @@
}
setenv("bootcmd",str);
-#endif
+#endif
return 0;
-}
+}
-/**
+/**
* board_init: - setup some data structures
*
- * @return: 0 in case of success
+ * @return: 0 in case of success
*/
int board_init (void)
@@ -80,7 +80,7 @@
}
-/**
+/**
* dram_init: - setup dynamic RAM
*
* @return: 0 in case of success
@@ -97,7 +97,7 @@
}
-/**
+/**
* csb226_set_led: - switch LEDs on or off
*
* @param led: LED to switch (0,1,2)
@@ -108,26 +108,26 @@
{
switch(led) {
- case 0: if (state==1) {
- GPCR0 |= CSB226_USER_LED0;
+ case 0: if (state==1) {
+ GPCR0 |= CSB226_USER_LED0;
} else if (state==0) {
GPSR0 |= CSB226_USER_LED0;
}
break;
case 1: if (state==1) {
- GPCR0 |= CSB226_USER_LED1;
- } else if (state==0) {
- GPSR0 |= CSB226_USER_LED1;
- }
- break;
+ GPCR0 |= CSB226_USER_LED1;
+ } else if (state==0) {
+ GPSR0 |= CSB226_USER_LED1;
+ }
+ break;
case 2: if (state==1) {
- GPCR0 |= CSB226_USER_LED2;
- } else if (state==0) {
- GPSR0 |= CSB226_USER_LED2;
- }
- break;
+ GPCR0 |= CSB226_USER_LED2;
+ } else if (state==0) {
+ GPSR0 |= CSB226_USER_LED2;
+ }
+ break;
}
return;
@@ -137,10 +137,10 @@
/**
* show_boot_progress: - indicate state of the boot process
*
- * @param status: Status number - see README for details.
+ * @param status: Status number - see README for details.
*
- * The CSB226 does only have 3 LEDs, so we switch them on at the most
- * important states (1, 5, 15).
+ * The CSB226 does only have 3 LEDs, so we switch them on at the most
+ * important states (1, 5, 15).
*/
void show_boot_progress (int status)
@@ -153,4 +153,3 @@
return;
}
-
diff --git a/board/csb226/flash.c b/board/csb226/flash.c
index 0ee78e6..9801773 100644
--- a/board/csb226/flash.c
+++ b/board/csb226/flash.c
@@ -7,7 +7,7 @@
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
- * Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de>
+ * Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de>
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -89,7 +89,7 @@
/**
* flash_print_info: - print information about the flash situation
*
- * @param info:
+ * @param info:
*/
void flash_print_info (flash_info_t *info)
@@ -118,13 +118,13 @@
return;
}
- printf(" Size: %ld MB in %d Sectors\n",
+ printf(" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf(" Sector Start Addresses:");
for (i = 0; i < info->sector_count; i++) {
if ((i % 5) == 0) printf ("\n ");
-
+
printf (" %08lX%s", info->start[i],
info->protect[i] ? " (RO)" : " ");
}
@@ -153,7 +153,7 @@
if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK))
return ERR_UNKNOWN_FLASH_VENDOR;
-
+
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
if (info->protect[sect]) prot++;
@@ -203,7 +203,7 @@
*addr = 0x00FF00FF; /* resest to read mode */
}
-
+
printf("ok.\n");
}
@@ -222,10 +222,10 @@
/**
* write_word: - copy memory to flash
- *
+ *
* @param info:
* @param dest:
- * @param data:
+ * @param data:
* @return:
*/
@@ -301,8 +301,8 @@
/**
* write_buf: - Copy memory to flash.
- *
- * @param info:
+ *
+ * @param info:
* @param src: source of copy transaction
* @param addr: where to copy to
* @param cnt: number of bytes to copy
@@ -372,4 +372,3 @@
return write_word(info, wp, data);
}
-
diff --git a/board/csb226/memsetup.S b/board/csb226/memsetup.S
index 60f9d50..68577ca 100644
--- a/board/csb226/memsetup.S
+++ b/board/csb226/memsetup.S
@@ -159,7 +159,7 @@
mem_init:
- ldr r1, =MEMC_BASE /* get memory controller base addr. */
+ ldr r1, =MEMC_BASE /* get memory controller base addr. */
/* ---------------------------------------------------------------- */
/* Step 2a: Initialize Asynchronous static memory controller */
@@ -167,65 +167,65 @@
/* MSC registers: timing, bus width, mem type */
- /* MSC0: nCS(0,1) */
- ldr r2, =CFG_MSC0_VAL
- str r2, [r1, #MSC0_OFFSET]
- ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
+ /* MSC0: nCS(0,1) */
+ ldr r2, =CFG_MSC0_VAL
+ str r2, [r1, #MSC0_OFFSET]
+ ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
/* that data latches */
- /* MSC1: nCS(2,3) */
- ldr r2, =CFG_MSC1_VAL
- str r2, [r1, #MSC1_OFFSET]
- ldr r2, [r1, #MSC1_OFFSET]
+ /* MSC1: nCS(2,3) */
+ ldr r2, =CFG_MSC1_VAL
+ str r2, [r1, #MSC1_OFFSET]
+ ldr r2, [r1, #MSC1_OFFSET]
/* MSC2: nCS(4,5) */
- ldr r2, =CFG_MSC2_VAL
- str r2, [r1, #MSC2_OFFSET]
- ldr r2, [r1, #MSC2_OFFSET]
+ ldr r2, =CFG_MSC2_VAL
+ str r2, [r1, #MSC2_OFFSET]
+ ldr r2, [r1, #MSC2_OFFSET]
/* ---------------------------------------------------------------- */
/* Step 2b: Initialize Card Interface */
/* ---------------------------------------------------------------- */
/* MECR: Memory Expansion Card Register */
- ldr r2, =CFG_MECR_VAL
- str r2, [r1, #MECR_OFFSET]
+ ldr r2, =CFG_MECR_VAL
+ str r2, [r1, #MECR_OFFSET]
ldr r2, [r1, #MECR_OFFSET]
/* MCMEM0: Card Interface slot 0 timing */
- ldr r2, =CFG_MCMEM0_VAL
- str r2, [r1, #MCMEM0_OFFSET]
+ ldr r2, =CFG_MCMEM0_VAL
+ str r2, [r1, #MCMEM0_OFFSET]
ldr r2, [r1, #MCMEM0_OFFSET]
- /* MCMEM1: Card Interface slot 1 timing */
- ldr r2, =CFG_MCMEM1_VAL
- str r2, [r1, #MCMEM1_OFFSET]
+ /* MCMEM1: Card Interface slot 1 timing */
+ ldr r2, =CFG_MCMEM1_VAL
+ str r2, [r1, #MCMEM1_OFFSET]
ldr r2, [r1, #MCMEM1_OFFSET]
/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
- ldr r2, =CFG_MCATT0_VAL
- str r2, [r1, #MCATT0_OFFSET]
+ ldr r2, =CFG_MCATT0_VAL
+ str r2, [r1, #MCATT0_OFFSET]
ldr r2, [r1, #MCATT0_OFFSET]
/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
- ldr r2, =CFG_MCATT1_VAL
- str r2, [r1, #MCATT1_OFFSET]
+ ldr r2, =CFG_MCATT1_VAL
+ str r2, [r1, #MCATT1_OFFSET]
ldr r2, [r1, #MCATT1_OFFSET]
/* MCIO0: Card Interface I/O Space Timing, slot 0 */
- ldr r2, =CFG_MCIO0_VAL
- str r2, [r1, #MCIO0_OFFSET]
+ ldr r2, =CFG_MCIO0_VAL
+ str r2, [r1, #MCIO0_OFFSET]
ldr r2, [r1, #MCIO0_OFFSET]
/* MCIO1: Card Interface I/O Space Timing, slot 1 */
- ldr r2, =CFG_MCIO1_VAL
- str r2, [r1, #MCIO1_OFFSET]
+ ldr r2, =CFG_MCIO1_VAL
+ str r2, [r1, #MCIO1_OFFSET]
ldr r2, [r1, #MCIO1_OFFSET]
/* ---------------------------------------------------------------- */
- /* Step 2c: Write FLYCNFG FIXME: what's that??? */
- /* ---------------------------------------------------------------- */
+ /* Step 2c: Write FLYCNFG FIXME: what's that??? */
+ /* ---------------------------------------------------------------- */
- /* test if we run from flash or RAM - RAM/BDI: don't setup RAM */
+ /* test if we run from flash or RAM - RAM/BDI: don't setup RAM */
adr r3, mem_init /* r0 <- current position of code */
ldr r2, =mem_init
cmp r3, r2 /* skip init if in place */
@@ -233,8 +233,8 @@
/* ---------------------------------------------------------------- */
- /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
- /* ---------------------------------------------------------------- */
+ /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
+ /* ---------------------------------------------------------------- */
/* Before accessing MDREFR we need a valid DRI field, so we set */
/* this to power on defaults + DRI field. */
@@ -246,7 +246,7 @@
orr r4, r4, r3
str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
/* ---------------------------------------------------------------- */
@@ -262,9 +262,9 @@
/* FIXME: we use async mode for now */
- /* ---------------------------------------------------------------- */
- /* Step 4: Initialize SDRAM */
- /* ---------------------------------------------------------------- */
+ /* ---------------------------------------------------------------- */
+ /* Step 4: Initialize SDRAM */
+ /* ---------------------------------------------------------------- */
/* Step 4a: assert MDREFR:K?RUN and configure */
/* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */
@@ -277,16 +277,16 @@
bic r4, r4, #(MDREFR_SLFRSH)
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
+ str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+ ldr r4, [r1, #MDREFR_OFFSET]
/* Step 4c: assert MDREFR:E1PIN and E0PIO */
orr r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN)
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
+ str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+ ldr r4, [r1, #MDREFR_OFFSET]
/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
@@ -295,8 +295,8 @@
ldr r4, =CFG_MDCNFG_VAL
bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
- str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
- ldr r4, [r1, #MDCNFG_OFFSET]
+ str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
+ ldr r4, [r1, #MDCNFG_OFFSET]
/* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
@@ -345,8 +345,8 @@
/* Step 4h: Write MDMRS. */
- ldr r2, =CFG_MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
+ ldr r2, =CFG_MDMRS_VAL
+ str r2, [r1, #MDMRS_OFFSET]
/* We are finished with Intel's memory controller initialisation */
@@ -357,17 +357,17 @@
initirqs:
- mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
- ldr r2, =ICLR
- str r1, [r2]
+ mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
+ ldr r2, =ICLR
+ str r1, [r2]
- ldr r2, =ICMR /* mask all interrupts at the controller */
- str r1, [r2]
+ ldr r2, =ICMR /* mask all interrupts at the controller */
+ str r1, [r2]
- /* ---------------------------------------------------------------- */
+ /* ---------------------------------------------------------------- */
/* Clock initialisation */
- /* ---------------------------------------------------------------- */
+ /* ---------------------------------------------------------------- */
initclks:
@@ -376,34 +376,34 @@
/* Turn Off ALL on-chip peripheral clocks for re-configuration */
/* Note: See label 'ENABLECLKS' for the re-enabling */
- ldr r1, =CKEN
- mov r2, #0
- str r2, [r1]
+ ldr r1, =CKEN
+ mov r2, #0
+ str r2, [r1]
- /* default value in case no valid rotary switch setting is found */
- ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
+ /* default value in case no valid rotary switch setting is found */
+ ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
- /* ... and write the core clock config register */
- ldr r1, =CCCR
- str r2, [r1]
+ /* ... and write the core clock config register */
+ ldr r1, =CCCR
+ str r2, [r1]
/* enable the 32Khz oscillator for RTC and PowerManager */
/*
- ldr r1, =OSCC
- mov r2, #OSCC_OON
- str r2, [r1]
+ ldr r1, =OSCC
+ mov r2, #OSCC_OON
+ str r2, [r1]
*/
/* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
/* has settled. */
60:
- ldr r2, [r1]
- ands r2, r2, #1
- beq 60b
+ ldr r2, [r1]
+ ands r2, r2, #1
+ beq 60b
/* ---------------------------------------------------------------- */
/* */
- /* ---------------------------------------------------------------- */
+ /* ---------------------------------------------------------------- */
/* Save SDRAM size */
ldr r1, =DRAM_SIZE
@@ -428,11 +428,10 @@
mcr p14,0,r0,c10,c0,0 /* dcsr */
#endif
- /* ---------------------------------------------------------------- */
+ /* ---------------------------------------------------------------- */
/* End memsetup */
- /* ---------------------------------------------------------------- */
+ /* ---------------------------------------------------------------- */
endmemsetup:
mov pc, lr
-
diff --git a/board/csb226/u-boot.lds b/board/csb226/u-boot.lds
index 46beb15..4c4cabf 100644
--- a/board/csb226/u-boot.lds
+++ b/board/csb226/u-boot.lds
@@ -26,29 +26,33 @@
ENTRY(_start)
SECTIONS
{
- . = 0x00000000;
+ . = 0x00000000;
- . = ALIGN(4);
+ . = ALIGN(4);
.text :
{
cpu/pxa/start.o (.text)
*(.text)
}
- . = ALIGN(4);
- .rodata : { *(.rodata) }
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
- . = ALIGN(4);
- .data : { *(.data) }
+ . = ALIGN(4);
+ .data : { *(.data) }
- . = ALIGN(4);
- .got : { *(.got) }
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
armboot_end_data = .;
- . = ALIGN(4);
+ . = ALIGN(4);
bss_start = .;
- .bss : { *(.bss) }
+ .bss : { *(.bss) }
bss_end = .;
armboot_end = .;