* Code cleanup:
- remove trailing white space, trailing empty lines, C++ comments, etc.
- split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c)
* Patches by Kenneth Johansson, 25 Jun 2003:
- major rework of command structure
(work done mostly by Michal Cendrowski and Joakim Kristiansen)
diff --git a/post/cpu/b.c b/post/cpu/b.c
index 1ae22cc..b4b17c8 100644
--- a/post/cpu/b.c
+++ b/post/cpu/b.c
@@ -84,8 +84,8 @@
}
if (ret == 0)
{
- if (link)
- ret = lr == (ulong) code + 24 ? 0 : -1;
+ if (link)
+ ret = lr == (ulong) code + 24 ? 0 : -1;
else
ret = lr == 0 ? 0 : -1;
}
@@ -100,7 +100,7 @@
if (ret == 0)
{
- ulong code[] =
+ ulong code[] =
{
ASM_MFLR(4),
ASM_MTLR(3),
@@ -115,15 +115,15 @@
ret = res == 0 ? 0 : -1;
- if (ret != 0)
- {
- post_log ("Error at b1 test !\n");
- }
+ if (ret != 0)
+ {
+ post_log ("Error at b1 test !\n");
+ }
}
if (ret == 0)
{
- ulong code[] =
+ ulong code[] =
{
ASM_MFLR(4),
ASM_MTLR(3),
@@ -138,15 +138,15 @@
ret = res == (ulong)code + 12 ? 0 : -1;
- if (ret != 0)
- {
- post_log ("Error at b2 test !\n");
- }
+ if (ret != 0)
+ {
+ post_log ("Error at b2 test !\n");
+ }
}
if (ret == 0)
{
- ulong cc, cd;
+ ulong cc, cd;
int cond;
ulong ctr;
int link;
@@ -157,30 +157,30 @@
{
for (cd = 0; cd < 4 && ret == 0; cd++)
{
- for (link = 0; link <= 1 && ret == 0; link++)
+ for (link = 0; link <= 1 && ret == 0; link++)
{
for (cond = 0; cond <= 1 && ret == 0; cond++)
{
- for (ctr = 1; ctr <= 2 && ret == 0; ctr++)
+ for (ctr = 1; ctr <= 2 && ret == 0; ctr++)
{
int dec = cd < 2;
int cr = cond ? 0x80000000 : 0x00000000;
int jumpc = cc >= 2 ||
- (cc == 0 && !cond) ||
- (cc == 1 && cond);
+ (cc == 0 && !cond) ||
+ (cc == 1 && cond);
int jumpd = cd >= 2 ||
- (cd == 0 && ctr != 1) ||
- (cd == 1 && ctr == 1);
+ (cd == 0 && ctr != 1) ||
+ (cd == 1 && ctr == 1);
int jump = jumpc && jumpd;
ret = cpu_post_test_bc (link ? OP_BCL : OP_BC,
- (cc << 3) + (cd << 1), 0, jump, dec, link,
+ (cc << 3) + (cd << 1), 0, jump, dec, link,
ctr, cr);
- if (ret != 0)
- {
- post_log ("Error at b3 test %d !\n", i);
- }
+ if (ret != 0)
+ {
+ post_log ("Error at b3 test %d !\n", i);
+ }
i++;
}
diff --git a/post/cpu/complex.c b/post/cpu/complex.c
index dc8b080..033584b 100644
--- a/post/cpu/complex.c
+++ b/post/cpu/complex.c
@@ -116,7 +116,7 @@
if (ret != 0)
{
- post_log ("Error at complex test !\n");
+ post_log ("Error at complex test !\n");
}
return ret;
diff --git a/post/cpu/cr.c b/post/cpu/cr.c
index 8e38729..da6ef37 100644
--- a/post/cpu/cr.c
+++ b/post/cpu/cr.c
@@ -70,11 +70,11 @@
} cpu_post_cr_table2[] =
{
{
- 0xa0000000,
+ 0xa0000000,
1
},
{
- 0x40000000,
+ 0x40000000,
5
},
};
@@ -89,13 +89,13 @@
} cpu_post_cr_table3[] =
{
{
- 0x01234567,
+ 0x01234567,
0,
4,
0x01230567
},
{
- 0x01234567,
+ 0x01234567,
7,
0,
0x71234567
@@ -115,131 +115,131 @@
{
{
OP_CRAND,
- 0x0000ffff,
+ 0x0000ffff,
0,
16,
0,
- 0x0000ffff
+ 0x0000ffff
},
{
OP_CRAND,
- 0x0000ffff,
+ 0x0000ffff,
16,
17,
0,
- 0x8000ffff
+ 0x8000ffff
},
{
OP_CRANDC,
- 0x0000ffff,
+ 0x0000ffff,
0,
16,
0,
- 0x0000ffff
+ 0x0000ffff
},
{
OP_CRANDC,
- 0x0000ffff,
+ 0x0000ffff,
16,
0,
0,
- 0x8000ffff
+ 0x8000ffff
},
{
OP_CROR,
- 0x0000ffff,
+ 0x0000ffff,
0,
16,
0,
- 0x8000ffff
+ 0x8000ffff
},
{
OP_CROR,
- 0x0000ffff,
+ 0x0000ffff,
0,
1,
0,
- 0x0000ffff
+ 0x0000ffff
},
{
OP_CRORC,
- 0x0000ffff,
+ 0x0000ffff,
0,
16,
0,
- 0x0000ffff
+ 0x0000ffff
},
{
OP_CRORC,
- 0x0000ffff,
+ 0x0000ffff,
0,
0,
0,
- 0x8000ffff
+ 0x8000ffff
},
{
OP_CRXOR,
- 0x0000ffff,
+ 0x0000ffff,
0,
0,
0,
- 0x0000ffff
+ 0x0000ffff
},
{
OP_CRXOR,
- 0x0000ffff,
+ 0x0000ffff,
0,
16,
0,
- 0x8000ffff
+ 0x8000ffff
},
{
OP_CRNAND,
- 0x0000ffff,
+ 0x0000ffff,
0,
16,
0,
- 0x8000ffff
+ 0x8000ffff
},
{
OP_CRNAND,
- 0x0000ffff,
+ 0x0000ffff,
16,
17,
0,
- 0x0000ffff
+ 0x0000ffff
},
{
OP_CRNOR,
- 0x0000ffff,
+ 0x0000ffff,
0,
16,
0,
- 0x0000ffff
+ 0x0000ffff
},
{
OP_CRNOR,
- 0x0000ffff,
+ 0x0000ffff,
0,
1,
0,
- 0x8000ffff
+ 0x8000ffff
},
{
OP_CREQV,
- 0x0000ffff,
+ 0x0000ffff,
0,
0,
0,
- 0x8000ffff
+ 0x8000ffff
},
{
OP_CREQV,
- 0x0000ffff,
+ 0x0000ffff,
0,
16,
0,
- 0x0000ffff
+ 0x0000ffff
},
};
static unsigned int cpu_post_cr_size4 =
@@ -258,7 +258,7 @@
ulong cr = cpu_post_cr_table1[i];
ulong res;
- unsigned long code[] =
+ unsigned long code[] =
{
ASM_MTCR(3),
ASM_MFCR(3),
@@ -269,10 +269,10 @@
ret = res == cr ? 0 : -1;
- if (ret != 0)
- {
- post_log ("Error at cr1 test %d !\n", i);
- }
+ if (ret != 0)
+ {
+ post_log ("Error at cr1 test %d !\n", i);
+ }
}
for (i = 0; i < cpu_post_cr_size2 && ret == 0; i++)
@@ -281,7 +281,7 @@
ulong res;
ulong xer;
- unsigned long code[] =
+ unsigned long code[] =
{
ASM_MTXER(3),
ASM_MCRXR(test->cr),
@@ -295,10 +295,10 @@
ret = xer == 0 && ((res << (4 * test->cr)) & 0xe0000000) == test->xer ?
0 : -1;
- if (ret != 0)
- {
- post_log ("Error at cr2 test %d !\n", i);
- }
+ if (ret != 0)
+ {
+ post_log ("Error at cr2 test %d !\n", i);
+ }
}
for (i = 0; i < cpu_post_cr_size3 && ret == 0; i++)
@@ -306,7 +306,7 @@
struct cpu_post_cr_s3 *test = cpu_post_cr_table3 + i;
ulong res;
- unsigned long code[] =
+ unsigned long code[] =
{
ASM_MTCR(3),
ASM_MCRF(test->cd, test->cs),
@@ -318,10 +318,10 @@
ret = res == test->res ? 0 : -1;
- if (ret != 0)
- {
- post_log ("Error at cr3 test %d !\n", i);
- }
+ if (ret != 0)
+ {
+ post_log ("Error at cr3 test %d !\n", i);
+ }
}
for (i = 0; i < cpu_post_cr_size4 && ret == 0; i++)
@@ -329,7 +329,7 @@
struct cpu_post_cr_s4 *test = cpu_post_cr_table4 + i;
ulong res;
- unsigned long code[] =
+ unsigned long code[] =
{
ASM_MTCR(3),
ASM_12F(test->cmd, test->op3, test->op1, test->op2),
@@ -341,10 +341,10 @@
ret = res == test->res ? 0 : -1;
- if (ret != 0)
- {
- post_log ("Error at cr4 test %d !\n", i);
- }
+ if (ret != 0)
+ {
+ post_log ("Error at cr4 test %d !\n", i);
+ }
}
asm ( "mtcr %0" : : "r" (cr_sav));
diff --git a/post/cpu/load.c b/post/cpu/load.c
index b3418ef..393c568 100644
--- a/post/cpu/load.c
+++ b/post/cpu/load.c
@@ -61,112 +61,112 @@
} cpu_post_load_table[] =
{
{
- OP_LWZ,
+ OP_LWZ,
4,
0,
0,
4
},
{
- OP_LHA,
+ OP_LHA,
3,
0,
0,
2
},
{
- OP_LHZ,
+ OP_LHZ,
2,
0,
0,
2
},
{
- OP_LBZ,
+ OP_LBZ,
1,
0,
0,
1
},
{
- OP_LWZU,
+ OP_LWZU,
4,
1,
0,
4
},
{
- OP_LHAU,
+ OP_LHAU,
3,
1,
0,
2
},
{
- OP_LHZU,
+ OP_LHZU,
2,
1,
0,
2
},
{
- OP_LBZU,
+ OP_LBZU,
1,
1,
0,
1
},
{
- OP_LWZX,
+ OP_LWZX,
4,
0,
1,
4
},
{
- OP_LHAX,
+ OP_LHAX,
3,
0,
1,
2
},
{
- OP_LHZX,
+ OP_LHZX,
2,
0,
1,
2
},
{
- OP_LBZX,
+ OP_LBZX,
1,
0,
1,
1
},
{
- OP_LWZUX,
+ OP_LWZUX,
4,
1,
1,
4
},
{
- OP_LHAUX,
+ OP_LHAUX,
3,
1,
1,
2
},
{
- OP_LHZUX,
+ OP_LHZUX,
2,
1,
1,
2
},
{
- OP_LBZUX,
+ OP_LBZUX,
1,
1,
1,
@@ -186,7 +186,7 @@
struct cpu_post_load_s *test = cpu_post_load_table + i;
uchar data[16] =
{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
- ulong base0 = (ulong) (data + 8);
+ ulong base0 = (ulong) (data + 8);
ulong base = base0;
ulong value;
@@ -194,7 +194,7 @@
{
ulong code[] =
{
- ASM_12(test->cmd, 5, 3, 4),
+ ASM_12(test->cmd, 5, 3, 4),
ASM_BLR,
};
@@ -204,7 +204,7 @@
{
ulong code[] =
{
- ASM_11I(test->cmd, 4, 3, test->offset),
+ ASM_11I(test->cmd, 4, 3, test->offset),
ASM_BLR,
};
@@ -224,27 +224,27 @@
switch (test->width)
{
case 1:
- ret = *(uchar *)(base0 + test->offset) == value ?
+ ret = *(uchar *)(base0 + test->offset) == value ?
0 : -1;
- break;
+ break;
case 2:
- ret = *(ushort *)(base0 + test->offset) == value ?
+ ret = *(ushort *)(base0 + test->offset) == value ?
0 : -1;
- break;
+ break;
case 3:
- ret = *(short *)(base0 + test->offset) == value ?
+ ret = *(short *)(base0 + test->offset) == value ?
0 : -1;
- break;
+ break;
case 4:
- ret = *(ulong *)(base0 + test->offset) == value ?
+ ret = *(ulong *)(base0 + test->offset) == value ?
0 : -1;
- break;
+ break;
}
}
if (ret != 0)
{
- post_log ("Error at load test %d !\n", i);
+ post_log ("Error at load test %d !\n", i);
}
}
diff --git a/post/cpu/multi.c b/post/cpu/multi.c
index bdad5d9..8724384 100644
--- a/post/cpu/multi.c
+++ b/post/cpu/multi.c
@@ -51,7 +51,7 @@
{
ulong src [26], dst [26];
- ulong code[] =
+ ulong code[] =
{
ASM_LMW(5, 3, 0),
ASM_STMW(5, 4, 0),
@@ -71,7 +71,7 @@
if (ret != 0)
{
- post_log ("Error at multi test !\n");
+ post_log ("Error at multi test !\n");
}
return ret;
diff --git a/post/cpu/store.c b/post/cpu/store.c
index e5189c7..f495bf2 100644
--- a/post/cpu/store.c
+++ b/post/cpu/store.c
@@ -62,7 +62,7 @@
} cpu_post_store_table[] =
{
{
- OP_STW,
+ OP_STW,
4,
0,
0,
@@ -70,7 +70,7 @@
0xff00ff00
},
{
- OP_STH,
+ OP_STH,
2,
0,
0,
@@ -78,7 +78,7 @@
0xff00
},
{
- OP_STB,
+ OP_STB,
1,
0,
0,
@@ -86,7 +86,7 @@
0xff
},
{
- OP_STWU,
+ OP_STWU,
4,
1,
0,
@@ -94,7 +94,7 @@
0xff00ff00
},
{
- OP_STHU,
+ OP_STHU,
2,
1,
0,
@@ -102,7 +102,7 @@
0xff00
},
{
- OP_STBU,
+ OP_STBU,
1,
1,
0,
@@ -110,7 +110,7 @@
0xff
},
{
- OP_STWX,
+ OP_STWX,
4,
0,
1,
@@ -118,7 +118,7 @@
0xff00ff00
},
{
- OP_STHX,
+ OP_STHX,
2,
0,
1,
@@ -126,7 +126,7 @@
0xff00
},
{
- OP_STBX,
+ OP_STBX,
1,
0,
1,
@@ -134,7 +134,7 @@
0xff
},
{
- OP_STWUX,
+ OP_STWUX,
4,
1,
1,
@@ -142,7 +142,7 @@
0xff00ff00
},
{
- OP_STHUX,
+ OP_STHUX,
2,
1,
1,
@@ -150,7 +150,7 @@
0xff00
},
{
- OP_STBUX,
+ OP_STBUX,
1,
1,
1,
@@ -171,14 +171,14 @@
struct cpu_post_store_s *test = cpu_post_store_table + i;
uchar data[16] =
{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
- ulong base0 = (ulong) (data + 8);
+ ulong base0 = (ulong) (data + 8);
ulong base = base0;
if (test->index)
{
ulong code[] =
{
- ASM_12(test->cmd, 5, 3, 4),
+ ASM_12(test->cmd, 5, 3, 4),
ASM_BLR,
};
@@ -188,7 +188,7 @@
{
ulong code[] =
{
- ASM_11I(test->cmd, 4, 3, test->offset),
+ ASM_11I(test->cmd, 4, 3, test->offset),
ASM_BLR,
};
@@ -208,23 +208,23 @@
switch (test->width)
{
case 1:
- ret = *(uchar *)(base0 + test->offset) == test->value ?
+ ret = *(uchar *)(base0 + test->offset) == test->value ?
0 : -1;
- break;
+ break;
case 2:
- ret = *(ushort *)(base0 + test->offset) == test->value ?
+ ret = *(ushort *)(base0 + test->offset) == test->value ?
0 : -1;
- break;
+ break;
case 4:
- ret = *(ulong *)(base0 + test->offset) == test->value ?
+ ret = *(ulong *)(base0 + test->offset) == test->value ?
0 : -1;
- break;
+ break;
}
}
if (ret != 0)
{
- post_log ("Error at store test %d !\n", i);
+ post_log ("Error at store test %d !\n", i);
}
}
diff --git a/post/cpu/string.c b/post/cpu/string.c
index a19a755..bd83bd1 100644
--- a/post/cpu/string.c
+++ b/post/cpu/string.c
@@ -54,7 +54,7 @@
{
char src [31], dst [31];
- ulong code[] =
+ ulong code[] =
{
ASM_LSWI(5, 3, 31),
ASM_STSWI(5, 4, 31),
@@ -76,7 +76,7 @@
{
char src [95], dst [95];
- ulong code[] =
+ ulong code[] =
{
ASM_LSWX(8, 3, 5),
ASM_STSWX(8, 4, 5),
@@ -96,7 +96,7 @@
if (ret != 0)
{
- post_log ("Error at string test !\n");
+ post_log ("Error at string test !\n");
}
return ret;
diff --git a/post/cpu/two.c b/post/cpu/two.c
index 6075714..cfbac5e 100644
--- a/post/cpu/two.c
+++ b/post/cpu/two.c
@@ -53,32 +53,32 @@
} cpu_post_two_table[] =
{
{
- OP_NEG,
+ OP_NEG,
3,
-3
},
{
- OP_NEG,
+ OP_NEG,
5,
-5
},
{
- OP_ADDME,
+ OP_ADDME,
6,
5
},
{
- OP_ADDZE,
+ OP_ADDZE,
5,
5
},
{
- OP_SUBFME,
+ OP_SUBFME,
6,
~6 - 1
},
{
- OP_SUBFZE,
+ OP_SUBFZE,
5,
~5
},
@@ -101,7 +101,7 @@
unsigned int reg0 = (reg + 0) % 32;
unsigned int reg1 = (reg + 1) % 32;
unsigned int stk = reg < 16 ? 31 : 15;
- unsigned long code[] =
+ unsigned long code[] =
{
ASM_STW(stk, 1, -4),
ASM_ADDI(stk, 1, -16),
@@ -118,7 +118,7 @@
ASM_LWZ(stk, 1, -4),
ASM_BLR,
};
- unsigned long codecr[] =
+ unsigned long codecr[] =
{
ASM_STW(stk, 1, -4),
ASM_ADDI(stk, 1, -16),
@@ -140,34 +140,34 @@
if (ret == 0)
{
- cr = 0;
- cpu_post_exec_21 (code, & cr, & res, test->op);
+ cr = 0;
+ cpu_post_exec_21 (code, & cr, & res, test->op);
- ret = res == test->res && cr == 0 ? 0 : -1;
+ ret = res == test->res && cr == 0 ? 0 : -1;
- if (ret != 0)
- {
- post_log ("Error at two test %d !\n", i);
- }
+ if (ret != 0)
+ {
+ post_log ("Error at two test %d !\n", i);
+ }
}
if (ret == 0)
{
- cpu_post_exec_21 (codecr, & cr, & res, test->op);
+ cpu_post_exec_21 (codecr, & cr, & res, test->op);
- ret = res == test->res &&
+ ret = res == test->res &&
(cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
- if (ret != 0)
- {
- post_log ("Error at two test %d !\n", i);
- }
+ if (ret != 0)
+ {
+ post_log ("Error at two test %d !\n", i);
+ }
}
}
}
if (flag)
- enable_interrupts();
+ enable_interrupts();
return ret;
}
diff --git a/post/post.c b/post/post.c
index d512533..9d62f40 100644
--- a/post/post.c
+++ b/post/post.c
@@ -50,7 +50,7 @@
res = -1;
}
}
-
+
gd->post_init_f_time = post_time_ms(0);
if (!gd->post_init_f_time)
{
@@ -398,7 +398,7 @@
if (test->reloc) {
addr = (ulong) (test->reloc) + gd->reloc_off;
test->reloc = (void (*)(void)) addr;
-
+
test->reloc();
}
}
diff --git a/post/spr.c b/post/spr.c
index 97f7610..330b977 100644
--- a/post/spr.c
+++ b/post/spr.c
@@ -48,66 +48,66 @@
} spr_test_list [] = {
/* Standard Special-Purpose Registers */
- {1, "XER", 0x00000000, 0x00000000},
- {8, "LR", 0x00000000, 0x00000000},
- {9, "CTR", 0x00000000, 0x00000000},
- {18, "DSISR", 0x00000000, 0x00000000},
- {19, "DAR", 0x00000000, 0x00000000},
- {22, "DEC", 0x00000000, 0x00000000},
- {26, "SRR0", 0x00000000, 0x00000000},
- {27, "SRR1", 0x00000000, 0x00000000},
- {272, "SPRG0", 0x00000000, 0x00000000},
- {273, "SPRG1", 0x00000000, 0x00000000},
- {274, "SPRG2", 0x00000000, 0x00000000},
- {275, "SPRG3", 0x00000000, 0x00000000},
- {287, "PVR", 0xFFFF0000, 0x00500000},
+ {1, "XER", 0x00000000, 0x00000000},
+ {8, "LR", 0x00000000, 0x00000000},
+ {9, "CTR", 0x00000000, 0x00000000},
+ {18, "DSISR", 0x00000000, 0x00000000},
+ {19, "DAR", 0x00000000, 0x00000000},
+ {22, "DEC", 0x00000000, 0x00000000},
+ {26, "SRR0", 0x00000000, 0x00000000},
+ {27, "SRR1", 0x00000000, 0x00000000},
+ {272, "SPRG0", 0x00000000, 0x00000000},
+ {273, "SPRG1", 0x00000000, 0x00000000},
+ {274, "SPRG2", 0x00000000, 0x00000000},
+ {275, "SPRG3", 0x00000000, 0x00000000},
+ {287, "PVR", 0xFFFF0000, 0x00500000},
/* Additional Special-Purpose Registers */
- {144, "CMPA", 0x00000000, 0x00000000},
- {145, "CMPB", 0x00000000, 0x00000000},
- {146, "CMPC", 0x00000000, 0x00000000},
- {147, "CMPD", 0x00000000, 0x00000000},
- {148, "ICR", 0xFFFFFFFF, 0x00000000},
- {149, "DER", 0x00000000, 0x00000000},
- {150, "COUNTA", 0xFFFFFFFF, 0x00000000},
- {151, "COUNTB", 0xFFFFFFFF, 0x00000000},
- {152, "CMPE", 0x00000000, 0x00000000},
- {153, "CMPF", 0x00000000, 0x00000000},
- {154, "CMPG", 0x00000000, 0x00000000},
- {155, "CMPH", 0x00000000, 0x00000000},
- {156, "LCTRL1", 0xFFFFFFFF, 0x00000000},
- {157, "LCTRL2", 0xFFFFFFFF, 0x00000000},
- {158, "ICTRL", 0xFFFFFFFF, 0x00000007},
- {159, "BAR", 0x00000000, 0x00000000},
- {630, "DPDR", 0x00000000, 0x00000000},
- {631, "DPIR", 0x00000000, 0x00000000},
- {638, "IMMR", 0xFFFF0000, CFG_IMMR },
- {560, "IC_CST", 0x8E380000, 0x00000000},
- {561, "IC_ADR", 0x00000000, 0x00000000},
- {562, "IC_DAT", 0x00000000, 0x00000000},
- {568, "DC_CST", 0xEF380000, 0x00000000},
- {569, "DC_ADR", 0x00000000, 0x00000000},
- {570, "DC_DAT", 0x00000000, 0x00000000},
- {784, "MI_CTR", 0xFFFFFFFF, 0x00000000},
- {786, "MI_AP", 0x00000000, 0x00000000},
- {787, "MI_EPN", 0x00000000, 0x00000000},
- {789, "MI_TWC", 0xFFFFFE02, 0x00000000},
- {790, "MI_RPN", 0x00000000, 0x00000000},
- {816, "MI_DBCAM", 0x00000000, 0x00000000},
- {817, "MI_DBRAM0", 0x00000000, 0x00000000},
- {818, "MI_DBRAM1", 0x00000000, 0x00000000},
- {792, "MD_CTR", 0xFFFFFFFF, 0x04000000},
- {793, "M_CASID", 0xFFFFFFF0, 0x00000000},
- {794, "MD_AP", 0x00000000, 0x00000000},
- {795, "MD_EPN", 0x00000000, 0x00000000},
- {796, "M_TWB", 0x00000003, 0x00000000},
- {797, "MD_TWC", 0x00000003, 0x00000000},
- {798, "MD_RPN", 0x00000000, 0x00000000},
- {799, "M_TW", 0x00000000, 0x00000000},
- {824, "MD_DBCAM", 0x00000000, 0x00000000},
- {825, "MD_DBRAM0", 0x00000000, 0x00000000},
- {826, "MD_DBRAM1", 0x00000000, 0x00000000},
+ {144, "CMPA", 0x00000000, 0x00000000},
+ {145, "CMPB", 0x00000000, 0x00000000},
+ {146, "CMPC", 0x00000000, 0x00000000},
+ {147, "CMPD", 0x00000000, 0x00000000},
+ {148, "ICR", 0xFFFFFFFF, 0x00000000},
+ {149, "DER", 0x00000000, 0x00000000},
+ {150, "COUNTA", 0xFFFFFFFF, 0x00000000},
+ {151, "COUNTB", 0xFFFFFFFF, 0x00000000},
+ {152, "CMPE", 0x00000000, 0x00000000},
+ {153, "CMPF", 0x00000000, 0x00000000},
+ {154, "CMPG", 0x00000000, 0x00000000},
+ {155, "CMPH", 0x00000000, 0x00000000},
+ {156, "LCTRL1", 0xFFFFFFFF, 0x00000000},
+ {157, "LCTRL2", 0xFFFFFFFF, 0x00000000},
+ {158, "ICTRL", 0xFFFFFFFF, 0x00000007},
+ {159, "BAR", 0x00000000, 0x00000000},
+ {630, "DPDR", 0x00000000, 0x00000000},
+ {631, "DPIR", 0x00000000, 0x00000000},
+ {638, "IMMR", 0xFFFF0000, CFG_IMMR },
+ {560, "IC_CST", 0x8E380000, 0x00000000},
+ {561, "IC_ADR", 0x00000000, 0x00000000},
+ {562, "IC_DAT", 0x00000000, 0x00000000},
+ {568, "DC_CST", 0xEF380000, 0x00000000},
+ {569, "DC_ADR", 0x00000000, 0x00000000},
+ {570, "DC_DAT", 0x00000000, 0x00000000},
+ {784, "MI_CTR", 0xFFFFFFFF, 0x00000000},
+ {786, "MI_AP", 0x00000000, 0x00000000},
+ {787, "MI_EPN", 0x00000000, 0x00000000},
+ {789, "MI_TWC", 0xFFFFFE02, 0x00000000},
+ {790, "MI_RPN", 0x00000000, 0x00000000},
+ {816, "MI_DBCAM", 0x00000000, 0x00000000},
+ {817, "MI_DBRAM0", 0x00000000, 0x00000000},
+ {818, "MI_DBRAM1", 0x00000000, 0x00000000},
+ {792, "MD_CTR", 0xFFFFFFFF, 0x04000000},
+ {793, "M_CASID", 0xFFFFFFF0, 0x00000000},
+ {794, "MD_AP", 0x00000000, 0x00000000},
+ {795, "MD_EPN", 0x00000000, 0x00000000},
+ {796, "M_TWB", 0x00000003, 0x00000000},
+ {797, "MD_TWC", 0x00000003, 0x00000000},
+ {798, "MD_RPN", 0x00000000, 0x00000000},
+ {799, "M_TW", 0x00000000, 0x00000000},
+ {824, "MD_DBCAM", 0x00000000, 0x00000000},
+ {825, "MD_DBRAM0", 0x00000000, 0x00000000},
+ {826, "MD_DBRAM1", 0x00000000, 0x00000000},
};
static int spr_test_list_size =
diff --git a/post/sysmon.c b/post/sysmon.c
index f069caa..30a5cb2 100644
--- a/post/sysmon.c
+++ b/post/sysmon.c
@@ -32,7 +32,7 @@
* This test performs the system hardware monitoring.
* The test passes when all the following voltages and temperatures
* are within allowed ranges:
- *
+ *
* Board temperature
* Front temperature
* +3.3V CPU logic
@@ -40,7 +40,7 @@
* +12V PCMCIA
* +12V CCFL
* +5V standby
- *
+ *
* CCFL is not enabled if temperature values are not within allowed ranges
*
* See the list off all parameters in the sysmon_table below
@@ -150,7 +150,7 @@
{
(*l)->init(*l);
}
-
+
return 0;
}
@@ -185,24 +185,24 @@
int dec, frac;
sprintf(buf, "%+d", unit_val / s->unit_div);
-
+
frac = (unit_val > 0 ? unit_val : -unit_val) % s->unit_div;
p = buf + strlen(buf);
-
+
dec = s->unit_div;
-
+
if (dec != 1)
{
*p++ = '.';
}
-
+
for (dec /= 10; dec != 0; dec /= 10)
{
*p++ = '0' + frac / dec % 10;
}
-
+
strcpy(p, s->unit_name);
-
+
return buf;
}
@@ -217,7 +217,7 @@
printf("Error: LM87 not found at 0x%02X\n", this->chip);
return;
}
-
+
/* Configure pins 5,6 as AIN */
val = 0x03;
if (i2c_write(this->chip, 0x16, 1, &val, 1))
diff --git a/post/tests.c b/post/tests.c
index 5b2c7e2..55da927 100644
--- a/post/tests.c
+++ b/post/tests.c
@@ -53,146 +53,146 @@
{
#if CONFIG_POST & CFG_POST_CACHE
{
- "Cache test",
- "cache",
- "This test verifies the CPU cache operation.",
- POST_RAM | POST_ALWAYS,
- &cache_post_test,
- NULL,
- NULL,
+ "Cache test",
+ "cache",
+ "This test verifies the CPU cache operation.",
+ POST_RAM | POST_ALWAYS,
+ &cache_post_test,
+ NULL,
+ NULL,
CFG_POST_CACHE
},
#endif
#if CONFIG_POST & CFG_POST_WATCHDOG
{
- "Watchdog timer test",
- "watchdog",
- "This test checks the watchdog timer.",
- POST_RAM | POST_POWERON | POST_POWERFAIL | POST_MANUAL | POST_REBOOT,
- &watchdog_post_test,
- NULL,
- NULL,
+ "Watchdog timer test",
+ "watchdog",
+ "This test checks the watchdog timer.",
+ POST_RAM | POST_POWERON | POST_POWERFAIL | POST_MANUAL | POST_REBOOT,
+ &watchdog_post_test,
+ NULL,
+ NULL,
CFG_POST_WATCHDOG
},
#endif
#if CONFIG_POST & CFG_POST_I2C
{
- "I2C test",
- "i2c",
- "This test verifies the I2C operation.",
- POST_RAM | POST_ALWAYS,
- &i2c_post_test,
- NULL,
- NULL,
+ "I2C test",
+ "i2c",
+ "This test verifies the I2C operation.",
+ POST_RAM | POST_ALWAYS,
+ &i2c_post_test,
+ NULL,
+ NULL,
CFG_POST_I2C
},
#endif
#if CONFIG_POST & CFG_POST_RTC
{
- "RTC test",
- "rtc",
- "This test verifies the RTC operation.",
- POST_RAM | POST_POWERFAIL | POST_MANUAL,
- &rtc_post_test,
- NULL,
- NULL,
+ "RTC test",
+ "rtc",
+ "This test verifies the RTC operation.",
+ POST_RAM | POST_POWERFAIL | POST_MANUAL,
+ &rtc_post_test,
+ NULL,
+ NULL,
CFG_POST_RTC
},
#endif
#if CONFIG_POST & CFG_POST_MEMORY
{
- "Memory test",
- "memory",
- "This test checks RAM.",
- POST_ROM | POST_POWERON | POST_POWERFAIL | POST_PREREL,
- &memory_post_test,
- NULL,
- NULL,
+ "Memory test",
+ "memory",
+ "This test checks RAM.",
+ POST_ROM | POST_POWERON | POST_POWERFAIL | POST_PREREL,
+ &memory_post_test,
+ NULL,
+ NULL,
CFG_POST_MEMORY
},
#endif
#if CONFIG_POST & CFG_POST_CPU
{
- "CPU test",
- "cpu",
- "This test verifies the arithmetic logic unit of"
- " CPU.",
- POST_RAM | POST_ALWAYS,
- &cpu_post_test,
- NULL,
- NULL,
+ "CPU test",
+ "cpu",
+ "This test verifies the arithmetic logic unit of"
+ " CPU.",
+ POST_RAM | POST_ALWAYS,
+ &cpu_post_test,
+ NULL,
+ NULL,
CFG_POST_CPU
},
#endif
#if CONFIG_POST & CFG_POST_UART
{
- "UART test",
- "uart",
- "This test verifies the UART operation.",
- POST_RAM | POST_POWERFAIL | POST_MANUAL,
- &uart_post_test,
- NULL,
- NULL,
+ "UART test",
+ "uart",
+ "This test verifies the UART operation.",
+ POST_RAM | POST_POWERFAIL | POST_MANUAL,
+ &uart_post_test,
+ NULL,
+ NULL,
CFG_POST_UART
},
#endif
#if CONFIG_POST & CFG_POST_ETHER
{
- "ETHERNET test",
- "ethernet",
- "This test verifies the ETHERNET operation.",
- POST_RAM | POST_ALWAYS | POST_MANUAL,
- ðer_post_test,
- NULL,
- NULL,
+ "ETHERNET test",
+ "ethernet",
+ "This test verifies the ETHERNET operation.",
+ POST_RAM | POST_ALWAYS | POST_MANUAL,
+ ðer_post_test,
+ NULL,
+ NULL,
CFG_POST_ETHER
},
#endif
#if CONFIG_POST & CFG_POST_SPI
{
- "SPI test",
- "spi",
- "This test verifies the SPI operation.",
- POST_RAM | POST_ALWAYS | POST_MANUAL,
- &spi_post_test,
- NULL,
- NULL,
+ "SPI test",
+ "spi",
+ "This test verifies the SPI operation.",
+ POST_RAM | POST_ALWAYS | POST_MANUAL,
+ &spi_post_test,
+ NULL,
+ NULL,
CFG_POST_SPI
},
#endif
#if CONFIG_POST & CFG_POST_USB
{
- "USB test",
- "usb",
- "This test verifies the USB operation.",
- POST_RAM | POST_ALWAYS | POST_MANUAL,
- &usb_post_test,
- NULL,
- NULL,
+ "USB test",
+ "usb",
+ "This test verifies the USB operation.",
+ POST_RAM | POST_ALWAYS | POST_MANUAL,
+ &usb_post_test,
+ NULL,
+ NULL,
CFG_POST_USB
},
#endif
#if CONFIG_POST & CFG_POST_SPR
{
- "SPR test",
- "spr",
- "This test checks SPR contents.",
- POST_ROM | POST_ALWAYS | POST_PREREL,
- &spr_post_test,
- NULL,
- NULL,
+ "SPR test",
+ "spr",
+ "This test checks SPR contents.",
+ POST_ROM | POST_ALWAYS | POST_PREREL,
+ &spr_post_test,
+ NULL,
+ NULL,
CFG_POST_SPR
},
#endif
#if CONFIG_POST & CFG_POST_SYSMON
{
- "SYSMON test",
- "sysmon",
- "This test monitors system hardware.",
- POST_RAM | POST_ALWAYS,
- &sysmon_post_test,
- &sysmon_init_f,
- &sysmon_reloc,
+ "SYSMON test",
+ "sysmon",
+ "This test monitors system hardware.",
+ POST_RAM | POST_ALWAYS,
+ &sysmon_post_test,
+ &sysmon_init_f,
+ &sysmon_reloc,
CFG_POST_SYSMON
},
#endif
diff --git a/post/watchdog.c b/post/watchdog.c
index 0cdfbf0..48c4282 100644
--- a/post/watchdog.c
+++ b/post/watchdog.c
@@ -66,8 +66,8 @@
if (ints)
enable_interrupts ();
- /*
- * If we have reached this point, the watchdog timer
+ /*
+ * If we have reached this point, the watchdog timer
* does not work
*/
return -1;