imx: timer: Modify GPT timer driver for mx7
Modify the GPT common platform driver for mx7 which only use 24Mhz
OSC as clock source.
Note: at default, the mx7d will use system counter as timer. The GPT
is disabled.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
diff --git a/arch/arm/mach-imx/timer.c b/arch/arm/mach-imx/timer.c
index fa1941a..a3c4788 100644
--- a/arch/arm/mach-imx/timer.c
+++ b/arch/arm/mach-imx/timer.c
@@ -39,18 +39,16 @@
#define GPTPR_PRESCALER24M_SHIFT 12
#define GPTPR_PRESCALER24M_MASK (0xF << GPTPR_PRESCALER24M_SHIFT)
+DECLARE_GLOBAL_DATA_PTR;
+
static inline int gpt_has_clk_source_osc(void)
{
-#if defined(CONFIG_MX6)
if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) ||
is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul() ||
- is_mx6ull() || is_mx6sll())
+ is_mx6ull() || is_mx6sll() || is_mx7())
return 1;
return 0;
-#else
- return 0;
-#endif
}
static inline ulong gpt_get_clk(void)
@@ -73,7 +71,8 @@
__raw_writel(GPTCR_SWR, &cur_gpt->control);
/* We have no udelay by now */
- __raw_writel(0, &cur_gpt->control);
+ for (i = 0; i < 100; i++)
+ __raw_writel(0, &cur_gpt->control);
i = __raw_readl(&cur_gpt->control);
i &= ~GPTCR_CLKSOURCE_MASK;
@@ -87,7 +86,7 @@
* Enable bit and prescaler
*/
if (is_mx6sdl() || is_mx6sx() || is_mx6ul() || is_mx6ull() ||
- is_mx6sll()) {
+ is_mx6sll() || is_mx7()) {
i |= GPTCR_24MEN;
/* Produce 3Mhz clock */
@@ -103,6 +102,9 @@
#endif
__raw_writel(i, &cur_gpt->control);
+ gd->arch.tbl = __raw_readl(&cur_gpt->counter);
+ gd->arch.tbu = 0;
+
return 0;
}