imx: cleanup bootaux
Move i.MX6/7 bootaux code to imx_bootaux.c.
The i.MX6/7 has different src layout, so define M4 reg offset
to ease the cleanup. Redefine the M4 related BIT for share
common code.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c
index b62dfbf..0272851 100644
--- a/arch/arm/mach-imx/imx_bootaux.c
+++ b/arch/arm/mach-imx/imx_bootaux.c
@@ -5,21 +5,41 @@
*/
#include <common.h>
+#include <asm/io.h>
#include <command.h>
#include <linux/compiler.h>
-/* Allow for arch specific config before we boot */
-int __weak arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
+int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
{
- /* please define platform specific arch_auxiliary_core_up() */
- return CMD_RET_FAILURE;
+ ulong stack, pc;
+
+ if (!boot_private_data)
+ return -EINVAL;
+
+ stack = *(ulong *)boot_private_data;
+ pc = *(ulong *)(boot_private_data + 4);
+
+ /* Set the stack and pc to M4 bootROM */
+ writel(stack, M4_BOOTROM_BASE_ADDR);
+ writel(pc, M4_BOOTROM_BASE_ADDR + 4);
+
+ /* Enable M4 */
+ clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET,
+ SRC_M4C_NON_SCLR_RST_MASK, SRC_M4_ENABLE_MASK);
+
+ return 0;
}
-/* Allow for arch specific config before we boot */
-int __weak arch_auxiliary_core_check_up(u32 core_id)
+int arch_auxiliary_core_check_up(u32 core_id)
{
- /* please define platform specific arch_auxiliary_core_check_up() */
- return 0;
+ unsigned int val;
+
+ val = readl(SRC_BASE_ADDR + SRC_M4_REG_OFFSET);
+
+ if (val & SRC_M4C_NON_SCLR_RST_MASK)
+ return 0; /* assert in reset */
+
+ return 1;
}
/*