ppc: Move cpu/$CPU to arch/ppc/cpu/$CPU
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
diff --git a/include/configs/aria.h b/include/configs/aria.h
index f89fc57..06763c5 100644
--- a/include/configs/aria.h
+++ b/include/configs/aria.h
@@ -190,7 +190,7 @@
/*
* Backward compatible definitions,
- * so we do not have to change cpu/mpc512x/fixed_sdram.c
+ * so we do not have to change arch/ppc/cpu/mpc512x/fixed_sdram.c
*/
#define CONFIG_SYS_DDRCMD_EM2 (CONFIG_SYS_MICRON_EMR2)
#define CONFIG_SYS_DDRCMD_EM3 (CONFIG_SYS_MICRON_EMR3)
diff --git a/include/configs/galaxy5200.h b/include/configs/galaxy5200.h
index 4be28b2..44669ea 100644
--- a/include/configs/galaxy5200.h
+++ b/include/configs/galaxy5200.h
@@ -141,7 +141,7 @@
#define CONFIG_SYS_FLASH_BASE 0xfe000000
/*
- * The flash size is autoconfigured, but cpu/mpc5xxx/cpu_init.c needs this
+ * The flash size is autoconfigured, but arch/ppc/cpu/mpc5xxx/cpu_init.c needs this
* variable defined
*/
#define CONFIG_SYS_FLASH_SIZE 0x02000000
diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h
index a79feec..e5537da 100644
--- a/include/configs/kilauea.h
+++ b/include/configs/kilauea.h
@@ -230,7 +230,7 @@
* SDRAM Controller DDR autocalibration values and takes a lot longer
* to run than Method_B.
* (See the Method_A and Method_B algorithm discription in the file:
- * cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
+ * arch/ppc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
* Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A
*
* DDR Autocalibration Method_B is the default.
diff --git a/include/configs/linkstation.h b/include/configs/linkstation.h
index 16b464c..3958d09 100644
--- a/include/configs/linkstation.h
+++ b/include/configs/linkstation.h
@@ -290,7 +290,7 @@
* taken from the orignal Linkstation boot code
*
* Most of the low level configuration setttings are normally used
- * in cpu/mpc824x/cpu_init.c which is NOT used by this implementation.
+ * in arch/ppc/cpu/mpc824x/cpu_init.c which is NOT used by this implementation.
* Low level initialisation is done in board/linkstation/early_init.S
* The values below are included for reference purpose only
*/
diff --git a/include/configs/quad100hd.h b/include/configs/quad100hd.h
index 403837e..2472187 100644
--- a/include/configs/quad100hd.h
+++ b/include/configs/quad100hd.h
@@ -233,7 +233,7 @@
* Definitions for initial stack pointer and data area (in data cache)
*/
/* use on chip memory (OCM) for temperary stack until sdram is tested */
-/* see ./cpu/ppc4xx/start.S */
+/* see ./arch/ppc/cpu/ppc4xx/start.S */
#define CONFIG_SYS_TEMP_STACK_OCM 1
/* On Chip Memory location */
@@ -251,7 +251,7 @@
* Taken from PPCBoot board/icecube/icecube.h
*/
-/* see ./cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */
+/* see ./arch/ppc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */
#define CONFIG_SYS_EBC_PB0AP 0x04002480
/* AMD NOR flash - this corresponds to FLASH_BASE so may be correct */
#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000
@@ -269,7 +269,7 @@
*
* Taken in part from PPCBoot board/icecube/icecube.h
*/
-/* see ./cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */
+/* see ./arch/ppc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */
#define CONFIG_SYS_GPIO0_OSRH 0x55555550
#define CONFIG_SYS_GPIO0_OSRL 0x00000110
#define CONFIG_SYS_GPIO0_ISR1H 0x00000000
diff --git a/include/configs/sc3.h b/include/configs/sc3.h
index d00f248..7423663 100644
--- a/include/configs/sc3.h
+++ b/include/configs/sc3.h
@@ -456,7 +456,7 @@
* - internal SRAM (OCM=On Chip Memory) is placed to CONFIG_SYS_OCM_DATA_ADDR
* - Stackpointer will be located to
* (CONFIG_SYS_INIT_RAM_ADDR&0xFFFF0000) | (CONFIG_SYS_INIT_SP_OFFSET&0x0000FFFF)
- * in cpu/ppc4xx/start.S
+ * in arch/ppc/cpu/ppc4xx/start.S
*/
#undef CONFIG_SYS_INIT_DCACHE_CS
@@ -495,7 +495,7 @@
#define BOOTFLAG_WARM 0x02 /* Software reboot */
/* ################################################################################### */
-/* These defines will be used in cpu/ppc4xx/cpu_init.c to setup external chip selects */
+/* These defines will be used in arch/ppc/cpu/ppc4xx/cpu_init.c to setup external chip selects */
/* They are currently undefined cause they are initiaized in board/solidcard3/init.S */
/* This chip select accesses the boot device */