mpc85xx: Add support for the P2020
Added various p2020 processor specific details:
* SVR for p2020, p2020E
* immap updates for LAWs and DDR on p2020
* LAW defines related to p2020
Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: Travis Wheatley <Travis.Wheatley@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index e5046be..ed8dded 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -58,7 +58,23 @@
uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */
char res19[4];
uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */
- char res20[780]; /* XXX: LAW 8, LAW9 for 8572 */
+ char res19_8a[20];
+ uint lawbar8; /* 0xd08 - Local Access Window 8 Base Address Register */
+ char res19_8b[4];
+ uint lawar8; /* 0xd10 - Local Access Window 8 Attributes Register */
+ char res19_9a[20];
+ uint lawbar9; /* 0xd28 - Local Access Window 9 Base Address Register */
+ char res19_9b[4];
+ uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */
+ char res19_10a[20];
+ uint lawbar10; /* 0xd48 - Local Access Window 10 Base Address Register */
+ char res19_10b[4];
+ uint lawar10; /* 0xd50 - Local Access Window 10 Attributes Register */
+ char res19_11a[20];
+ uint lawbar11; /* 0xd68 - Local Access Window 11 Base Address Register */
+ char res19_11b[4];
+ uint lawar11; /* 0xd70 - Local Access Window 11 Attributes Register */
+ char res20[652];
uint eebacr; /* 0x1000 - ECM CCB Address Configuration Register */
char res21[12];
uint eebpcr; /* 0x1010 - ECM CCB Port Configuration Register */
@@ -119,7 +135,12 @@
uint ddr_sr_cntr; /* 0x217C - DDR self refresh counter */
uint ddr_sdram_rcw_1; /* 0x2180 - DDR Register Control Words 1 */
uint ddr_sdram_rcw_2; /* 0x2184 - DDR Register Control Words 2 */
- char res8_1b[2672];
+ char res8_1b[2456];
+ uint ddr_dsr1; /* 0x2B20 - DDR Debug Status Register 1 */
+ uint ddr_dsr2; /* 0x2B24 - DDR Debug Status Register 2 */
+ uint ddr_cdr1; /* 0x2B28 - DDR Control Driver Register 1 */
+ uint ddr_cdr2; /* 0x2B2C - DDR Control Driver Register 2 */
+ char res8_1c[200];
uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */
uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */
char res8_2[512];