| commit | 8f2e2f15ffa1bb03b6e6e189312426059f3215d1 | [log] [tgz] |
|---|---|---|
| author | Fabio Estevam <fabio.estevam@nxp.com> | Mon Jul 18 10:19:28 2016 -0300 |
| committer | Stefano Babic <sbabic@denx.de> | Wed Jul 20 18:26:37 2016 +0200 |
| tree | 590d7251e471c82dbe64ba604c57bc5fea0803d4 | |
| parent | 95cee94bd80c8dfbd5ac3b019782b55f4edebdeb [diff] |
mx6: clock: Fix the logic for reading axi_alt_sel According to the IMX6DQRM Reference Manual, the description of bit 7 (axi_alt_sel) of the CCM_CBCDR register is: "AXI alternative clock select 0 pll2 396MHz PFD will be selected as alternative clock for AXI root clock 1 pll3 540MHz PFD will be selected as alternative clock for AXI root clock " The current logic is inverted, so fix it to match the reference manual. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>