Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86
- Remember the device being emulated for Sandbox PCI
- Update Kconfig options for FSP 1.0
- Drop RESET_BASE and RESET_SEG_SIZE that are no longer used
diff --git a/MAINTAINERS b/MAINTAINERS
index c536566..2ef2976 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -404,6 +404,7 @@
S: Maintained
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git
F: arch/arm/mach-versal/
+N: (?<!uni)versal
ARM VERSATILE EXPRESS DRIVERS
M: Liviu Dudau <liviu.dudau@foss.arm.com>
@@ -442,11 +443,13 @@
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git
F: arch/arm/mach-zynqmp/
F: drivers/clk/clk_zynqmp.c
+F: driver/firmware/firmware-zynqmp.c
F: drivers/fpga/zynqpl.c
F: drivers/gpio/zynq_gpio.c
F: drivers/i2c/i2c-cdns.c
F: drivers/i2c/muxes/pca954x.c
F: drivers/i2c/zynq_i2c.c
+F: drivers/mailbox/zynqmp-ipi.c
F: drivers/mmc/zynq_sdhci.c
F: drivers/mtd/nand/raw/zynq_nand.c
F: drivers/net/phy/xilinx_phy.c
@@ -458,6 +461,7 @@
F: drivers/usb/host/ehci-zynq.c
F: drivers/watchdog/cdns_wdt.c
F: include/zynqmppl.h
+F: include/zynqmp_firmware.h
F: tools/zynqmp*
N: ultra96
N: zynqmp
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 384e382..c5027c1 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -462,6 +462,22 @@
Such implementation may be faster under some conditions
but may increase the binary size.
+config SET_STACK_SIZE
+ bool "Enable an option to set max stack size that can be used"
+ default y if ARCH_VERSAL || ARCH_ZYNQMP
+ help
+ This will enable an option to set max stack size that can be
+ used by u-boot.
+
+config STACK_SIZE
+ hex "Define max stack size that can be used by u-boot"
+ depends on SET_STACK_SIZE
+ default 0x4000000 if ARCH_VERSAL || ARCH_ZYNQMP
+ help
+ Defines Max stack size that can be used by u-boot so that the
+ initrd_high will be calculated as base stack pointer minus this
+ stack size.
+
config ARM64_SUPPORT_AARCH32
bool "ARM64 system support AArch32 execution state"
depends on ARM64
@@ -980,6 +996,7 @@
select DM_MMC if MMC
select DM_SERIAL
select OF_CONTROL
+ imply BOARD_LATE_INIT
config ARCH_VF610
bool "Freescale Vybrid"
@@ -1034,16 +1051,21 @@
select CLK
select DM
select DM_ETH if NET
+ select DM_MAILBOX
select DM_MMC if MMC
select DM_SERIAL
select DM_SPI if SPI
select DM_SPI_FLASH if DM_SPI
select DM_USB if USB
+ select FIRMWARE
select OF_CONTROL
select SPL_BOARD_INIT if SPL
select SPL_CLK if SPL
+ select SPL_DM_MAILBOX if SPL
+ select SPL_FIRMWARE if SPL
select SPL_SEPARATE_BSS if SPL
select SUPPORT_SPL
+ select ZYNQMP_IPI
imply BOARD_LATE_INIT
imply CMD_DM
imply FAT_WRITE
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 73d47f5..727da1a 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -247,6 +247,10 @@
dtb-$(CONFIG_ARCH_ZYNQMP) += \
avnet-ultra96-rev1.dtb \
avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dtb \
+ zynqmp-a2197-revA.dtb \
+ zynqmp-a2197-g-revA.dtb \
+ zynqmp-a2197-m-revA.dtb \
+ zynqmp-a2197-p-revA.dtb \
zynqmp-mini.dtb \
zynqmp-mini-emmc0.dtb \
zynqmp-mini-emmc1.dtb \
diff --git a/arch/arm/dts/am335x-guardian.dts b/arch/arm/dts/am335x-guardian.dts
index f3f022c..5ed2133 100644
--- a/arch/arm/dts/am335x-guardian.dts
+++ b/arch/arm/dts/am335x-guardian.dts
@@ -32,12 +32,19 @@
gpio_keys {
compatible = "gpio-keys";
pinctrl-names = "default";
- pinctrl-0 = <&gpio_keys_pins>;
+ pinctrl-0 = <&guardian_button_pins>;
- button21 {
+ select-button {
+ label = "guardian-select-button";
+ linux,code = <KEY_5>;
+ gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
+ wakeup-source;
+ };
+
+ power-button {
label = "guardian-power-button";
linux,code = <KEY_POWER>;
- gpios = <&gpio2 21 0>;
+ gpios = <&gpio2 21 GPIO_ACTIVE_LOW>;
wakeup-source;
};
};
@@ -45,19 +52,12 @@
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
- pinctrl-0 = <&leds_pins>;
+ pinctrl-0 = <&guardian_led_pins>;
- led1 {
- label = "green:heartbeat";
- gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- default-state = "off";
- };
-
- led2 {
- label = "green:mmc0";
+ life-led {
+ label = "guardian:life-led";
gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "mmc0";
+ linux,default-trigger = "heartbeat";
default-state = "off";
};
};
@@ -140,22 +140,25 @@
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
- gpmc,cs-rd-off-ns = <44>;
- gpmc,cs-wr-off-ns = <44>;
- gpmc,adv-on-ns = <6>;
- gpmc,adv-rd-off-ns = <34>;
- gpmc,adv-wr-off-ns = <44>;
+ gpmc,cs-rd-off-ns = <30>;
+ gpmc,cs-wr-off-ns = <30>;
+ gpmc,adv-on-ns = <0>;
+ gpmc,adv-rd-off-ns = <30>;
+ gpmc,adv-wr-off-ns = <30>;
gpmc,we-on-ns = <0>;
- gpmc,we-off-ns = <40>;
- gpmc,oe-on-ns = <0>;
- gpmc,oe-off-ns = <54>;
- gpmc,access-ns = <64>;
- gpmc,rd-cycle-ns = <82>;
- gpmc,wr-cycle-ns = <82>;
+ gpmc,we-off-ns = <15>;
+ gpmc,oe-on-ns = <1>;
+ gpmc,oe-off-ns = <15>;
+ gpmc,access-ns = <30>;
+ gpmc,rd-cycle-ns = <30>;
+ gpmc,wr-cycle-ns = <30>;
+ gpmc,wait-on-read = "true";
+ gpmc,wait-on-write = "true";
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
- gpmc,wr-access-ns = <40>;
+ gpmc,wait-monitoring-ns = <0>;
+ gpmc,wr-access-ns = <0>;
gpmc,wr-data-mux-bus-ns = <0>;
/*
@@ -199,18 +202,8 @@
};
partition@6 {
- label = "u-boot-env";
- reg = <0x300000 0x40000>;
- };
-
- partition@7 {
- label = "u-boot-env.backup1";
- reg = <0x340000 0x40000>;
- };
-
- partition@8 {
label = "UBI";
- reg = <0x380000 0x1fc80000>;
+ reg = <0x300000 0x1fd00000>;
};
};
};
@@ -326,6 +319,12 @@
status = "okay";
};
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "okay";
+};
+
&usb {
status = "okay";
};
@@ -354,7 +353,7 @@
&am33xx_pinmux {
pinctrl-names = "default";
- pinctrl-0 = <&clkout2_pin &gpio_pins>;
+ pinctrl-0 = <&clkout2_pin &guardian_interface_pins>;
clkout2_pin: pinmux_clkout2_pin {
pinctrl-single,pins = <
@@ -368,16 +367,25 @@
>;
};
- gpio_keys_pins: pinmux_gpio_keys_pins {
+ guardian_button_pins: pinmux_gpio_keys_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x884, PIN_INPUT | MUX_MODE7)
>;
};
- gpio_pins: pinmux_gpio_pins {
+ guardian_interface_pins: pinmux_guardian_interface_pins {
pinctrl-single,pins = <
- AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE7)
- AM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x9ac, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLUP | MUX_MODE7)
+ AM33XX_IOPAD(0x90c, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x944, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
+ AM33XX_IOPAD(0x91c, PIN_INPUT | MUX_MODE7)
+ AM33XX_IOPAD(0x918, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
>;
};
@@ -452,10 +460,9 @@
>;
};
- leds_pins: pinmux_leds_pins {
+ guardian_led_pins: pinmux_leds_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x868, PIN_OUTPUT | MUX_MODE7)
- AM33XX_IOPAD(0x86c, PIN_OUTPUT | MUX_MODE7)
>;
};
@@ -487,6 +494,13 @@
>;
};
+ uart2_pins: pinmux_uart2_pins {
+ pinctrl-single,pins = <
+ AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE1)
+ AM33XX_IOPAD(0x930, PIN_OUTPUT_PULLDOWN | MUX_MODE1)
+ >;
+ };
+
nandflash_pins: pinmux_nandflash_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x800, PIN_INPUT | MUX_MODE0)
diff --git a/arch/arm/dts/am335x-icev2-u-boot.dtsi b/arch/arm/dts/am335x-icev2-u-boot.dtsi
new file mode 100644
index 0000000..cc9569a
--- /dev/null
+++ b/arch/arm/dts/am335x-icev2-u-boot.dtsi
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ */
+/ {
+ xtal25mhz: xtal25mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+};
+
+&i2c0 {
+ cdce913: cdce913@65 {
+ compatible = "ti,cdce913";
+ reg = <0x65>;
+ clocks = <&xtal25mhz>;
+ #clock-cells = <1>;
+ xtal-load-pf = <0>;
+ };
+};
diff --git a/arch/arm/dts/am437x-idk-evm-u-boot.dtsi b/arch/arm/dts/am437x-idk-evm-u-boot.dtsi
index 3aa9195..50fe09c 100644
--- a/arch/arm/dts/am437x-idk-evm-u-boot.dtsi
+++ b/arch/arm/dts/am437x-idk-evm-u-boot.dtsi
@@ -9,6 +9,12 @@
ocp {
u-boot,dm-spl;
};
+
+ xtal25mhz: xtal25mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
};
&uart0 {
@@ -17,6 +23,14 @@
&i2c0 {
u-boot,dm-spl;
+
+ cdce913: cdce913@65 {
+ compatible = "ti,cdce913";
+ reg = <0x65>;
+ clocks = <&xtal25mhz>;
+ #clock-cells = <1>;
+ xtal-load-pf = <0>;
+ };
};
&mmc1 {
diff --git a/arch/arm/dts/am571x-idk-u-boot.dtsi b/arch/arm/dts/am571x-idk-u-boot.dtsi
new file mode 100644
index 0000000..6519920
--- /dev/null
+++ b/arch/arm/dts/am571x-idk-u-boot.dtsi
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#include "am57xx-idk-common-u-boot.dtsi"
diff --git a/arch/arm/dts/am572x-idk-u-boot.dtsi b/arch/arm/dts/am572x-idk-u-boot.dtsi
new file mode 100644
index 0000000..6519920
--- /dev/null
+++ b/arch/arm/dts/am572x-idk-u-boot.dtsi
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#include "am57xx-idk-common-u-boot.dtsi"
diff --git a/arch/arm/dts/am574x-idk-u-boot.dtsi b/arch/arm/dts/am574x-idk-u-boot.dtsi
new file mode 100644
index 0000000..6519920
--- /dev/null
+++ b/arch/arm/dts/am574x-idk-u-boot.dtsi
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#include "am57xx-idk-common-u-boot.dtsi"
diff --git a/arch/arm/dts/am57xx-idk-common-u-boot.dtsi b/arch/arm/dts/am57xx-idk-common-u-boot.dtsi
new file mode 100644
index 0000000..b07aea0
--- /dev/null
+++ b/arch/arm/dts/am57xx-idk-common-u-boot.dtsi
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#include "omap5-u-boot.dtsi"
+
+/ {
+ xtal25mhz: xtal25mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+};
+
+&i2c1 {
+ cdce913: cdce913@65 {
+ compatible = "ti,cdce913";
+ reg = <0x65>;
+ clocks = <&xtal25mhz>;
+ #clock-cells = <1>;
+ xtal-load-pf = <0>;
+ };
+};
diff --git a/arch/arm/dts/bcm63158.dtsi b/arch/arm/dts/bcm63158.dtsi
index 175af38..7dd2858 100644
--- a/arch/arm/dts/bcm63158.dtsi
+++ b/arch/arm/dts/bcm63158.dtsi
@@ -10,6 +10,10 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ spi0 = &hsspi;
+ };
+
cpus {
#address-cells = <2>;
#size-cells = <0>;
@@ -67,6 +71,14 @@
u-boot,dm-pre-reloc;
};
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&periph_osc>;
+ clock-mult = <2>;
+ clock-div = <1>;
+ };
+
refclk50mhz: refclk50mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -192,6 +204,19 @@
status = "disabled";
};
+ hsspi: spi-controller@ff801000 {
+ compatible = "brcm,bcm6328-hsspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0xff801000 0x0 0x600>;
+ clocks = <&hsspi_pll>, <&hsspi_pll>;
+ clock-names = "hsspi", "pll";
+ spi-max-frequency = <100000000>;
+ num-cs = <8>;
+
+ status = "disabled";
+ };
+
nand: nand-controller@ff801800 {
compatible = "brcm,nand-bcm63158",
"brcm,brcmnand-v5.0",
diff --git a/arch/arm/dts/bcm6858.dtsi b/arch/arm/dts/bcm6858.dtsi
index 91f7787..0222562 100644
--- a/arch/arm/dts/bcm6858.dtsi
+++ b/arch/arm/dts/bcm6858.dtsi
@@ -10,6 +10,10 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ spi0 = &hsspi;
+ };
+
cpus {
#address-cells = <2>;
#size-cells = <0>;
@@ -67,6 +71,14 @@
u-boot,dm-pre-reloc;
};
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&periph_osc>;
+ clock-mult = <2>;
+ clock-div = <1>;
+ };
+
refclk50mhz: refclk50mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -192,6 +204,19 @@
status = "disabled";
};
+ hsspi: spi-controller@ff801000 {
+ compatible = "brcm,bcm6328-hsspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0xff801000 0x0 0x600>;
+ clocks = <&hsspi_pll>, <&hsspi_pll>;
+ clock-names = "hsspi", "pll";
+ spi-max-frequency = <100000000>;
+ num-cs = <8>;
+
+ status = "disabled";
+ };
+
nand: nand-controller@ff801800 {
compatible = "brcm,nand-bcm6858",
"brcm,brcmnand-v5.0",
diff --git a/arch/arm/dts/bcm963158.dts b/arch/arm/dts/bcm963158.dts
index 8565944..c2bdd33 100644
--- a/arch/arm/dts/bcm963158.dts
+++ b/arch/arm/dts/bcm963158.dts
@@ -125,3 +125,15 @@
label = "green:aggregate_link";
};
};
+
+&hsspi {
+ status = "okay";
+
+ flash: mt25@0 {
+ compatible = "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ spi-max-frequency = <25000000>;
+ };
+};
diff --git a/arch/arm/dts/bcm968580xref.dts b/arch/arm/dts/bcm968580xref.dts
index 861e989..a034e38 100644
--- a/arch/arm/dts/bcm968580xref.dts
+++ b/arch/arm/dts/bcm968580xref.dts
@@ -124,3 +124,15 @@
label = "green:wps";
};
};
+
+&hsspi {
+ status = "okay";
+
+ flash: mt25@0 {
+ compatible = "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ spi-max-frequency = <25000000>;
+ };
+};
diff --git a/arch/arm/dts/k3-am65-mcu.dtsi b/arch/arm/dts/k3-am65-mcu.dtsi
index c9bfd9b..c42e755 100644
--- a/arch/arm/dts/k3-am65-mcu.dtsi
+++ b/arch/arm/dts/k3-am65-mcu.dtsi
@@ -2,7 +2,7 @@
/*
* Device Tree Source for AM6 SoC Family MCU Domain peripherals
*
- * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
*/
&cbass_mcu {
@@ -26,4 +26,42 @@
clocks = <&k3_clks 114 1>;
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
};
+
+ mcu_r5fss0: r5fss@41000000 {
+ compatible = "ti,am654-r5fss";
+ lockstep-mode = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x41000000 0x00 0x41000000 0x20000>,
+ <0x41400000 0x00 0x41400000 0x20000>;
+ power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>;
+
+ mcu_r5fss0_core0: r5f@41000000 {
+ compatible = "ti,am654-r5f";
+ reg = <0x41000000 0x00008000>,
+ <0x41010000 0x00008000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <159>;
+ ti,sci-proc-ids = <0x01 0xFF>;
+ resets = <&k3_reset 159 1>;
+ atcm-enable = <1>;
+ btcm-enable = <1>;
+ loczrama = <1>;
+ };
+
+ mcu_r5fss0_core1: r5f@41400000 {
+ compatible = "ti,am654-r5f";
+ reg = <0x41400000 0x00008000>,
+ <0x41410000 0x00008000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <245>;
+ ti,sci-proc-ids = <0x02 0xFF>;
+ resets = <&k3_reset 245 1>;
+ atcm-enable = <1>;
+ btcm-enable = <1>;
+ loczrama = <1>;
+ };
+ };
};
diff --git a/arch/arm/dts/k3-am654-base-board.dts b/arch/arm/dts/k3-am654-base-board.dts
index e73b9aa..573ead0 100644
--- a/arch/arm/dts/k3-am654-base-board.dts
+++ b/arch/arm/dts/k3-am654-base-board.dts
@@ -17,6 +17,11 @@
bootargs = "earlycon=ns16550a,mmio32,0x02800000";
};
+ aliases {
+ remoteproc0 = &mcu_r5fss0_core0;
+ remoteproc1 = &mcu_r5fss0_core1;
+ };
+
memory@80000000 {
device_type = "memory";
/* 4G RAM */
diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts
index 7ed307f..e31ed4f 100644
--- a/arch/arm/dts/k3-am654-r5-base-board.dts
+++ b/arch/arm/dts/k3-am654-r5-base-board.dts
@@ -16,6 +16,7 @@
aliases {
serial0 = &wkup_uart0;
+ serial1 = &mcu_uart0;
serial2 = &main_uart0;
};
@@ -118,6 +119,14 @@
status = "okay";
};
+&mcu_uart0 {
+ u-boot,dm-spl;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_uart0_pins_default>;
+ clock-frequency = <48000000>;
+ status = "okay";
+};
+
&main_uart0 {
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};
@@ -141,6 +150,16 @@
u-boot,dm-spl;
};
+ mcu_uart0_pins_default: mcu_uart0_pins_default {
+ pinctrl-single,pins = <
+ AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) /* (P4) MCU_OSPI1_D1.MCU_UART0_RXD */
+ AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) /* (P5) MCU_OSPI1_D2.MCU_UART0_TXD */
+ AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4) /* (P1) MCU_OSPI1_D3.MCU_UART0_CTSn */
+ AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4) /* (N3) MCU_OSPI1_CSn1.MCU_UART0_RTSn */
+ >;
+ u-boot,dm-spl;
+ };
+
wkup_i2c0_pins_default: wkup-i2c0-pins-default {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */
diff --git a/arch/arm/dts/k3-j721e-common-proc-board.dts b/arch/arm/dts/k3-j721e-common-proc-board.dts
index b5b8c3c..c978cab 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-common-proc-board.dts
@@ -12,6 +12,18 @@
stdout-path = "serial2:115200n8";
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
};
+
+ aliases {
+ remoteproc0 = &mcu_r5fss0_core0;
+ remoteproc1 = &mcu_r5fss0_core1;
+ remoteproc2 = &main_r5fss0_core0;
+ remoteproc3 = &main_r5fss0_core1;
+ remoteproc4 = &main_r5fss1_core0;
+ remoteproc5 = &main_r5fss1_core1;
+ remoteproc6 = &c66_0;
+ remoteproc7 = &c66_1;
+ remoteproc8 = &c71_0;
+ };
};
&wkup_uart0 {
@@ -19,6 +31,10 @@
status = "disabled";
};
+&main_uart0 {
+ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
+};
+
&main_uart3 {
/* UART not brought out */
status = "disabled";
diff --git a/arch/arm/dts/k3-j721e-main.dtsi b/arch/arm/dts/k3-j721e-main.dtsi
index 3445784..6bd59ba 100644
--- a/arch/arm/dts/k3-j721e-main.dtsi
+++ b/arch/arm/dts/k3-j721e-main.dtsi
@@ -228,4 +228,115 @@
ti,trm-icp = <0x8>;
dma-coherent;
};
+
+ main_r5fss0: r5fss@5c00000 {
+ compatible = "ti,j721e-r5fss";
+ lockstep-mode = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
+ <0x5d00000 0x00 0x5d00000 0x20000>;
+ power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
+
+ main_r5fss0_core0: r5f@5c00000 {
+ compatible = "ti,j721e-r5f";
+ reg = <0x5c00000 0x00008000>,
+ <0x5c10000 0x00008000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <245>;
+ ti,sci-proc-ids = <0x06 0xFF>;
+ resets = <&k3_reset 245 1>;
+ atcm-enable = <1>;
+ btcm-enable = <1>;
+ loczrama = <1>;
+ };
+
+ main_r5fss0_core1: r5f@5d00000 {
+ compatible = "ti,j721e-r5f";
+ reg = <0x5d00000 0x00008000>,
+ <0x5d10000 0x00008000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <246>;
+ ti,sci-proc-ids = <0x07 0xFF>;
+ resets = <&k3_reset 246 1>;
+ atcm-enable = <1>;
+ btcm-enable = <1>;
+ loczrama = <1>;
+ };
+ };
+
+ main_r5fss1: r5fss@5e00000 {
+ compatible = "ti,j721e-r5fss";
+ lockstep-mode = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
+ <0x5f00000 0x00 0x5f00000 0x20000>;
+ power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>;
+
+ main_r5fss1_core0: r5f@5e00000 {
+ compatible = "ti,j721e-r5f";
+ reg = <0x5e00000 0x00008000>,
+ <0x5e10000 0x00008000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <247>;
+ ti,sci-proc-ids = <0x08 0xFF>;
+ resets = <&k3_reset 247 1>;
+ atcm-enable = <1>;
+ btcm-enable = <1>;
+ loczrama = <1>;
+ };
+
+ main_r5fss1_core1: r5f@5f00000 {
+ compatible = "ti,j721e-r5f";
+ reg = <0x5f00000 0x00008000>,
+ <0x5f10000 0x00008000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <248>;
+ ti,sci-proc-ids = <0x09 0xFF>;
+ resets = <&k3_reset 248 1>;
+ atcm-enable = <1>;
+ btcm-enable = <1>;
+ loczrama = <1>;
+ };
+ };
+
+ c66_0: dsp@4d80800000 {
+ compatible = "ti,j721e-c66-dsp";
+ reg = <0x4d 0x80800000 0x00 0x00048000>,
+ <0x4d 0x80e00000 0x00 0x00008000>,
+ <0x4d 0x80f00000 0x00 0x00008000>;
+ reg-names = "l2sram", "l1pram", "l1dram";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <142>;
+ ti,sci-proc-ids = <0x03 0xFF>;
+ resets = <&k3_reset 142 1>;
+ };
+
+ c66_1: dsp@4d81800000 {
+ compatible = "ti,j721e-c66-dsp";
+ reg = <0x4d 0x81800000 0x00 0x00048000>,
+ <0x4d 0x81e00000 0x00 0x00008000>,
+ <0x4d 0x81f00000 0x00 0x00008000>;
+ reg-names = "l2sram", "l1pram", "l1dram";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <143>;
+ ti,sci-proc-ids = <0x04 0xFF>;
+ resets = <&k3_reset 143 1>;
+ };
+
+ c71_0: dsp@64800000 {
+ compatible = "ti,j721e-c71-dsp";
+ reg = <0x00 0x64800000 0x00 0x00080000>,
+ <0x00 0x64e00000 0x00 0x0000c000>;
+ reg-names = "l2sram", "l1dram";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <15>;
+ ti,sci-proc-ids = <0x30 0xFF>;
+ resets = <&k3_reset 15 1>;
+ };
};
diff --git a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
index 1175fa9..b958b5b 100644
--- a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
@@ -69,4 +69,42 @@
clocks = <&k3_clks 149 0>;
clock-names = "fclk";
};
+
+ mcu_r5fss0: r5fss@41000000 {
+ compatible = "ti,j721e-r5fss";
+ lockstep-mode = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x41000000 0x00 0x41000000 0x20000>,
+ <0x41400000 0x00 0x41400000 0x20000>;
+ power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
+
+ mcu_r5fss0_core0: r5f@41000000 {
+ compatible = "ti,j721e-r5f";
+ reg = <0x41000000 0x00008000>,
+ <0x41010000 0x00008000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <250>;
+ ti,sci-proc-ids = <0x01 0xFF>;
+ resets = <&k3_reset 250 1>;
+ atcm-enable = <1>;
+ btcm-enable = <1>;
+ loczrama = <1>;
+ };
+
+ mcu_r5fss0_core1: r5f@41400000 {
+ compatible = "ti,j721e-r5f";
+ reg = <0x41400000 0x00008000>,
+ <0x41410000 0x00008000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <251>;
+ ti,sci-proc-ids = <0x02 0xFF>;
+ resets = <&k3_reset 251 1>;
+ atcm-enable = <1>;
+ btcm-enable = <1>;
+ loczrama = <1>;
+ };
+ };
};
diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi
index 64079c6..1135b1e 100644
--- a/arch/arm/dts/mt7623.dtsi
+++ b/arch/arm/dts/mt7623.dtsi
@@ -9,8 +9,9 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mt7623-power.h>
-#include <dt-bindings/reset/mtk-reset.h>
+#include <dt-bindings/reset/mt7623-reset.h>
#include "skeleton.dtsi"
/ {
@@ -255,6 +256,133 @@
#reset-cells = <1>;
};
+ pcie: pcie@1a140000 {
+ compatible = "mediatek,mt7623-pcie";
+ device_type = "pci";
+ reg = <0x1a140000 0x1000>, /* PCIe shared registers */
+ <0x1a142000 0x1000>, /* Port0 registers */
+ <0x1a143000 0x1000>, /* Port1 registers */
+ <0x1a144000 0x1000>; /* Port2 registers */
+ reg-names = "subsys", "port0", "port1", "port2";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 0>;
+ interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
+ <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
+ <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
+ <&hifsys CLK_HIFSYS_PCIE0>,
+ <&hifsys CLK_HIFSYS_PCIE1>,
+ <&hifsys CLK_HIFSYS_PCIE2>;
+ clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
+ resets = <&hifsys HIFSYS_PCIE0_RST>,
+ <&hifsys HIFSYS_PCIE1_RST>,
+ <&hifsys HIFSYS_PCIE2_RST>;
+ reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
+ phys = <&pcie0_port PHY_TYPE_PCIE>,
+ <&pcie1_port PHY_TYPE_PCIE>,
+ <&u3port1 PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
+ power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>;
+ bus-range = <0x00 0xff>;
+ status = "disabled";
+ ranges = <0x81000000 0 0x1a160000 0x1a160000 0 0x00010000
+ 0x83000000 0 0x60000000 0x60000000 0 0x10000000>;
+
+ pcie@0,0 {
+ reg = <0x0000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
+ ranges;
+ status = "disabled";
+ };
+
+ pcie@1,0 {
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
+ ranges;
+ status = "disabled";
+ };
+
+ pcie@2,0 {
+ reg = <0x1000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
+ ranges;
+ status = "disabled";
+ };
+ };
+
+ pcie0_phy: pcie-phy@1a149000 {
+ compatible = "mediatek,generic-tphy-v1";
+ reg = <0x1a149000 0x0700>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ pcie0_port: pcie-phy@1a149900 {
+ reg = <0x1a149900 0x0700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
+
+ pcie1_phy: pcie-phy@1a14a000 {
+ compatible = "mediatek,generic-tphy-v1";
+ reg = <0x1a14a000 0x0700>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ pcie1_port: pcie-phy@1a14a900 {
+ reg = <0x1a14a900 0x0700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
+
+ u3phy2: usb-phy@1a244000 {
+ compatible = "mediatek,generic-tphy-v1";
+ reg = <0x1a244000 0x0700>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ u2port1: usb-phy@1a244800 {
+ reg = <0x1a244800 0x0100>;
+ clocks = <&topckgen CLK_TOP_USB_PHY48M>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ u3port1: usb-phy@1a244900 {
+ reg = <0x1a244900 0x0700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
+
ethsys: syscon@1b000000 {
compatible = "mediatek,mt7623-ethsys", "syscon";
reg = <0x1b000000 0x1000>;
diff --git a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
index 51628bb..b0c8621 100644
--- a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
+++ b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
@@ -172,6 +172,13 @@
};
};
+ pcie_default: pcie-default {
+ mux {
+ function = "pcie";
+ groups = "pcie0_0_perst", "pcie1_0_perst";
+ };
+ };
+
uart0_pins_a: uart0-default {
mux {
function = "uart";
@@ -201,6 +208,28 @@
};
};
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_default>;
+ status = "okay";
+
+ pcie@0,0 {
+ status = "okay";
+ };
+
+ pcie@1,0 {
+ status = "okay";
+ };
+};
+
+&pcie0_phy {
+ status = "okay";
+};
+
+&pcie1_phy {
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
diff --git a/arch/arm/dts/mt7629.dtsi b/arch/arm/dts/mt7629.dtsi
index 8ff1916..b0c843b 100644
--- a/arch/arm/dts/mt7629.dtsi
+++ b/arch/arm/dts/mt7629.dtsi
@@ -10,7 +10,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/mt7629-power.h>
-#include <dt-bindings/reset/mtk-reset.h>
+#include <dt-bindings/reset/mt7629-reset.h>
#include "skeleton.dtsi"
/ {
diff --git a/arch/arm/dts/zynq-cse-qspi-single.dts b/arch/arm/dts/zynq-cse-qspi-single.dts
index 0d680df..ac6982a 100644
--- a/arch/arm/dts/zynq-cse-qspi-single.dts
+++ b/arch/arm/dts/zynq-cse-qspi-single.dts
@@ -7,6 +7,10 @@
#include "zynq-cse-qspi.dtsi"
+/ {
+ model = "Zynq CSE QSPI SINGLE Board";
+};
+
&flash0 {
spi-rx-bus-width = <4>;
};
diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts
index 54231cd..d106957 100644
--- a/arch/arm/dts/zynq-zc702.dts
+++ b/arch/arm/dts/zynq-zc702.dts
@@ -16,6 +16,7 @@
serial0 = &uart1;
spi0 = &qspi;
mmc0 = &sdhci0;
+ usb0 = &usb0;
};
memory@0 {
diff --git a/arch/arm/dts/zynqmp-a2197-g-revA.dts b/arch/arm/dts/zynqmp-a2197-g-revA.dts
new file mode 100644
index 0000000..c6072b5
--- /dev/null
+++ b/arch/arm/dts/zynqmp-a2197-g-revA.dts
@@ -0,0 +1,282 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx Versal a2197 RevA System Controller on MGT
+ *
+ * (C) Copyright 2019, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Versal System Controller on a2197 MGT Char board RevA";
+ compatible = "xlnx,zynqmp-a2197-g-revA", "xlnx,zynqmp-a2197-revA",
+ "xlnx,zynqmp-a2197", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem0;
+ gpio0 = &gpio;
+ i2c0 = &i2c0;
+ mmc0 = &sdhci0;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &dcc;
+ usb0 = &usb0;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ xlnx,eeprom = <&eeprom>;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&sdhci0 { /* emmc MIO 13-23 16GB */
+ status = "okay";
+ non-removable;
+ disable-wp;
+ bus-width = <8>;
+ xlnx,mio_bank = <0>;
+};
+
+&uart0 { /* uart0 MIO38-39 */
+ status = "okay";
+ u-boot,dm-pre-reloc;
+};
+
+&gem0 { /* eth MDIO 76/77 */
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "sgmii";
+ is-internal-pcspma;
+ phy0: phy@0 { /* marwell m88e1512 */
+ reg = <0>;
+ reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
+/* xlnx,phy-type = <PHY_TYPE_SGMII>; */
+ };
+/* phy-names = "...";
+ phys = <&lane0 PHY_TYPE_SGMII ... >
+ Note: lane0 sgmii/lane1 usb3 */
+};
+
+&gpio {
+ status = "okay";
+ gpio-line-names = "", "", "", "", "", /* 0 - 4 */
+ "", "", "", "", "", /* 5 - 9 */
+ "", "", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
+ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
+ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
+ "", "", "", "", "", /* 25 - 29 */
+ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
+ "LP_I2C0_PMC_SDA", "", "", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
+ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */
+ "", "", "", "", "", /* 45 - 49 */
+ "", "", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
+ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
+ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */
+ "", "", "", "", "", /* 65 - 69 */
+ "", "", "", "", "", /* 70 - 74 */
+ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
+ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */
+ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */
+ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */
+ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */
+ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */
+ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */
+ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */
+ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */
+ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */
+ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */
+ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */
+ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */
+ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */
+ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */
+ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */
+ "", "", "", "", "", /* 150 - 154 */
+ "", "", "", "", "", /* 155 - 159 */
+ "", "", "", "", "", /* 160 - 164 */
+ "", "", "", "", "", /* 165 - 169 */
+ "", "", "", ""; /* 170 - 174 */
+};
+
+&i2c0 { /* MIO 34-35 - can't stay here */
+ status = "okay";
+ clock-frequency = <400000>;
+ scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
+ i2c-mux@74 { /* u94 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* Use for storing information about SC board */
+ eeprom: eeprom@50 { /* u96 - 24LC32A - 256B */
+ compatible = "atmel,24c32";
+ reg = <0x50>;
+ };
+ };
+ i2c@1 { /* CM_I2C_SCL - Samtec */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ i2c@2 { /* PMBUS - AFX_PMBUS */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ tps544@d { /* u85 */
+ compatible = "ti,tps544b25";
+ reg = <0xd>;
+ };
+ tps544@10 { /* u73 */
+ compatible = "ti,tps544b25";
+ reg = <0x10>;
+ };
+ tps544@11 { /* u76 */
+ compatible = "ti,tps544b25";
+ reg = <0x11>;
+ };
+ tps544@12 { /* u77 */
+ compatible = "ti,tps544b25";
+ reg = <0x12>;
+ };
+ tps544@13 { /* u80 */
+ compatible = "ti,tps544b25";
+ reg = <0x13>;
+ };
+ tps544@14 { /* u81 */
+ compatible = "ti,tps544b25";
+ reg = <0x14>;
+ };
+ tps544@15 { /* u83 */
+ compatible = "ti,tps544b25";
+ reg = <0x15>;
+ };
+ tps544@16 { /* u63 */
+ compatible = "ti,tps544b25";
+ reg = <0x16>;
+ };
+ tps544@17 { /* u66 */
+ compatible = "ti,tps544b25";
+ reg = <0x17>;
+ };
+ tps544@18 { /* u67 */
+ compatible = "ti,tps544b25";
+ reg = <0x18>;
+ };
+ tps544@19 { /* u69 */
+ compatible = "ti,tps544b25";
+ reg = <0x19>;
+ };
+ tps544@1d { /* u88 */
+ compatible = "ti,tps544b25";
+ reg = <0x1d>;
+ };
+ tps544@1e { /* u89 */
+ compatible = "ti,tps544b25";
+ reg = <0x1e>;
+ };
+ tps544@1f { /* u87 */
+ compatible = "ti,tps544b25";
+ reg = <0x1f>;
+ };
+ tps544@20 { /* u71 */
+ compatible = "ti,tps544b25";
+ reg = <0x20>;
+ };
+ ina226@40 { /* u74 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <1000>;
+ };
+ ina226@41 { /* u75 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <1000>;
+ };
+ ina226@42 { /* u78 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ ina226@43 { /* u79 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <1000>;
+ };
+ ina226@44 { /* u82 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <1000>;
+ };
+ ina226@45 { /* u84 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ tps53681@c0 { /* u53 - FIXME name - don't know what it does - also vcc_io_soc */
+ compatible = "ti,tps53681"; /* FIXME no linux driver */
+ reg = <0xc0>;
+ };
+ };
+ i2c@3 { /* fmc1 via JA2G */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ eeprom_fmc1: eeprom@50 { /* on FMC */
+ compatible = "atmel,24c04";
+ reg = <0x50>;
+ };
+ };
+ i2c@4 { /* fmc2 via JA3G */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ eeprom_fmc2: eeprom@50 { /* on FMC */
+ compatible = "atmel,24c04";
+ reg = <0x50>;
+ };
+ };
+ i2c@5 { /* fmc3 via JA4G */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ eeprom_fmc3: eeprom@50 { /* on FMC */
+ compatible = "atmel,24c04";
+ reg = <0x50>;
+ };
+ };
+ i2c@6 { /* ddr dimm */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+ /* 7 unused */
+ };
+};
+
+&usb0 { /* USB0 MIO52-63 */
+ status = "okay";
+ xlnx,usb-polarity = <0>;
+ xlnx,usb-reset-mode = <0>;
+};
+
+&dwc3_0 {
+ status = "okay";
+ dr_mode = "peripheral";
+ maximum-speed = "high-speed";
+};
diff --git a/arch/arm/dts/zynqmp-a2197-m-revA.dts b/arch/arm/dts/zynqmp-a2197-m-revA.dts
new file mode 100644
index 0000000..e4b45ea
--- /dev/null
+++ b/arch/arm/dts/zynqmp-a2197-m-revA.dts
@@ -0,0 +1,461 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx Versal a2197 RevA System Controller
+ *
+ * (C) Copyright 2019, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Versal System Controller on a2197 Memory Char board RevA";
+ compatible = "xlnx,zynqmp-a2197-m-revA", "xlnx,zynqmp-a2197-revA",
+ "xlnx,zynqmp-a2197", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem0;
+ gpio0 = &gpio;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &dcc;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ spi0 = &qspi;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ xlnx,eeprom = <&eeprom>;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>; /* FIXME don't know how big memory is there */
+ };
+};
+
+&qspi {
+ status = "okay";
+ is-dual = <1>;
+ flash@0 {
+ compatible = "m25p80", "spi-flash"; /* 32MB */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <108000000>;
+ };
+};
+
+&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */
+ status = "okay";
+ non-removable;
+ disable-wp;
+ bus-width = <8>;
+ xlnx,mio_bank = <0>; /* FIXME tap delay */
+};
+
+&uart0 { /* uart0 MIO38-39 */
+ status = "okay";
+ u-boot,dm-pre-reloc;
+};
+
+&uart1 { /* uart1 MIO40-41 */
+ status = "okay";
+ u-boot,dm-pre-reloc;
+};
+
+&sdhci1 { /* sd1 MIO45-51 cd in place */
+ status = "disable";
+ no-1-8-v;
+ disable-wp;
+ xlnx,mio_bank = <1>;
+};
+
+&gem0 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "sgmii"; /* DTG generates this properly 1512 */
+ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;
+ phy0: phy@0 { /* marwell m88e1512 - SGMII */
+ reg = <0>;
+/* xlnx,phy-type = <PHY_TYPE_SGMII>; */
+ };
+/* phy-names = "...";
+ phys = <&lane0 PHY_TYPE_SGMII ... >
+ Note: lane0 sgmii/lane1 usb3 */
+};
+
+&gpio {
+ status = "okay";
+ gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */
+ "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */
+ "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
+ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
+ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
+ "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */
+ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
+ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
+ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */
+ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
+ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
+ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
+ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */
+ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */
+ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */
+ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
+ "", "", "", "", "", /* 78 - 79 */
+ "", "", "", "", "", /* 80 - 84 */
+ "", "", "", "", "", /* 85 -89 */
+ "", "", "", "", "", /* 90 - 94 */
+ "", "", "", "", "", /* 95 - 99 */
+ "", "", "", "", "", /* 100 - 104 */
+ "", "", "", "", "", /* 105 - 109 */
+ "", "", "", "", "", /* 110 - 114 */
+ "", "", "", "", "", /* 115 - 119 */
+ "", "", "", "", "", /* 120 - 124 */
+ "", "", "", "", "", /* 125 - 129 */
+ "", "", "", "", "", /* 130 - 134 */
+ "", "", "", "", "", /* 135 - 139 */
+ "", "", "", "", "", /* 140 - 144 */
+ "", "", "", "", "", /* 145 - 149 */
+ "", "", "", "", "", /* 150 - 154 */
+ "", "", "", "", "", /* 155 - 159 */
+ "", "", "", "", "", /* 160 - 164 */
+ "", "", "", "", "", /* 165 - 169 */
+ "", "", "", ""; /* 170 - 174 */
+};
+
+&i2c0 { /* MIO 34-35 - can't stay here */
+ status = "okay";
+ clock-frequency = <400000>;
+ i2c-mux@74 { /* u46 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */
+ i2c@0 { /* PMBUS must be enabled via SW21 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ reg_vcc1v2_lp4: tps544@15 { /* u97 */
+ compatible = "ti,tps544b25";
+ reg = <0x15>;
+ };
+ reg_vcc1v1_lp4: tps544@16 { /* u95 */
+ compatible = "ti,tps544b25";
+ reg = <0x16>;
+ };
+ reg_vdd1_1v8_lp4: tps544@17 { /* u99 */
+ compatible = "ti,tps544b25";
+ reg = <0x17>;
+ };
+ /* UTIL_PMBUS connection */
+ reg_vcc1v8: tps544@13 { /* u92 */
+ compatible = "ti,tps544b25";
+ reg = <0x13>;
+ };
+ reg_vcc3v3: tps544@14 { /* u93 */
+ compatible = "ti,tps544b25";
+ reg = <0x14>;
+ };
+ reg_vcc5v0: tps544@1e { /* u94 */
+ compatible = "ti,tps544b25";
+ reg = <0x1e>;
+ };
+ };
+ i2c@1 { /* PMBUS_INA226 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ vcc_aux: ina226@42 { /* u86 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ vcc_ram: ina226@43 { /* u81 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ vcc1v1_lp4: ina226@46 { /* u96 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <5000>;
+ };
+ vcc1v2_lp4: ina226@47 { /* u98 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>;
+ };
+ vdd1_1v8_lp4: ina226@48 { /* u100 */
+ compatible = "ti,ina226";
+ reg = <0x48>;
+ shunt-resistor = <5000>;
+ };
+ vcc0v6_lp4: ina226@49 { /* u101 */
+ compatible = "ti,ina226";
+ reg = <0x49>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c@2 { /* PMBUS1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ reg_vccint: tps53681@c0 { /* u69 */
+ compatible = "ti,tps53681"; /* FIXME no linux driver */
+ reg = <0xc0>;
+ };
+ reg_vcc_pmc: tps544@7 { /* u80 */
+ compatible = "ti,tps544b25";
+ reg = <0x7>;
+ };
+ reg_vcc_ram: tps544@8 { /* u82 */
+ compatible = "ti,tps544b25";
+ reg = <0x8>;
+ };
+ reg_vcc_pslp: tps544@9 { /* u83 */
+ compatible = "ti,tps544b25";
+ reg = <0x9>;
+ };
+ reg_vcc_psfp: tps544@a { /* u84 */
+ compatible = "ti,tps544b25";
+ reg = <0xa>;
+ };
+ reg_vccaux: tps544@d { /* u85 */
+ compatible = "ti,tps544b25";
+ reg = <0xd>;
+ };
+ reg_vccaux_pmc: tps544@e { /* u87 */
+ compatible = "ti,tps544b25";
+ reg = <0xe>;
+ };
+ reg_vcco_500: tps544@f { /* u88 */
+ compatible = "ti,tps544b25";
+ reg = <0xf>;
+ };
+ reg_vcco_501: tps544@10 { /* u89 */
+ compatible = "ti,tps544b25";
+ reg = <0x10>;
+ };
+ reg_vcco_502: tps544@11 { /* u90 */
+ compatible = "ti,tps544b25";
+ reg = <0x11>;
+ };
+ reg_vcco_503: tps544@12 { /* u91 */
+ compatible = "ti,tps544b25";
+ reg = <0x12>;
+ };
+ };
+ i2c@3 { /* MEM PMBUS - FIXME bug in schematics */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* reg = <3>; */
+ };
+ i2c@4 { /* LP_I2C_SM */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ /* connected to U20G */
+ };
+ /* 5-7 unused */
+ };
+};
+
+/* TODO sysctrl via J239 */
+/* TODO samtec J212G/H via J242 */
+/* TODO teensy via U30 PCA9543A bus 1 */
+&i2c1 { /* i2c1 MIO 36-37 */
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* Must be enabled via J242 */
+ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ };
+
+ i2c-mux@74 { /* u35 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */
+ dc_i2c: i2c@0 { /* DC_I2C */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* Use for storing information about SC board */
+ eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */
+ compatible = "atmel,24c08";
+ reg = <0x54>;
+ };
+ si570_ref_clk: clock-generator@5d { /* u26 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>; /* FIXME addr */
+ temperature-stability = <50>;
+ factory-fout = <156250000>; /* FIXME every chip can be different */
+ clock-frequency = <33333333>;
+ clock-output-names = "REF_CLK"; /* FIXME */
+ };
+ /* Connection via Samtec U20D */
+ /* Use for storing information about X-PRC card */
+ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ };
+
+ /* Use for setting up certain features on X-PRC card */
+ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */
+ compatible = "nxp,pca9534";
+ reg = <0x22>;
+ gpio-controller; /* IRQ not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
+ "", "", "", "";
+ gtr_sel0 {
+ gpio-hog;
+ gpios = <0 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_1";
+ };
+ gtr_sel1 {
+ gpio-hog;
+ gpios = <1 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_2";
+ };
+ gtr_sel2 {
+ gpio-hog;
+ gpios = <2 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_3";
+ };
+ gtr_sel3 {
+ gpio-hog;
+ gpios = <3 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_4";
+ };
+ };
+ };
+ i2c@1 { /* UTIL_PMBUS - FIXME incorrect schematics */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* reg = <1>; */
+ };
+ i2c@2 { /* C0_LP4 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ si570_c0_lp4: clock-generator@5d { /* u10 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>; /* FIXME addr */
+ temperature-stability = <50>;
+ factory-fout = <30000000>;
+ clock-frequency = <30000000>;
+ clock-output-names = "C0_LP4_SI570_CLK";
+ };
+ };
+ i2c@3 { /* C1_LP4 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ si570_c1_lp4: clock-generator@5d { /* u10 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>; /* FIXME addr */
+ temperature-stability = <50>;
+ factory-fout = <30000000>;
+ clock-frequency = <30000000>;
+ clock-output-names = "C1_LP4_SI570_CLK";
+ };
+ };
+ i2c@4 { /* C2_LP4 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ si570_c2_lp4: clock-generator@5d { /* u10 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>; /* FIXME addr */
+ temperature-stability = <50>;
+ factory-fout = <30000000>;
+ clock-frequency = <30000000>;
+ clock-output-names = "C2_LP4_SI570_CLK";
+ };
+ };
+ i2c@5 { /* C3_LP4 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ si570_c3_lp4: clock-generator@5d { /* u15 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>; /* FIXME addr */
+ temperature-stability = <50>;
+ factory-fout = <30000000>;
+ clock-frequency = <30000000>;
+ clock-output-names = "C3_LP4_SI570_CLK";
+ };
+ };
+ i2c@6 { /* HSDP_SI570 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ si570_hsdp: clock-generator@5d { /* u19 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>; /* FIXME addr */
+ temperature-stability = <50>;
+ factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */
+ clock-frequency = <33333333>;
+ clock-output-names = "HSDP_SI570";
+ };
+ };
+ };
+};
+
+&usb0 {
+ status = "okay";
+ xlnx,usb-polarity = <0>;
+ xlnx,usb-reset-mode = <0>;
+};
+
+&dwc3_0 {
+ status = "okay";
+ dr_mode = "host";
+ /* dr_mode = "peripheral"; */
+ maximum-speed = "high-speed";
+};
+
+&usb1 {
+ status = "disabled"; /* not at mem board */
+ xlnx,usb-polarity = <0>;
+ xlnx,usb-reset-mode = <0>;
+};
+
+&dwc3_1 {
+ /delete-property/ phy-names ;
+ /delete-property/ phys ;
+ maximum-speed = "high-speed";
+ snps,dis_u2_susphy_quirk ;
+ snps,dis_u3_susphy_quirk ;
+ status = "disabled";
+};
diff --git a/arch/arm/dts/zynqmp-a2197-p-revA.dts b/arch/arm/dts/zynqmp-a2197-p-revA.dts
new file mode 100644
index 0000000..322b36e
--- /dev/null
+++ b/arch/arm/dts/zynqmp-a2197-p-revA.dts
@@ -0,0 +1,567 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx Versal a2197 RevA System Controller
+ *
+ * (C) Copyright 2019, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */
+ compatible = "xlnx,zynqmp-a2197-p-revA", "xlnx,zynqmp-a2197-revA",
+ "xlnx,zynqmp-a2197", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem0;
+ gpio0 = &gpio;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &dcc;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ xlnx,eeprom = <&eeprom>;
+ /* xlnx,fmc-eeprom = FIXME */
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>; /* FIXME don't know how big memory is there */
+ };
+};
+
+&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */
+ status = "okay";
+ non-removable;
+ disable-wp;
+ bus-width = <8>;
+ xlnx,mio_bank = <0>;
+};
+
+&uart0 { /* uart0 MIO38-39 */
+ status = "okay";
+ u-boot,dm-pre-reloc;
+};
+
+&uart1 { /* uart1 MIO40-41 */
+ status = "okay";
+ u-boot,dm-pre-reloc;
+};
+
+&sdhci1 { /* sd1 MIO45-51 cd in place */
+ status = "okay";
+ no-1-8-v;
+ disable-wp;
+ xlnx,mio_bank = <1>;
+};
+
+&gem0 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "sgmii"; /* DTG generates this properly 1512 */
+ is-internal-pcspma;
+ /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */
+ phy0: phy@0 {
+ reg = <0>;
+ };
+};
+
+&gpio {
+ status = "okay";
+ gpio-line-names = "", "", "", "", "", /* 0 - 4 */
+ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */
+ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
+ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
+ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
+ "", "", "", "", "", /* 25 - 29 */
+ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
+ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
+ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */
+ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
+ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
+ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
+ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */
+ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */
+ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */
+ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
+ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */
+ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */
+ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */
+ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */
+ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */
+ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */
+ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */
+ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */
+ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */
+ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */
+ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */
+ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */
+ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */
+ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */
+ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */
+ "", "", "", "", "", /* 150 - 154 */
+ "", "", "", "", "", /* 155 - 159 */
+ "", "", "", "", "", /* 160 - 164 */
+ "", "", "", "", "", /* 165 - 169 */
+ "", "", "", ""; /* 170 - 174 */
+};
+
+&i2c0 { /* MIO 34-35 - can't stay here */
+ status = "okay";
+ clock-frequency = <400000>;
+ i2c-mux@74 { /* u33 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
+ i2c@0 { /* PMBUS1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* On connector J98 */
+ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0x7>;
+ regulator-name = "reg_vcc_fmc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2600000>;
+ /* enable-gpio = <&gpio0 23 0x4>; optional */
+ };
+ reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0x8>;
+ };
+ reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0x9>;
+ };
+ reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0xa>;
+ };
+ reg_vccint: tps53681@c0 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */
+ compatible = "ti,tps53681"; /* FIXME no linux driver */
+ reg = <0xc0>;
+ /* vccint, vcc_io_soc */
+ };
+ };
+ i2c@1 { /* PMBUS1_INA226 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* FIXME check alerts comming to SC */
+ vcc_fmc: ina226@42 { /* u81 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ vcc_ram: ina226@43 { /* u82 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ vcc_pslp: ina226@44 { /* u84 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <5000>;
+ };
+ vcc_psfp: ina226@45 { /* u87 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c@2 { /* PMBUS2 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* On connector J104 */
+ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0xd>;
+ };
+ reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0xe>;
+ };
+ reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0xf>;
+ };
+ reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0x10>;
+ };
+ reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0x11>;
+ };
+ reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0x12>;
+ };
+ reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0x13>;
+ };
+ reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0x14>;
+ };
+ reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0x15>;
+ };
+ reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0x16>;
+ };
+ reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0x17>;
+ };
+ reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0x19>;
+ };
+ reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0x1a>;
+ };
+ reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0x1b>;
+ };
+ reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0x1c>;
+ };
+ reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0x1d>;
+ };
+ reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0x1e>;
+ };
+ reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */
+ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */
+ reg = <0x1f>;
+ };
+ };
+ i2c@3 { /* PMBUS2_INA226 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* FIXME check alerts coming to SC */
+ vccaux: ina226@40 { /* u89 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <5000>;
+ };
+ vccaux_fmc: ina226@41 { /* u91 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ vcco_500: ina226@42 { /* u92 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ vcco_501: ina226@43 { /* u94 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ vcco_502: ina226@44 { /* u96 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <5000>;
+ };
+ vcco_503: ina226@45 { /* u98 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ vcc_1v8: ina226@46 { /* u100 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <5000>;
+ };
+ vcc_3v3: ina226@47 { /* u103 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>;
+ };
+ vcc_1v2_ddr4: ina226@48 { /* u105 */
+ compatible = "ti,ina226";
+ reg = <0x48>;
+ shunt-resistor = <1000>;
+ };
+ vcc1v1_lp4: ina226@49 { /* u107 */
+ compatible = "ti,ina226";
+ reg = <0x49>;
+ shunt-resistor = <5000>;
+ };
+ vadj_fmc: ina226@4a { /* u110 */
+ compatible = "ti,ina226";
+ reg = <0x4a>;
+ shunt-resistor = <5000>;
+ };
+ mgtyavcc: ina226@4b { /* u112 */
+ compatible = "ti,ina226";
+ reg = <0x4b>;
+ shunt-resistor = <1000>;
+ };
+ mgtyavtt: ina226@4c { /* u113 */
+ compatible = "ti,ina226";
+ reg = <0x4c>;
+ shunt-resistor = <1000>;
+ };
+ mgtyvccaux: ina226@4d { /* u116 */
+ compatible = "ti,ina226";
+ reg = <0x4d>;
+ shunt-resistor = <5000>;
+ };
+ vcc_bat: ina226@4e { /* u12 */
+ compatible = "ti,ina226";
+ reg = <0x4e>;
+ shunt-resistor = <10000000>; /* 10 ohm */
+ };
+ };
+ i2c@4 { /* LP_I2C_SM */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ /* connected to J212G */
+ /* zynqmp sm alert or samtec J212H */
+ };
+ /* 5-7 unused */
+ };
+};
+
+&i2c1 { /* i2c1 MIO 36-37 */
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* Must be enabled via J242 */
+ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ };
+
+ i2c-mux@74 { /* u35 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
+ dc_i2c: i2c@0 { /* DC_I2C */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* Use for storing information about SC board */
+ eeprom: eeprom@54 { /* u34 - m24128 16kB */
+ compatible = "st,24c128", "atmel,24c128";
+ reg = <0x54>;
+ };
+ si570_ref_clk: clock-generator@5d { /* u32 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>; /* 570JAC000900DG */
+ temperature-stability = <50>;
+ factory-fout = <156250000>; /* FIXME every chip can be different */
+ clock-frequency = <33333333>;
+ clock-output-names = "REF_CLK"; /* FIXME */
+ };
+ /* Connection via Samtec J212D */
+ /* Use for storing information about X-PRC card */
+ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ };
+
+ /* Use for setting up certain features on X-PRC card */
+ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */
+ compatible = "nxp,pca9534";
+ reg = <0x22>;
+ gpio-controller; /* IRQ not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
+ "", "", "", "";
+ gtr_sel0 {
+ gpio-hog;
+ gpios = <0 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_1";
+ };
+ gtr_sel1 {
+ gpio-hog;
+ gpios = <1 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_2";
+ };
+ gtr_sel2 {
+ gpio-hog;
+ gpios = <2 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_3";
+ };
+ gtr_sel3 {
+ gpio-hog;
+ gpios = <3 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_4";
+ };
+ };
+ };
+ i2c@1 { /* FMCP1_IIC */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* FIXME connection to Samtec J51C */
+ /* expected eeprom 0x50 SE cards */
+ };
+ i2c@2 { /* FMCP2_IIC */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* FIXME connection to Samtec J53C */
+ /* expected eeprom 0x50 SE cards */
+ };
+ i2c@3 { /* DDR4_DIMM1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ si570_ddr_dimm1: clock-generator@60 { /* u2 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x60>; /* 570BAB000299DG */
+ temperature-stability = <50>;
+ factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */
+ clock-frequency = <33333333>;
+ clock-output-names = "REF_CLK"; /* FIXME */
+ };
+ /* 0x50 SPD? */
+ };
+ i2c@4 { /* DDR4_DIMM2 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ si570_ddr_dimm2: clock-generator@60 { /* u3 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x60>; /* 570BAB000299DG */
+ temperature-stability = <50>;
+ factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */
+ clock-frequency = <33333333>;
+ clock-output-names = "REF_CLK"; /* FIXME */
+ };
+ /* 0x50 SPD? */
+ };
+ i2c@5 { /* LPDDR4_SI570_CLK */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ si570_lpddr4: clock-generator@60 { /* u4 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x60>; /* 570BAB000299DG */
+ temperature-stability = <50>;
+ factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */
+ clock-frequency = <33333333>;
+ clock-output-names = "LPDDR4_SI570_CLK";
+ };
+ };
+ i2c@6 { /* HSDP_SI570 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ si570_hsdp: clock-generator@5d { /* u5 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>; /* 570JAC000900DG */
+ temperature-stability = <50>;
+ factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */
+ clock-frequency = <33333333>;
+ clock-output-names = "HSDP_SI570";
+ };
+ };
+ i2c@7 { /* PCIE_CLK */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */
+ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */
+ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */
+ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */
+ #clock-cells = <1>; /* author David Cater <david.cater@idt.com>*/
+ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */
+ reg = <0xd8>;
+ /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */
+ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */
+
+ };
+
+ };
+ };
+};
+
+&usb0 {
+ status = "okay";
+ xlnx,usb-polarity = <0>;
+ xlnx,usb-reset-mode = <0>;
+};
+
+&dwc3_0 {
+ status = "okay";
+ dr_mode = "peripheral";
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ maximum-speed = "super-speed";
+};
+
+&usb1 {
+ status = "okay";
+ xlnx,usb-polarity = <0>;
+ xlnx,usb-reset-mode = <0>;
+};
+
+&dwc3_1 {
+ /delete-property/ phy-names ;
+ /delete-property/ phys ;
+ dr_mode = "host";
+ maximum-speed = "high-speed";
+ snps,dis_u2_susphy_quirk ;
+ snps,dis_u3_susphy_quirk ;
+ status = "okay";
+};
+
+&xilinx_ams {
+ status = "okay";
+};
+
+&ams_ps {
+ status = "okay";
+};
+
+&ams_pl {
+ status = "okay";
+};
diff --git a/arch/arm/dts/zynqmp-a2197-revA.dts b/arch/arm/dts/zynqmp-a2197-revA.dts
new file mode 100644
index 0000000..3153138
--- /dev/null
+++ b/arch/arm/dts/zynqmp-a2197-revA.dts
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx Versal a2197 RevA System Controller
+ *
+ * (C) Copyright 2019, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Versal System Controller on a2197 board RevA";
+ compatible = "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp";
+
+ aliases {
+ i2c0 = &i2c0;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ xlnx,eeprom = <&eeprom1 &eeprom0 &eeprom0>;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&uart0 { /* uart0 MIO38-39 */
+ status = "okay";
+ u-boot,dm-pre-reloc;
+};
+
+&i2c0 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ clock-frequency = <400000>;
+ i2c-mux@74 { /* this cover MGT board */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ u-boot,dm-pre-reloc;
+ /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* Use for storing information about SC board */
+ eeprom0: eeprom@50 { /* u96 - 24LC32A - 256B */
+ compatible = "atmel,24c32";
+ u-boot,dm-pre-reloc;
+ reg = <0x50>;
+ };
+ };
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ clock-frequency = <400000>;
+ i2c-mux@74 { /* This cover processor board */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ u-boot,dm-pre-reloc;
+ /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* Use for storing information about SC board */
+ eeprom1: eeprom@50 { /* u96 - 24LC32A - 256B */
+ compatible = "atmel,24c32";
+ u-boot,dm-pre-reloc;
+ reg = <0x50>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/zynqmp-clk.dtsi b/arch/arm/dts/zynqmp-clk.dtsi
index a795efd..c70f85a 100644
--- a/arch/arm/dts/zynqmp-clk.dtsi
+++ b/arch/arm/dts/zynqmp-clk.dtsi
@@ -38,6 +38,7 @@
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <300000000>;
+ u-boot,dm-pre-reloc;
};
clk600: clk600 {
diff --git a/arch/arm/dts/zynqmp-mini-qspi.dts b/arch/arm/dts/zynqmp-mini-qspi.dts
index 1716d51..e4ba5ae 100644
--- a/arch/arm/dts/zynqmp-mini-qspi.dts
+++ b/arch/arm/dts/zynqmp-mini-qspi.dts
@@ -64,7 +64,7 @@
&qspi {
status = "okay";
flash0: flash@0 {
- compatible = "n25q512a11", "spi-flash";
+ compatible = "n25q512a11", "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index dfb6ebc..8e35171 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -96,6 +96,29 @@
};
};
+ zynqmp_ipi {
+ u-boot,dm-pre-reloc;
+ compatible = "xlnx,zynqmp-ipi-mailbox";
+ interrupt-parent = <&gic>;
+ interrupts = <0 35 4>;
+ xlnx,ipi-id = <0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ipi_mailbox_pmu1: mailbox@ff990400 {
+ u-boot,dm-pre-reloc;
+ reg = <0x0 0xff9905c0 0x0 0x20>,
+ <0x0 0xff9905e0 0x0 0x20>,
+ <0x0 0xff990e80 0x0 0x20>,
+ <0x0 0xff990ea0 0x0 0x20>;
+ reg-names = "local_request_region" , "local_response_region",
+ "remote_request_region", "remote_response_region";
+ #mbox-cells = <1>;
+ xlnx,ipi-id = <4>;
+ };
+ };
+
dcc: dcc {
compatible = "arm,dcc";
status = "disabled";
@@ -116,11 +139,22 @@
method = "smc";
};
- pmufw: firmware {
- compatible = "xlnx,zynqmp-pm";
- method = "smc";
- interrupt-parent = <&gic>;
- interrupts = <0 35 4>;
+ firmware {
+ zynqmp-firmware {
+ compatible = "xlnx,zynqmp-firmware";
+ method = "smc";
+ #power-domain-cells = <0x1>;
+ u-boot,dm-pre-reloc;
+
+ zynqmp_power: zynqmp-power {
+ u-boot,dm-pre-reloc;
+ compatible = "xlnx,zynqmp-power";
+ interrupt-parent = <&gic>;
+ interrupts = <0 35 4>;
+ mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>;
+ mbox-names = "tx", "rx";
+ };
+ };
};
timer {
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index e6d27b6..723f3cf 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -315,66 +315,10 @@
extern void __readwrite_bug(const char *fn);
-/*
- * If this architecture has PCI memory IO, then define the read/write
- * macros. These should only be used with the cookie passed from
- * ioremap.
- */
-#ifdef __mem_pci
-
-#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; })
-#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
-#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
-
-#define writeb(v,c) __raw_writeb(v,__mem_pci(c))
-#define writew(v,c) __raw_writew(cpu_to_le16(v),__mem_pci(c))
-#define writel(v,c) __raw_writel(cpu_to_le32(v),__mem_pci(c))
-
-#define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l))
-#define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l))
-#define memcpy_toio(c,a,l) _memcpy_toio(__mem_pci(c),(a),(l))
-
-#define eth_io_copy_and_sum(s,c,l,b) \
- eth_copy_and_sum((s),__mem_pci(c),(l),(b))
-
-static inline int
-check_signature(unsigned long io_addr, const unsigned char *signature,
- int length)
-{
- int retval = 0;
- do {
- if (readb(io_addr) != *signature)
- goto out;
- io_addr++;
- signature++;
- length--;
- } while (length);
- retval = 1;
-out:
- return retval;
-}
-
-#else
#define memset_io(a, b, c) memset((void *)(a), (b), (c))
#define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c))
#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c))
-#if !defined(readb)
-
-#define readb(addr) (__readwrite_bug("readb"),0)
-#define readw(addr) (__readwrite_bug("readw"),0)
-#define readl(addr) (__readwrite_bug("readl"),0)
-#define writeb(v,addr) __readwrite_bug("writeb")
-#define writew(v,addr) __readwrite_bug("writew")
-#define writel(v,addr) __readwrite_bug("writel")
-
-#define eth_io_copy_and_sum(a,b,c,d) __readwrite_bug("eth_io_copy_and_sum")
-
-#define check_signature(io,sig,len) (0)
-
-#endif
-#endif /* __mem_pci */
-
/*
* If this architecture has ISA IO, then define the isa_read/isa_write
* macros.
diff --git a/arch/arm/lib/interrupts_64.c b/arch/arm/lib/interrupts_64.c
index 0bfdb8d..a32a4b6 100644
--- a/arch/arm/lib/interrupts_64.c
+++ b/arch/arm/lib/interrupts_64.c
@@ -30,6 +30,17 @@
efi_print_image_infos((void *)regs->elr);
}
+static void dump_instr(struct pt_regs *regs)
+{
+ u32 *addr = (u32 *)(regs->elr & ~3UL);
+ int i;
+
+ printf("Code: ");
+ for (i = -4; i < 1; i++)
+ printf(i == 0 ? "(%08x) " : "%08x ", addr[i]);
+ printf("\n");
+}
+
void show_regs(struct pt_regs *regs)
{
int i;
@@ -44,6 +55,7 @@
printf("x%-2d: %016lx x%-2d: %016lx\n",
i, regs->regs[i], i+1, regs->regs[i+1]);
printf("\n");
+ dump_instr(regs);
}
/*
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index de1c1cc..5583241 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -66,6 +66,27 @@
int
default 16
+config K3_EARLY_CONS
+ bool "Activate to allow for an early console during SPL"
+ depends on SPL
+ help
+ Turn this option on to enable an early console functionality in SPL
+ before the main console is being brought up. This can be useful in
+ situations where the main console is dependent on System Firmware
+ (SYSFW) being up and running, which is usually not the case during
+ the very early stages of boot. Using this early console functionality
+ will allow for an alternate serial port to be used to support things
+ like UART-based boot and early diagnostic messages until the main
+ console is ready to get activated.
+
+config K3_EARLY_CONS_IDX
+ depends on K3_EARLY_CONS
+ int "Index of serial device to use for SPL early console"
+ default 1
+ help
+ Use this option to set the index of the serial device to be used
+ for the early console during SPL execution.
+
config K3_LOAD_SYSFW
bool
depends on SPL
diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c
index 82778d2..7f908ee 100644
--- a/arch/arm/mach-k3/arm64-mmu.c
+++ b/arch/arm/mach-k3/arm64-mmu.c
@@ -14,7 +14,7 @@
#ifdef CONFIG_SOC_K3_AM6
/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
-#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3)
+#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
/* ToDo: Add 64bit IO */
struct mm_region am654_mem_map[NR_MMU_REGIONS] = {
@@ -28,7 +28,19 @@
}, {
.virt = 0x80000000UL,
.phys = 0x80000000UL,
- .size = 0x80000000UL,
+ .size = 0x20000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xa0000000UL,
+ .phys = 0xa0000000UL,
+ .size = 0x02100000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xa2100000UL,
+ .phys = 0xa2100000UL,
+ .size = 0x5df00000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
@@ -68,13 +80,13 @@
}, {
.virt = 0xa0000000UL,
.phys = 0xa0000000UL,
- .size = 0x0bc00000UL,
+ .size = 0x1bc00000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
PTE_BLOCK_NON_SHARE
}, {
- .virt = 0xabc00000UL,
- .phys = 0xabc00000UL,
- .size = 0x54400000UL,
+ .virt = 0xbbc00000UL,
+ .phys = 0xbbc00000UL,
+ .size = 0x44400000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index c16afc6..f8274b3 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -14,19 +14,48 @@
#include <linux/soc/ti/ti_sci_protocol.h>
#include <fdt_support.h>
#include <asm/arch/sys_proto.h>
+#include <asm/hardware.h>
+#include <asm/io.h>
struct ti_sci_handle *get_ti_sci_handle(void)
{
struct udevice *dev;
int ret;
- ret = uclass_get_device(UCLASS_FIRMWARE, 0, &dev);
+ ret = uclass_get_device_by_driver(UCLASS_FIRMWARE,
+ DM_GET_DRIVER(ti_sci), &dev);
if (ret)
panic("Failed to get SYSFW (%d)\n", ret);
return (struct ti_sci_handle *)ti_sci_get_handle_from_sysfw(dev);
}
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_K3_EARLY_CONS
+int early_console_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ gd->baudrate = CONFIG_BAUDRATE;
+
+ ret = uclass_get_device_by_seq(UCLASS_SERIAL, CONFIG_K3_EARLY_CONS_IDX,
+ &dev);
+ if (ret) {
+ printf("Error getting serial dev for early console! (%d)\n",
+ ret);
+ return ret;
+ }
+
+ gd->cur_serial_dev = dev;
+ gd->flags |= GD_FLG_SERIAL_READY;
+ gd->have_console = 1;
+
+ return 0;
+}
+#endif
+
#ifdef CONFIG_SYS_K3_SPL_ATF
void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
{
@@ -164,3 +193,43 @@
{
}
#endif
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+ u32 soc, rev;
+ char *name;
+
+ soc = (readl(CTRLMMR_WKUP_JTAG_DEVICE_ID) &
+ DEVICE_ID_FAMILY_MASK) >> DEVICE_ID_FAMILY_SHIFT;
+ rev = (readl(CTRLMMR_WKUP_JTAG_ID) &
+ JTAG_ID_VARIANT_MASK) >> JTAG_ID_VARIANT_SHIFT;
+
+ printf("SoC: ");
+ switch (soc) {
+ case AM654:
+ name = "AM654";
+ break;
+ case J721E:
+ name = "J721E";
+ break;
+ default:
+ name = "Unknown Silicon";
+ };
+
+ printf("%s PG ", name);
+ switch (rev) {
+ case REV_PG1_0:
+ name = "1.0";
+ break;
+ case REV_PG2_0:
+ name = "2.0";
+ break;
+ default:
+ name = "Unknown Revision";
+ };
+ printf("%s\n", name);
+
+ return 0;
+}
+#endif
diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h
index ac7e80d..8f9a023 100644
--- a/arch/arm/mach-k3/common.h
+++ b/arch/arm/mach-k3/common.h
@@ -8,4 +8,11 @@
#include <asm/armv7_mpu.h>
+#define AM654 2
+#define J721E 4
+
+#define REV_PG1_0 0
+#define REV_PG2_0 1
+
void setup_k3_mpu_regions(void);
+int early_console_init(void);
diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h
index 4e62982..d670d5a 100644
--- a/arch/arm/mach-k3/include/mach/hardware.h
+++ b/arch/arm/mach-k3/include/mach/hardware.h
@@ -13,4 +13,22 @@
#ifdef CONFIG_SOC_K3_J721E
#include "j721e_hardware.h"
#endif
+
+/* Assuming these addresses and definitions stay common across K3 devices */
+#define CTRLMMR_WKUP_JTAG_DEVICE_ID 0x43000018
+#define DEVICE_ID_FAMILY_SHIFT 26
+#define DEVICE_ID_FAMILY_MASK (0x3f << 26)
+#define DEVICE_ID_BASE_SHIFT 11
+#define DEVICE_ID_BASE_MASK (0x1fff << 11)
+#define DEVICE_ID_SPEED_SHIFT 6
+#define DEVICE_ID_SPEED_MASK (0x1f << 6)
+#define DEVICE_ID_TEMP_SHIFT 3
+#define DEVICE_ID_TEMP_MASK (0x7 << 3)
+
+#define CTRLMMR_WKUP_JTAG_ID 0x43000014
+#define JTAG_ID_VARIANT_SHIFT 28
+#define JTAG_ID_VARIANT_MASK (0xf << 28)
+#define JTAG_ID_PARTNO_SHIFT 12
+#define JTAG_ID_PARTNO_MASK (0x7ff << 1)
+
#endif /* _ASM_ARCH_HARDWARE_H_ */
diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c
index 7a482bd..5903bbe 100644
--- a/arch/arm/mach-k3/sysfw-loader.c
+++ b/arch/arm/mach-k3/sysfw-loader.c
@@ -12,6 +12,9 @@
#include <remoteproc.h>
#include <linux/soc/ti/ti_sci_protocol.h>
#include <asm/arch/sys_proto.h>
+#include "common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
/* Name of the FIT image nodes for SYSFW and its config data */
#define SYSFW_FIRMWARE "sysfw.bin"
@@ -215,6 +218,24 @@
#endif
break;
#endif
+#if CONFIG_IS_ENABLED(YMODEM_SUPPORT)
+ case BOOT_DEVICE_UART:
+#ifdef CONFIG_K3_EARLY_CONS
+ /*
+ * Establish a serial console if not yet available as required
+ * for UART-based boot. For this use the early console feature
+ * that allows setting up a UART for use before SYSFW has been
+ * brought up. Note that the associated UART module's clocks
+ * must have gotten enabled by the ROM bootcode which will be
+ * the case when continuing to boot serially from the same
+ * UART that the ROM loaded the initial bootloader from.
+ */
+ if (!gd->have_console)
+ early_console_init();
+#endif
+ ret = spl_ymodem_load_image(&spl_image, &bootdev);
+ break;
+#endif
default:
panic("Loading SYSFW image from device %u not supported!\n",
bootdev.boot_device);
diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig
index 7f6b344..39d9c28 100644
--- a/arch/arm/mach-omap2/am33xx/Kconfig
+++ b/arch/arm/mach-omap2/am33xx/Kconfig
@@ -89,6 +89,7 @@
config TARGET_AM335X_GUARDIAN
bool "Support am335x based guardian board from bosch"
+ select BOARD_LATE_INIT
select DM
select DM_SERIAL
select DM_GPIO
diff --git a/arch/arm/mach-omap2/emif-common.c b/arch/arm/mach-omap2/emif-common.c
index b384343..290f9dc 100644
--- a/arch/arm/mach-omap2/emif-common.c
+++ b/arch/arm/mach-omap2/emif-common.c
@@ -348,52 +348,63 @@
static void dra7_enable_ecc(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
- u32 rgn, size;
+ u32 rgn, rgn_start, size, ctrl_reg;
/* ECC available only on dra76x EMIF1 */
if ((base != EMIF1_BASE) || !is_dra76x())
return;
if (regs->emif_ecc_ctrl_reg & EMIF_ECC_CTRL_REG_ECC_EN_MASK) {
- writel(regs->emif_ecc_address_range_1,
- &emif->emif_ecc_address_range_1);
- writel(regs->emif_ecc_address_range_2,
- &emif->emif_ecc_address_range_2);
- writel(regs->emif_ecc_ctrl_reg, &emif->emif_ecc_ctrl_reg);
-
- /* Set region1 memory with 0 */
- rgn = ((regs->emif_ecc_address_range_1 &
- EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16) +
- CONFIG_SYS_SDRAM_BASE;
- size = (regs->emif_ecc_address_range_1 &
- EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000;
-
- if (regs->emif_ecc_ctrl_reg &
- EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK)
- dra7_reset_ddr_data(rgn, size);
-
- /* Set region2 memory with 0 */
- rgn = ((regs->emif_ecc_address_range_2 &
- EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16) +
- CONFIG_SYS_SDRAM_BASE;
- size = (regs->emif_ecc_address_range_2 &
- EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000;
-
- if (regs->emif_ecc_ctrl_reg &
- EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK)
- dra7_reset_ddr_data(rgn, size);
+ /* Disable high-order interleaving */
+ clrbits_le32(MA_PRIORITY, MA_HIMEM_INTERLEAVE_UN_MASK);
#ifdef CONFIG_DRA7XX
/* Clear the status flags and other history */
writel(readl(&emif->emif_1b_ecc_err_cnt),
&emif->emif_1b_ecc_err_cnt);
writel(0xffffffff, &emif->emif_1b_ecc_err_dist_1);
+ writel(0x2, &emif->emif_1b_ecc_err_addr_log);
writel(0x1, &emif->emif_2b_ecc_err_addr_log);
writel(EMIF_INT_WR_ECC_ERR_SYS_MASK |
EMIF_INT_TWOBIT_ECC_ERR_SYS_MASK |
EMIF_INT_ONEBIT_ECC_ERR_SYS_MASK,
&emif->emif_irqstatus_sys);
#endif
+ writel(regs->emif_ecc_address_range_1,
+ &emif->emif_ecc_address_range_1);
+ writel(regs->emif_ecc_address_range_2,
+ &emif->emif_ecc_address_range_2);
+
+ /* Disable RMW and ECC verification for read accesses */
+ ctrl_reg = (regs->emif_ecc_ctrl_reg &
+ ~EMIF_ECC_REG_RMW_EN_MASK) |
+ EMIF_ECC_CTRL_REG_ECC_VERIFY_DIS_MASK;
+ writel(ctrl_reg, &emif->emif_ecc_ctrl_reg);
+
+ /* Set region1 memory with 0 */
+ rgn_start = (regs->emif_ecc_address_range_1 &
+ EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16;
+ rgn = rgn_start + CONFIG_SYS_SDRAM_BASE;
+ size = (regs->emif_ecc_address_range_1 &
+ EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000 - rgn_start;
+
+ if (regs->emif_ecc_ctrl_reg &
+ EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK)
+ dra7_reset_ddr_data(rgn, size);
+
+ /* Set region2 memory with 0 */
+ rgn_start = (regs->emif_ecc_address_range_2 &
+ EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16;
+ rgn = rgn_start + CONFIG_SYS_SDRAM_BASE;
+ size = (regs->emif_ecc_address_range_2 &
+ EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000 - rgn_start;
+
+ if (regs->emif_ecc_ctrl_reg &
+ EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK)
+ dra7_reset_ddr_data(rgn, size);
+
+ /* Default value enables RMW and ECC verification */
+ writel(regs->emif_ecc_ctrl_reg, &emif->emif_ecc_ctrl_reg);
}
}
diff --git a/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c b/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c
index e2abb7d..9eda57c 100644
--- a/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c
+++ b/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c
@@ -202,8 +202,9 @@
return;
}
- if (!ret)
- ret = isolate_io(DEISOLATE_IO);
+ /* Deisolate IO if it is already isolated */
+ if (readl((*ctrl)->ctrl_core_sma_sw_0) & CTRL_ISOLATE_MASK)
+ isolate_io(DEISOLATE_IO);
/* lock IODELAY CONFIG registers */
writel(CFG_IODELAY_LOCK_KEY, (*ctrl)->iodelay_config_base +
@@ -240,6 +241,12 @@
debug("IODELAY: IO delay recalibration successfully completed\n");
}
+ /* If there is an error during iodelay recalibration, SoC is in a bad
+ * state. Do not progress any further.
+ */
+ if (ret)
+ hang();
+
return;
}
diff --git a/arch/arm/mach-versal/Kconfig b/arch/arm/mach-versal/Kconfig
index 26d1756..a08e5ae 100644
--- a/arch/arm/mach-versal/Kconfig
+++ b/arch/arm/mach-versal/Kconfig
@@ -36,11 +36,6 @@
config ZYNQ_SDHCI_MAX_FREQ
default 200000000
-config VERSAL_OF_BOARD_DTB_ADDR
- hex
- default 0x1000
- depends on OF_BOARD
-
config IOU_SWITCH_DIVISOR0
hex "IOU switch divisor0"
default 0x20
@@ -54,4 +49,11 @@
MMU table than the one which will be allocated during
relocation.
+config DEFINE_TCM_OCM_MMAP
+ bool "Define TCM and OCM memory in MMU Table"
+ default y if MP
+ help
+ This option if enabled defines the TCM and OCM memory and its
+ memory attributes in MMU table entry.
+
endif
diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c
index 70c1908..49f1e51 100644
--- a/arch/arm/mach-versal/cpu.c
+++ b/arch/arm/mach-versal/cpu.c
@@ -12,14 +12,21 @@
DECLARE_GLOBAL_DATA_PTR;
-static struct mm_region versal_mem_map[] = {
+#define VERSAL_MEM_MAP_USED 5
+
+#define DRAM_BANKS CONFIG_NR_DRAM_BANKS
+
+#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
+#define TCM_MAP 1
+#else
+#define TCM_MAP 0
+#endif
+
+/* +1 is end of list which needs to be empty */
+#define VERSAL_MEM_MAP_MAX (VERSAL_MEM_MAP_USED + DRAM_BANKS + TCM_MAP + 1)
+
+static struct mm_region versal_mem_map[VERSAL_MEM_MAP_MAX] = {
{
- .virt = 0x0UL,
- .phys = 0x0UL,
- .size = 0x80000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
.virt = 0x80000000UL,
.phys = 0x80000000UL,
.size = 0x70000000UL,
@@ -34,12 +41,6 @@
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
- .virt = 0xffe00000UL,
- .phys = 0xffe00000UL,
- .size = 0x00200000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
.virt = 0x400000000UL,
.phys = 0x400000000UL,
.size = 0x200000000UL,
@@ -59,12 +60,36 @@
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
- /* List terminator */
- 0,
}
};
+void mem_map_fill(void)
+{
+ int banks = VERSAL_MEM_MAP_USED;
+
+#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
+ versal_mem_map[banks].virt = 0xffe00000UL;
+ versal_mem_map[banks].phys = 0xffe00000UL;
+ versal_mem_map[banks].size = 0x00200000UL;
+ versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE;
+ banks = banks + 1;
+#endif
+
+ for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ /* Zero size means no more DDR that's this is end */
+ if (!gd->bd->bi_dram[i].size)
+ break;
+
+ versal_mem_map[banks].virt = gd->bd->bi_dram[i].start;
+ versal_mem_map[banks].phys = gd->bd->bi_dram[i].start;
+ versal_mem_map[banks].size = gd->bd->bi_dram[i].size;
+ versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE;
+ banks = banks + 1;
+ }
+}
+
struct mm_region *mem_map = versal_mem_map;
u64 get_page_table_size(void)
@@ -83,16 +108,27 @@
}
#endif
-#if defined(CONFIG_OF_BOARD)
-void *board_fdt_blob_setup(void)
+int versal_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
+ u32 arg3, u32 *ret_payload)
{
- static void *fw_dtb = (void *)CONFIG_VERSAL_OF_BOARD_DTB_ADDR;
+ struct pt_regs regs;
- if (fdt_magic(fw_dtb) != FDT_MAGIC) {
- printf("DTB is not passed via %llx\n", (u64)fw_dtb);
- return NULL;
+ if (current_el() == 3)
+ return 0;
+
+ regs.regs[0] = PM_SIP_SVC | api_id;
+ regs.regs[1] = ((u64)arg1 << 32) | arg0;
+ regs.regs[2] = ((u64)arg3 << 32) | arg2;
+
+ smc_call(®s);
+
+ if (ret_payload) {
+ ret_payload[0] = (u32)regs.regs[0];
+ ret_payload[1] = upper_32_bits(regs.regs[0]);
+ ret_payload[2] = (u32)regs.regs[1];
+ ret_payload[3] = upper_32_bits(regs.regs[1]);
+ ret_payload[4] = (u32)regs.regs[2];
}
- return fw_dtb;
+ return regs.regs[0];
}
-#endif
diff --git a/arch/arm/mach-versal/include/mach/hardware.h b/arch/arm/mach-versal/include/mach/hardware.h
index 23fbc3d..e26beab 100644
--- a/arch/arm/mach-versal/include/mach/hardware.h
+++ b/arch/arm/mach-versal/include/mach/hardware.h
@@ -51,3 +51,26 @@
};
#define rpu_base ((struct rpu_regs *)VERSAL_RPU_BASEADDR)
+
+#define VERSAL_CRP_BASEADDR 0xF1260000
+
+struct crp_regs {
+ u32 reserved0[128];
+ u32 boot_mode_usr;
+};
+
+#define crp_base ((struct crp_regs *)VERSAL_CRP_BASEADDR)
+
+/* Bootmode setting values */
+#define BOOT_MODES_MASK 0x0000000F
+#define QSPI_MODE_24BIT 0x00000001
+#define QSPI_MODE_32BIT 0x00000002
+#define SD_MODE 0x00000003 /* sd 0 */
+#define SD_MODE1 0x00000005 /* sd 1 */
+#define EMMC_MODE 0x00000006
+#define USB_MODE 0x00000007
+#define OSPI_MODE 0x00000008
+#define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */
+#define JTAG_MODE 0x00000000
+#define BOOT_MODE_USE_ALT 0x100
+#define BOOT_MODE_ALT_SHIFT 12
diff --git a/arch/arm/mach-versal/include/mach/sys_proto.h b/arch/arm/mach-versal/include/mach/sys_proto.h
index 1dc7bf6..2f5ad02 100644
--- a/arch/arm/mach-versal/include/mach/sys_proto.h
+++ b/arch/arm/mach-versal/include/mach/sys_proto.h
@@ -8,4 +8,65 @@
TCM_SPLIT,
};
+enum pm_api_id {
+ PM_GET_API_VERSION = 1,
+ PM_SET_CONFIGURATION,
+ PM_GET_NODE_STATUS,
+ PM_GET_OPERATING_CHARACTERISTIC,
+ PM_REGISTER_NOTIFIER,
+ PM_REQUEST_SUSPEND,
+ PM_SELF_SUSPEND,
+ PM_FORCE_POWERDOWN,
+ PM_ABORT_SUSPEND,
+ PM_REQUEST_WAKEUP,
+ PM_SET_WAKEUP_SOURCE,
+ PM_SYSTEM_SHUTDOWN,
+ PM_REQUEST_NODE,
+ PM_RELEASE_NODE,
+ PM_SET_REQUIREMENT,
+ PM_SET_MAX_LATENCY,
+ PM_RESET_ASSERT,
+ PM_RESET_GET_STATUS,
+ PM_MMIO_WRITE,
+ PM_MMIO_READ,
+ PM_PM_INIT_FINALIZE,
+ PM_FPGA_LOAD,
+ PM_FPGA_GET_STATUS,
+ PM_GET_CHIPID,
+ PM_SECURE_SHA = 26,
+ PM_SECURE_RSA,
+ PM_PINCTRL_REQUEST,
+ PM_PINCTRL_RELEASE,
+ PM_PINCTRL_GET_FUNCTION,
+ PM_PINCTRL_SET_FUNCTION,
+ PM_PINCTRL_CONFIG_PARAM_GET,
+ PM_PINCTRL_CONFIG_PARAM_SET,
+ PM_IOCTL,
+ PM_QUERY_DATA,
+ PM_CLOCK_ENABLE,
+ PM_CLOCK_DISABLE,
+ PM_CLOCK_GETSTATE,
+ PM_CLOCK_SETDIVIDER,
+ PM_CLOCK_GETDIVIDER,
+ PM_CLOCK_SETRATE,
+ PM_CLOCK_GETRATE,
+ PM_CLOCK_SETPARENT,
+ PM_CLOCK_GETPARENT,
+ PM_SECURE_IMAGE,
+ PM_FPGA_READ = 46,
+ PM_SECURE_AES,
+ PM_CLOCK_PLL_GETPARAM = 49,
+ PM_REGISTER_ACCESS = 52,
+ PM_EFUSE_ACCESS,
+ PM_FEATURE_CHECK = 63,
+ PM_API_MAX,
+};
+
+#define PM_SIP_SVC 0xC2000000
+#define PAYLOAD_ARG_CNT 4U
+
void tcm_init(u8 mode);
+void mem_map_fill(void);
+
+int versal_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
+ u32 arg3, u32 *ret_payload);
diff --git a/arch/arm/mach-zynqmp/Makefile b/arch/arm/mach-zynqmp/Makefile
index f3765e4..8a3b074 100644
--- a/arch/arm/mach-zynqmp/Makefile
+++ b/arch/arm/mach-zynqmp/Makefile
@@ -8,7 +8,3 @@
obj-$(CONFIG_MP) += mp.o
obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o
obj-$(CONFIG_ZYNQMP_PSU_INIT_ENABLED) += psu_spl_init.o
-
-ifneq ($(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE),"")
-obj-$(CONFIG_SPL_BUILD) += pmu_ipc.o
-endif
diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c
index 5ef1a52..bb21cbc 100644
--- a/arch/arm/mach-zynqmp/cpu.c
+++ b/arch/arm/mach-zynqmp/cpu.c
@@ -9,6 +9,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/armv8/mmu.h>
#include <asm/io.h>
+#include <zynqmp_firmware.h>
#define ZYNQ_SILICON_VER_MASK 0xF000
#define ZYNQ_SILICON_VER_SHIFT 12
@@ -179,29 +180,6 @@
return regs.regs[0];
}
-unsigned int __maybe_unused zynqmp_pmufw_version(void)
-{
- int ret;
- u32 ret_payload[PAYLOAD_ARG_CNT];
- static u32 pm_api_version = ZYNQMP_PM_VERSION_INVALID;
-
- /*
- * Get PMU version only once and later
- * just return stored values instead of
- * asking PMUFW again.
- */
- if (pm_api_version == ZYNQMP_PM_VERSION_INVALID) {
- ret = invoke_smc(ZYNQMP_SIP_SVC_GET_API_VERSION, 0, 0, 0, 0,
- ret_payload);
- pm_api_version = ret_payload[1];
-
- if (ret)
- panic("PMUFW is not found - Please load it!\n");
- }
-
- return pm_api_version;
-}
-
static int zynqmp_mmio_rawwrite(const u32 address,
const u32 mask,
const u32 value)
diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h
index 915badc..69e729f 100644
--- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h
+++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h
@@ -10,7 +10,6 @@
#define PAYLOAD_ARG_CNT 5
#define ZYNQMP_CSU_SILICON_VER_MASK 0xF
-#define ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD 0xC200002D
#define KEY_PTR_LEN 32
#define ZYNQMP_FPGA_BIT_AUTH_DDR 1
@@ -21,21 +20,6 @@
#define ZYNQMP_FPGA_AUTH_DDR 1
-#define ZYNQMP_SIP_SVC_GET_API_VERSION 0xC2000001
-
-#define ZYNQMP_PM_VERSION_MAJOR 1
-#define ZYNQMP_PM_VERSION_MINOR 0
-#define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16
-#define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF
-
-#define ZYNQMP_PM_VERSION \
- ((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \
- ZYNQMP_PM_VERSION_MINOR)
-
-#define ZYNQMP_PM_VERSION_INVALID ~0
-
-#define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0)
-
enum {
IDCODE,
VERSION,
@@ -54,12 +38,16 @@
TCM_SPLIT,
};
+struct zynqmp_ipi_msg {
+ size_t len;
+ u32 *buf;
+};
+
int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);
unsigned int zynqmp_get_silicon_version(void);
void handoff_setup(void);
-unsigned int zynqmp_pmufw_version(void);
int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
int zynqmp_mmio_read(const u32 address, u32 *value);
int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3,
@@ -72,6 +60,4 @@
void tcm_init(u8 mode);
#endif
-void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size);
-
#endif /* _ASM_ARCH_SYS_PROTO_H */
diff --git a/arch/arm/mach-zynqmp/pmu_ipc.c b/arch/arm/mach-zynqmp/pmu_ipc.c
deleted file mode 100644
index d8858ea..0000000
--- a/arch/arm/mach-zynqmp/pmu_ipc.c
+++ /dev/null
@@ -1,112 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Inter-Processor Communication with the Platform Management Unit (PMU)
- * firmware.
- *
- * (C) Copyright 2019 Luca Ceresoli
- * Luca Ceresoli <luca@lucaceresoli.net>
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
-
-/* IPI bitmasks, register base and register offsets */
-#define IPI_BIT_MASK_APU 0x00001
-#define IPI_BIT_MASK_PMU0 0x10000
-#define IPI_REG_BASE_APU 0xFF300000
-#define IPI_REG_BASE_PMU0 0xFF330000
-#define IPI_REG_OFFSET_TRIG 0x00
-#define IPI_REG_OFFSET_OBR 0x04
-
-/* IPI mailbox buffer offsets */
-#define IPI_BUF_BASE_APU 0xFF990400
-#define IPI_BUF_OFFSET_TARGET_PMU 0x1C0
-#define IPI_BUF_OFFSET_REQ 0x00
-#define IPI_BUF_OFFSET_RESP 0x20
-
-#define PMUFW_PAYLOAD_ARG_CNT 8
-
-/* PMUFW commands */
-#define PMUFW_CMD_SET_CONFIGURATION 2
-
-static void pmu_ipc_send_request(const u32 *req, size_t req_len)
-{
- u32 *mbx = (u32 *)(IPI_BUF_BASE_APU +
- IPI_BUF_OFFSET_TARGET_PMU +
- IPI_BUF_OFFSET_REQ);
- size_t i;
-
- for (i = 0; i < req_len; i++)
- writel(req[i], &mbx[i]);
-}
-
-static void pmu_ipc_read_response(unsigned int *value, size_t count)
-{
- u32 *mbx = (u32 *)(IPI_BUF_BASE_APU +
- IPI_BUF_OFFSET_TARGET_PMU +
- IPI_BUF_OFFSET_RESP);
- size_t i;
-
- for (i = 0; i < count; i++)
- value[i] = readl(&mbx[i]);
-}
-
-/**
- * Send request to PMU and get the response.
- *
- * @req: Request buffer. Byte 0 is the API ID, other bytes are optional
- * parameters.
- * @req_len: Request length in number of 32-bit words.
- * @res: Response buffer. Byte 0 is the error code, other bytes are
- * optional parameters. Optional, if @res_maxlen==0 the parameters
- * will not be read.
- * @res_maxlen: Space allocated for the response in number of 32-bit words.
- *
- * @return Error code returned by the PMU (i.e. the first word of the response)
- */
-static int pmu_ipc_request(const u32 *req, size_t req_len,
- u32 *res, size_t res_maxlen)
-{
- u32 status;
-
- if (req_len > PMUFW_PAYLOAD_ARG_CNT ||
- res_maxlen > PMUFW_PAYLOAD_ARG_CNT)
- return -EINVAL;
-
- pmu_ipc_send_request(req, req_len);
-
- /* Raise Inter-Processor Interrupt to PMU and wait for response */
- writel(IPI_BIT_MASK_PMU0, IPI_REG_BASE_APU + IPI_REG_OFFSET_TRIG);
- do {
- status = readl(IPI_REG_BASE_APU + IPI_REG_OFFSET_OBR);
- } while (status & IPI_BIT_MASK_PMU0);
-
- pmu_ipc_read_response(res, res_maxlen);
-
- return 0;
-}
-
-/**
- * Send a configuration object to the PMU firmware.
- *
- * @cfg_obj: Pointer to the configuration object
- * @size: Size of @cfg_obj in bytes
- */
-void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size)
-{
- const u32 request[] = {
- PMUFW_CMD_SET_CONFIGURATION,
- (u32)((u64)cfg_obj)
- };
- u32 response;
- int err;
-
- printf("Loading PMUFW cfg obj (%ld bytes)\n", size);
-
- err = pmu_ipc_request(request, ARRAY_SIZE(request), &response, 1);
- if (err)
- panic("Cannot load PMUFW configuration object (%d)\n", err);
- if (response != 0)
- panic("PMUFW returned 0x%08x status!\n", response);
-}
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 5cc68d6..5ce8261 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -20,6 +20,14 @@
endchoice
+config STACK_SIZE
+ hex "Define max stack size that can be used by u-boot"
+ default 0x200000
+ help
+ Defines Max stack size that can be used by u-boot so that the
+ initrd_high will be calculated as base stack pointer minus this
+ stack size.
+
source "board/xilinx/microblaze-generic/Kconfig"
config SPL_LDSCRIPT
diff --git a/arch/microblaze/include/asm/config.h b/arch/microblaze/include/asm/config.h
index 45966ee..1124272 100644
--- a/arch/microblaze/include/asm/config.h
+++ b/arch/microblaze/include/asm/config.h
@@ -6,8 +6,12 @@
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
+#define CONFIG_LMB
+
#ifndef CONFIG_SPL_BUILD
#define CONFIG_NEEDS_MANUAL_RELOC
#endif
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
+
#endif
diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c
index ec33294..11e5347 100644
--- a/arch/microblaze/lib/bootm.c
+++ b/arch/microblaze/lib/bootm.c
@@ -15,71 +15,111 @@
#include <u-boot/zlib.h>
#include <asm/byteorder.h>
-int do_bootm_linux(int flag, int argc, char * const argv[],
- bootm_headers_t *images)
+DECLARE_GLOBAL_DATA_PTR;
+
+static ulong get_sp(void)
{
- /* First parameter is mapped to $r5 for kernel boot args */
- void (*thekernel) (char *, ulong, ulong);
- char *commandline = env_get("bootargs");
- ulong rd_data_start, rd_data_end;
+ ulong ret;
+
+ asm("addik %0, r1, 0" : "=r"(ret) : );
+ return ret;
+}
+
+void arch_lmb_reserve(struct lmb *lmb)
+{
+ ulong sp, bank_end;
+ int bank;
/*
- * allow the PREP bootm subcommand, it is required for bootm to work
+ * Booting a (Linux) kernel image
+ *
+ * Allocate space for command line and board info - the
+ * address should be as high as possible within the reach of
+ * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused
+ * memory, which means far enough below the current stack
+ * pointer.
*/
- if (flag & BOOTM_STATE_OS_PREP)
- return 0;
+ sp = get_sp();
+ debug("## Current stack ends at 0x%08lx ", sp);
- if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
- return 1;
+ /* adjust sp by 4K to be safe */
+ sp -= 4096;
+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+ if (sp < gd->bd->bi_dram[bank].start)
+ continue;
+ bank_end = gd->bd->bi_dram[bank].start +
+ gd->bd->bi_dram[bank].size;
+ if (sp >= bank_end)
+ continue;
+ lmb_reserve(lmb, sp, bank_end - sp);
+ break;
+ }
+}
- int ret;
-
- char *of_flat_tree = NULL;
-#if defined(CONFIG_OF_LIBFDT)
- /* did generic code already find a device tree? */
- if (images->ft_len)
- of_flat_tree = images->ft_addr;
-#endif
+static void boot_jump_linux(bootm_headers_t *images, int flag)
+{
+ void (*thekernel)(char *cmdline, ulong rd, ulong dt);
+ ulong dt = (ulong)images->ft_addr;
+ ulong rd_start = images->initrd_start;
+ ulong cmdline = images->cmdline_start;
+ int fake = (flag & BOOTM_STATE_OS_FAKE_GO);
thekernel = (void (*)(char *, ulong, ulong))images->ep;
- /* find ramdisk */
- ret = boot_get_ramdisk(argc, argv, images, IH_ARCH_MICROBLAZE,
- &rd_data_start, &rd_data_end);
- if (ret)
- return 1;
-
- bootstage_mark(BOOTSTAGE_ID_RUN_OS);
-
- if (!of_flat_tree && argc > 1)
- of_flat_tree = (char *)simple_strtoul(argv[1], NULL, 16);
-
- /* fixup the initrd now that we know where it should be */
- if (images->rd_start && images->rd_end && of_flat_tree) {
- ret = fdt_initrd(of_flat_tree, images->rd_start,
- images->rd_end);
- if (ret)
- return 1;
- }
-
#ifdef DEBUG
printf("## Transferring control to Linux (at address 0x%08lx) ",
(ulong)thekernel);
- printf("ramdisk 0x%08lx, FDT 0x%08lx...\n",
- rd_data_start, (ulong) of_flat_tree);
+ printf("cmdline 0x%08lx, ramdisk 0x%08lx, FDT 0x%08lx...\n",
+ cmdline, rd_start, dt);
#endif
#ifdef XILINX_USE_DCACHE
flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
#endif
- /*
- * Linux Kernel Parameters (passing device tree):
- * r5: pointer to command line
- * r6: pointer to ramdisk
- * r7: pointer to the fdt, followed by the board info data
- */
- thekernel(commandline, rd_data_start, (ulong)of_flat_tree);
- /* does not return */
+ if (!fake) {
+ /*
+ * Linux Kernel Parameters (passing device tree):
+ * r5: pointer to command line
+ * r6: pointer to ramdisk
+ * r7: pointer to the fdt, followed by the board info data
+ */
+ thekernel((char *)cmdline, rd_start, dt);
+ /* does not return */
+ }
+}
+
+static void boot_prep_linux(bootm_headers_t *images)
+{
+ if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
+ printf("using: FDT\n");
+ if (image_setup_linux(images)) {
+ printf("FDT creation failed! hanging...");
+ hang();
+ }
+ }
+}
+
+int do_bootm_linux(int flag, int argc, char * const argv[],
+ bootm_headers_t *images)
+{
+ images->cmdline_start = (ulong)env_get("bootargs");
+
+ /* cmdline init is the part of 'prep' and nothing to do for 'bdt' */
+ if (flag & BOOTM_STATE_OS_BD_T || flag & BOOTM_STATE_OS_CMDLINE)
+ return -1;
+
+ if (flag & BOOTM_STATE_OS_PREP) {
+ boot_prep_linux(images);
+ return 0;
+ }
+
+ if (flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO)) {
+ boot_jump_linux(images, flag);
+ return 0;
+ }
+
+ boot_prep_linux(images);
+ boot_jump_linux(images, flag);
return 1;
}
diff --git a/board/bosch/guardian/board.c b/board/bosch/guardian/board.c
index ec0c4a17..072aa4e 100644
--- a/board/bosch/guardian/board.c
+++ b/board/bosch/guardian/board.c
@@ -172,6 +172,8 @@
int board_init(void)
{
+ save_omap_boot_params();
+
#if defined(CONFIG_HW_WATCHDOG)
hw_watchdog_init();
#endif
@@ -183,3 +185,54 @@
#endif
return 0;
}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+static void set_bootmode_env(void)
+{
+ char *boot_device_name = NULL;
+ char *boot_mode_gpio = "gpio@44e07000_14";
+ int ret;
+ int value;
+
+ struct gpio_desc boot_mode_desc;
+
+ switch (gd->arch.omap_boot_device) {
+ case BOOT_DEVICE_NAND:
+ boot_device_name = "nand";
+ break;
+ case BOOT_DEVICE_USBETH:
+ boot_device_name = "usbeth";
+ break;
+ default:
+ break;
+ }
+
+ if (boot_device_name)
+ env_set("boot_device", boot_device_name);
+
+ ret = dm_gpio_lookup_name(boot_mode_gpio, &boot_mode_desc);
+ if (ret) {
+ printf("%s is not found\n", boot_mode_gpio);
+ goto err;
+ }
+
+ ret = dm_gpio_request(&boot_mode_desc, "setup_bootmode_env");
+ if (ret && ret != -EBUSY) {
+ printf("requesting gpio: %s failed\n", boot_mode_gpio);
+ goto err;
+ }
+
+ value = dm_gpio_get_value(&boot_mode_desc);
+ value ? env_set("swi_status", "0") : env_set("swi_status", "1");
+ return;
+
+err:
+ env_set("swi_status", "err");
+}
+
+int board_late_init(void)
+{
+ set_bootmode_env();
+ return 0;
+}
+#endif /* CONFIG_BOARD_LATE_INIT */
diff --git a/board/bosch/guardian/mux.c b/board/bosch/guardian/mux.c
index 708c3e7..20a1f25 100644
--- a/board/bosch/guardian/mux.c
+++ b/board/bosch/guardian/mux.c
@@ -26,24 +26,16 @@
{-1},
};
-static struct module_pin_mux adc_voltages_en[] = {
- {OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUP_EN)},
- {-1},
-};
-
-static struct module_pin_mux asp_power_en[] = {
- {OFFSET(mcasp0_aclkx), (MODE(7) | PULLUP_EN)},
- {-1},
-};
-
-static struct module_pin_mux switch_off_3v6_pin_mux[] = {
- {OFFSET(mii1_txd0), (MODE(7) | PULLUP_EN)},
- /*
- * The uart1 lines are made floating inputs, based on the Guardian
- * A2 Sample Power Supply Schematics
- */
- {OFFSET(uart1_rxd), (MODE(7) | PULLUDDIS)},
- {OFFSET(uart1_txd), (MODE(7) | PULLUDDIS)},
+static struct module_pin_mux guardian_interfaces_pin_mux[] = {
+ {OFFSET(mcasp0_ahclkx), (MODE(7) | PULLDOWN_EN)},
+ {OFFSET(mcasp0_aclkx), (MODE(7) | PULLUP_EN)},
+ {OFFSET(mii1_txd0), (MODE(7) | PULLUP_EN)},
+ {OFFSET(uart1_rxd), (MODE(7) | RXACTIVE | PULLUDDIS)},
+ {OFFSET(uart1_txd), (MODE(7) | PULLUDDIS)},
+ {OFFSET(mii1_crs), (MODE(7) | PULLDOWN_EN)},
+ {OFFSET(rmii1_refclk), (MODE(7) | PULLDOWN_EN)},
+ {OFFSET(mii1_txd3), (MODE(7) | PULLUDDIS)},
+ {OFFSET(mii1_rxdv), (MODE(7) | PULLDOWN_EN)},
{-1},
};
@@ -93,7 +85,5 @@
#ifdef CONFIG_NAND
configure_module_pin_mux(nand_pin_mux);
#endif
- configure_module_pin_mux(adc_voltages_en);
- configure_module_pin_mux(asp_power_en);
- configure_module_pin_mux(switch_off_3v6_pin_mux);
+ configure_module_pin_mux(guardian_interfaces_pin_mux);
}
diff --git a/board/sandbox/MAINTAINERS b/board/sandbox/MAINTAINERS
index df29abe..433be48 100644
--- a/board/sandbox/MAINTAINERS
+++ b/board/sandbox/MAINTAINERS
@@ -13,13 +13,6 @@
F: include/configs/sandbox.h
F: configs/sandbox64_defconfig
-SANDBOX_NOBLK BOARD
-M: Simon Glass <sjg@chromium.org>
-S: Maintained
-F: board/sandbox/
-F: include/configs/sandbox.h
-F: configs/sandbox_noblk_defconfig
-
SANDBOX SPL BOARD
M: Simon Glass <sjg@chromium.org>
S: Maintained
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 7eaa6cd..499c872 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -791,6 +791,7 @@
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
+ struct udevice *dev;
#if !defined(CONFIG_SPL_BUILD)
uint8_t mac_addr[6];
uint32_t mac_hi, mac_lo;
@@ -871,6 +872,9 @@
env_set("serial#", board_serial);
}
+ /* Just probe the potentially supported cdce913 device */
+ uclass_get_device(UCLASS_CLK, 0, &dev);
+
return 0;
}
#endif
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 2e09cc2..f5ecf87 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -720,6 +720,7 @@
int board_late_init(void)
{
+ struct udevice *dev;
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
set_board_info_env(NULL);
@@ -737,6 +738,10 @@
if (device_okay("/ocp/omap_dwc3@483c0000"))
enable_usb_clocks(1);
#endif
+
+ /* Just probe the potentially supported cdce913 device */
+ uclass_get_device(UCLASS_CLK, 0, &dev);
+
return 0;
}
#endif
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index f78e6c2..237a834 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -30,6 +30,7 @@
#include <dwc3-omap-uboot.h>
#include <ti-usb-phy-uboot.h>
#include <mmc.h>
+#include <dm/uclass.h>
#include "../common/board_detect.h"
#include "mux_data.h"
@@ -689,6 +690,7 @@
{
setup_board_eeprom_env();
u8 val;
+ struct udevice *dev;
/*
* DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
@@ -720,6 +722,9 @@
am57x_idk_lcd_detect();
+ /* Just probe the potentially supported cdce913 device */
+ uclass_get_device(UCLASS_CLK, 0, &dev);
+
#if !defined(CONFIG_SPL_BUILD)
board_ti_set_ethaddr(2);
#endif
diff --git a/board/ti/am65x/README b/board/ti/am65x/README
index 16384e0..2e3fd9c 100644
--- a/board/ti/am65x/README
+++ b/board/ti/am65x/README
@@ -261,3 +261,35 @@
=> setenv mmcdev 0
=> setenv bootpart 0
=> boot
+
+UART:
+-----
+ROM supports booting from MCU_UART0 via X-Modem protocol. The entire UART-based
+boot process up to U-Boot (proper) prompt goes through different stages and uses
+different UART peripherals as follows:
+
+ WHO | Loading WHAT | HW Module | Protocol
+----------+---------------+-------------+------------
+Boot ROM | tiboot3.bin | MCU_UART0 | X-Modem(*)
+R5 SPL | sysfw.itb | MCU_UART0 | Y-Modem(*)
+R5 SPL | tispl.bin | MAIN_UART0 | Y-Modem
+A53 SPL | u-boot.img | MAIN_UART0 | Y-Modem
+
+(*) Note that in addition to X/Y-Modem related protocol timeouts the DMSC
+ watchdog timeout of 3min (typ.) needs to be observed until System Firmware
+ is fully loaded (from sysfw.itb) and started.
+
+Example bash script sequence for running on a Linux host PC feeding all boot
+artifacts needed to the device:
+
+MCU_DEV=/dev/ttyUSB1
+MAIN_DEV=/dev/ttyUSB0
+
+stty -F $MCU_DEV 115200 cs8 -cstopb -parenb
+stty -F $MAIN_DEV 115200 cs8 -cstopb -parenb
+
+sb --xmodem tiboot3.bin > $MCU_DEV < $MCU_DEV
+sb --ymodem sysfw.itb > $MCU_DEV < $MCU_DEV
+sb --ymodem tispl.bin > $MAIN_DEV < $MAIN_DEV
+sleep 1
+sb --xmodem u-boot.img > $MAIN_DEV < $MAIN_DEV
diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c
index ad333ad..544f872 100644
--- a/board/ti/am65x/evm.c
+++ b/board/ti/am65x/evm.c
@@ -127,6 +127,19 @@
return ret;
}
+int checkboard(void)
+{
+ struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
+
+ if (do_board_detect())
+ /* EEPROM not populated */
+ printf("Board: %s rev %s\n", "AM6-COMPROCEVM", "E3");
+ else
+ printf("Board: %s rev %s\n", ep->name, ep->version);
+
+ return 0;
+}
+
static void setup_board_eeprom_env(void)
{
char *name = "am65x";
@@ -272,7 +285,7 @@
if (strncmp(ep.name, cards[i].card_name, sizeof(ep.name)))
continue;
- printf("detected %s\n", cards[i].card_name);
+ printf("Detected: %s rev %s\n", ep.name, ep.version);
/*
* Populate any MAC addresses from daughtercard into the U-Boot
diff --git a/board/ti/j721e/README b/board/ti/j721e/README
new file mode 100644
index 0000000..5be7d09
--- /dev/null
+++ b/board/ti/j721e/README
@@ -0,0 +1,227 @@
+Introduction:
+-------------
+The J721e family of SoCs are part of K3 Multicore SoC architecture platform
+targeting automotive applications. They are designed as a low power, high
+performance and highly integrated device architecture, adding significant
+enhancement on processing power, graphics capability, video and imaging
+processing, virtualization and coherent memory support.
+
+The device is partitioned into three functional domains, each containing
+specific processing cores and peripherals:
+1. Wake-up (WKUP) domain:
+ - Device Management and Security Controller (DMSC)
+2. Microcontroller (MCU) domain:
+ - Dual Core ARM Cortex-R5F processor
+3. MAIN domain:
+ - Dual core 64-bit ARM Cortex-A72
+ - 2 x Dual cortex ARM Cortex-R5 subsystem
+ - 2 x C66x Digital signal processor sub system
+ - C71x Digital signal processor sub-system with MMA.
+
+More info can be found in TRM: http://www.ti.com/lit/pdf/spruil1
+
+Boot Flow:
+----------
+Boot flow is similar to that of AM65x SoC and extending it with remoteproc
+support. Below is the pictorial representation of boot flow:
+
++------------------------------------------------------------------------+-----------------------+
+| DMSC | MCU R5 | A72 | MAIN R5/C66x/C7x |
++------------------------------------------------------------------------+-----------------------+
+| +--------+ | | | |
+| | Reset | | | | |
+| +--------+ | | | |
+| : | | | |
+| +--------+ | +-----------+ | | |
+| | *ROM* |----------|-->| Reset rls | | | |
+| +--------+ | +-----------+ | | |
+| | | | : | | |
+| | ROM | | : | | |
+| |services| | : | | |
+| | | | +-------------+ | | |
+| | | | | *R5 ROM* | | | |
+| | | | +-------------+ | | |
+| | |<---------|---|Load and auth| | | |
+| | | | | tiboot3.bin | | | |
+| | | | +-------------+ | | |
+| | | | : | | |
+| | | | : | | |
+| | | | : | | |
+| | | | +-------------+ | | |
+| | | | | *R5 SPL* | | | |
+| | | | +-------------+ | | |
+| | | | | Load | | | |
+| | | | | sysfw.itb | | | |
+| | Start | | +-------------+ | | |
+| | System |<---------|---| Start | | | |
+| |Firmware| | | SYSFW | | | |
+| +--------+ | +-------------+ | | |
+| : | | | | | |
+| +---------+ | | Load | | | |
+| | *SYSFW* | | | system | | | |
+| +---------+ | | Config data | | | |
+| | |<--------|---| | | | |
+| | | | +-------------+ | | |
+| | | | | DDR | | | |
+| | | | | config | | | |
+| | | | +-------------+ | | |
+| | | | | Load | | | |
+| | | | | tispl.bin | | | |
+| | | | +-------------+ | | |
+| | | | | Load R5 | | | |
+| | | | | firmware | | | |
+| | | | +-------------+ | | |
+| | |<--------|---| Start A72 | | | |
+| | | | | and jump to | | | |
+| | | | | next image | | | |
+| | | | +-------------+ | | |
+| | | | | +-----------+ | |
+| | |---------|-----------------------|---->| Reset rls | | |
+| | | | | +-----------+ | |
+| | DMSC | | | : | |
+| |Services | | | +-----------+ | |
+| | |<--------|-----------------------|---->|*ATF/OPTEE*| | |
+| | | | | +-----------+ | |
+| | | | | : | |
+| | | | | +-----------+ | |
+| | |<--------|-----------------------|---->| *A72 SPL* | | |
+| | | | | +-----------+ | |
+| | | | | | Load | | |
+| | | | | | u-boot.img| | |
+| | | | | +-----------+ | |
+| | | | | : | |
+| | | | | +-----------+ | |
+| | |<--------|-----------------------|---->| *U-Boot* | | |
+| | | | | +-----------+ | |
+| | | | | | prompt | | |
+| | | | | +-----------+ | |
+| | | | | | Load R5 | | |
+| | | | | | Firmware | | |
+| | | | | +-----------+ | |
+| | |<--------|-----------------------|-----| Start R5 | | +-----------+ |
+| | |---------|-----------------------|-----+-----------+-----|----->| R5 starts | |
+| | | | | | Load C6 | | +-----------+ |
+| | | | | | Firmware | | |
+| | | | | +-----------+ | |
+| | |<--------|-----------------------|-----| Start C6 | | +-----------+ |
+| | |---------|-----------------------|-----+-----------+-----|----->| C6 starts | |
+| | | | | | Load C7 | | +-----------+ |
+| | | | | | Firmware | | |
+| | | | | +-----------+ | |
+| | |<--------|-----------------------|-----| Start C7 | | +-----------+ |
+| | |---------|-----------------------|-----+-----------+-----|----->| C7 starts | |
+| +---------+ | | | +-----------+ |
+| | | | |
++------------------------------------------------------------------------+-----------------------+
+
+- Here DMSC acts as master and provides all the critical services. R5/A72
+requests DMSC to get these services done as shown in the above diagram.
+
+Sources:
+--------
+1. SYSFW:
+ Tree: git://git.ti.com/processor-firmware/system-firmware-image-gen.git
+ Branch: master
+
+2. ATF:
+ Tree: https://github.com/ARM-software/arm-trusted-firmware.git
+ Branch: master
+
+3. OPTEE:
+ Tree: https://github.com/OP-TEE/optee_os.git
+ Branch: master
+
+4. U-Boot:
+ Tree: https://gitlab.denx.de/u-boot/u-boot
+ Branch: master
+
+Build procedure:
+----------------
+1. SYSFW:
+$ make CROSS_COMPILE=arm-linux-gnueabihf-
+
+2. ATF:
+$ make CROSS_COMPILE=aarch64-linux-gnu- ARCH=aarch64 PLAT=k3 TARGET_BOARD=generic SPD=opteed
+
+3. OPTEE:
+$ make PLATFORM=k3-j721e CFG_ARM64_core=y
+
+4. U-Boot:
+
+4.1. R5:
+$ make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- j721e_evm_r5_defconfig O=/tmp/r5
+$ make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- O=/tmp/r5
+
+4.2. A72:
+$ make ARCH=arm CROSS_COMPILE=aarch64-linux-gnu- j721e_evm_a72_defconfig O=/tmp/a72
+$ make ARCH=arm CROSS_COMPILE=aarch64-linux-gnu- ATF=<path to ATF dir>/build/k3/generic/release/bl31.bin TEE=<path to OPTEE OS dir>/out/arm-plat-k3/core/tee-pager.bin O=/tmp/a72
+
+Target Images
+--------------
+Copy the below images to an SD card and boot:
+- sysfw.itb from step 1
+- tiboot3.bin from step 4.1
+- tispl.bin, u-boot.img from 4.2
+
+Image formats:
+--------------
+
+- tiboot3.bin:
+ +-----------------------+
+ | X.509 |
+ | Certificate |
+ | +-------------------+ |
+ | | | |
+ | | R5 | |
+ | | u-boot-spl.bin | |
+ | | | |
+ | +-------------------+ |
+ | | | |
+ | | FIT header | |
+ | | +---------------+ | |
+ | | | | | |
+ | | | DTB 1...N | | |
+ | | +---------------+ | |
+ | +-------------------+ |
+ +-----------------------+
+
+- tispl.bin
+ +-----------------------+
+ | |
+ | FIT HEADER |
+ | +-------------------+ |
+ | | | |
+ | | A72 ATF | |
+ | +-------------------+ |
+ | | | |
+ | | A72 OPTEE | |
+ | +-------------------+ |
+ | | | |
+ | | A72 SPL | |
+ | +-------------------+ |
+ | | | |
+ | | SPL DTB 1...N | |
+ | +-------------------+ |
+ +-----------------------+
+
+- sysfw.itb
+ +-----------------------+
+ | |
+ | FIT HEADER |
+ | +-------------------+ |
+ | | | |
+ | | sysfw.bin | |
+ | +-------------------+ |
+ | | | |
+ | | board config | |
+ | +-------------------+ |
+ | | | |
+ | | PM config | |
+ | +-------------------+ |
+ | | | |
+ | | RM config | |
+ | +-------------------+ |
+ | | | |
+ | | Secure config | |
+ | +-------------------+ |
+ +-----------------------+
diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig
index 37bec5f..cb272ea 100644
--- a/board/xilinx/Kconfig
+++ b/board/xilinx/Kconfig
@@ -39,3 +39,11 @@
before the build.
endif
+
+config XILINX_OF_BOARD_DTB_ADDR
+ hex
+ default 0x1000 if ARCH_VERSAL
+ default 0x100000 if ARCH_ZYNQ || ARCH_ZYNQMP
+ depends on OF_BOARD
+ help
+ Offset in the memory where the board configuration DTB is placed.
diff --git a/board/xilinx/bootscripts/qspiboot.cmd b/board/xilinx/bootscripts/qspiboot.cmd
new file mode 100644
index 0000000..c10341c
--- /dev/null
+++ b/board/xilinx/bootscripts/qspiboot.cmd
@@ -0,0 +1,10 @@
+# This is an example file to generate boot.scr - a boot script for U-Boot
+# This example only target for qspi boot, sameway it can be created for boot
+# devices like nand.
+# Generate boot.scr:
+# ./tools/mkimage -c none -A arm -T script -d qspiboot.cmd boot.scr
+#
+# It requires a list of environment variables to be defined before load:
+# fdt_addr, fdt_offset, fdt_size, kernel_addr, kernel_offset, kernel_size
+#
+sf probe 0 0 0 && sf read $fdt_addr $fdt_offset $fdt_size && sf read $kernel_addr $kernel_offset $kernel_size && booti $kernel_addr - $fdt_addr
diff --git a/board/xilinx/bootscripts/sdboot.cmd b/board/xilinx/bootscripts/sdboot.cmd
new file mode 100644
index 0000000..0031900
--- /dev/null
+++ b/board/xilinx/bootscripts/sdboot.cmd
@@ -0,0 +1,10 @@
+# This is an example file to generate boot.scr - a boot script for U-Boot
+# This example only target for qspi boot, sameway it can be created for boot
+# devices like nand.
+# Generate boot.scr:
+# ./tools/mkimage -c none -A arm -T script -d sdboot.cmd boot.scr
+#
+# It requires a list of environment variables used below to be defined
+# before load
+#
+mmc dev $devnum && mmcinfo && run uenvboot || run sdroot$devnum;load mmc $devnum:$partid $fdt_addr system.dtb && load mmc $devnum:$partid $kernel_addr Image && booti $kernel_addr - $fdt_addr
diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
index 7e6340b..1c28263 100644
--- a/board/xilinx/common/board.c
+++ b/board/xilinx/common/board.c
@@ -36,3 +36,17 @@
return ret;
}
+
+#if defined(CONFIG_OF_BOARD)
+void *board_fdt_blob_setup(void)
+{
+ static void *fw_dtb = (void *)CONFIG_XILINX_OF_BOARD_DTB_ADDR;
+
+ if (fdt_magic(fw_dtb) != FDT_MAGIC) {
+ printf("DTB is not passed via %p\n", fw_dtb);
+ return NULL;
+ }
+
+ return fw_dtb;
+}
+#endif
diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c
index ba82292..7e784d1 100644
--- a/board/xilinx/microblaze-generic/microblaze-generic.c
+++ b/board/xilinx/microblaze-generic/microblaze-generic.c
@@ -12,20 +12,12 @@
#include <common.h>
#include <config.h>
-#include <dm.h>
#include <dm/lists.h>
#include <fdtdec.h>
-#include <asm/processor.h>
-#include <asm/microblaze_intc.h>
-#include <asm/asm.h>
-#include <asm/gpio.h>
-#include <dm/uclass.h>
-#include <wdt.h>
+#include <linux/sizes.h>
DECLARE_GLOBAL_DATA_PTR;
-ulong ram_base;
-
int dram_init_banksize(void)
{
return fdtdec_setup_memory_banksize();
@@ -41,6 +33,8 @@
int board_late_init(void)
{
+ ulong max_size, lowmem_size;
+
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SYSRESET_MICROBLAZE)
int ret;
@@ -49,5 +43,21 @@
if (ret)
printf("Warning: No reset driver: ret=%d\n", ret);
#endif
+
+ if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
+ debug("Saved variables - Skipping\n");
+ return 0;
+ }
+
+ max_size = gd->start_addr_sp - CONFIG_STACK_SIZE;
+ max_size = round_down(max_size, SZ_16M);
+
+ /* Linux default LOWMEM_SIZE is 0x30000000 = 768MB */
+ lowmem_size = gd->ram_base + 768 * 1024 * 1024;
+
+ env_set_addr("initrd_high", (void *)min_t(ulong, max_size,
+ lowmem_size));
+ env_set_addr("fdt_high", (void *)min_t(ulong, max_size, lowmem_size));
+
return 0;
}
diff --git a/board/xilinx/versal/Makefile b/board/xilinx/versal/Makefile
index 2b81276..e9307d7 100644
--- a/board/xilinx/versal/Makefile
+++ b/board/xilinx/versal/Makefile
@@ -5,3 +5,4 @@
#
obj-y := board.o
+obj-y += ../common/board.o
diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c
index 9075147..abdd580 100644
--- a/board/xilinx/versal/board.c
+++ b/board/xilinx/versal/board.c
@@ -9,13 +9,27 @@
#include <malloc.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include <versalpl.h>
+#include <linux/sizes.h>
DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_FPGA_VERSALPL)
+static xilinx_desc versalpl = XILINX_VERSAL_DESC;
+#endif
+
int board_init(void)
{
printf("EL Level:\tEL%d\n", current_el());
+#if defined(CONFIG_FPGA_VERSALPL)
+ fpga_init();
+ fpga_add(fpga_xilinx, &versalpl);
+#endif
+
return 0;
}
@@ -65,9 +79,133 @@
return 0;
}
+int board_late_init(void)
+{
+ u32 reg = 0;
+ u8 bootmode;
+ struct udevice *dev;
+ int bootseq = -1;
+ int bootseq_len = 0;
+ int env_targets_len = 0;
+ const char *mode;
+ char *new_targets;
+ char *env_targets;
+ ulong initrd_hi;
+
+ if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
+ debug("Saved variables - Skipping\n");
+ return 0;
+ }
+
+ reg = readl(&crp_base->boot_mode_usr);
+
+ if (reg >> BOOT_MODE_ALT_SHIFT)
+ reg >>= BOOT_MODE_ALT_SHIFT;
+
+ bootmode = reg & BOOT_MODES_MASK;
+
+ puts("Bootmode: ");
+ switch (bootmode) {
+ case USB_MODE:
+ puts("USB_MODE\n");
+ mode = "dfu_usb";
+ break;
+ case JTAG_MODE:
+ puts("JTAG_MODE\n");
+ mode = "jtag pxe dhcp";
+ break;
+ case QSPI_MODE_24BIT:
+ puts("QSPI_MODE_24\n");
+ mode = "xspi0";
+ break;
+ case QSPI_MODE_32BIT:
+ puts("QSPI_MODE_32\n");
+ mode = "xspi0";
+ break;
+ case OSPI_MODE:
+ puts("OSPI_MODE\n");
+ mode = "xspi0";
+ break;
+ case EMMC_MODE:
+ puts("EMMC_MODE\n");
+ mode = "mmc0";
+ break;
+ case SD_MODE:
+ puts("SD_MODE\n");
+ if (uclass_get_device_by_name(UCLASS_MMC,
+ "sdhci@f1040000", &dev)) {
+ puts("Boot from SD0 but without SD0 enabled!\n");
+ return -1;
+ }
+ debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
+
+ mode = "mmc";
+ bootseq = dev->seq;
+ break;
+ case SD1_LSHFT_MODE:
+ puts("LVL_SHFT_");
+ /* fall through */
+ case SD_MODE1:
+ puts("SD_MODE1\n");
+ if (uclass_get_device_by_name(UCLASS_MMC,
+ "sdhci@f1050000", &dev)) {
+ puts("Boot from SD1 but without SD1 enabled!\n");
+ return -1;
+ }
+ debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
+
+ mode = "mmc";
+ bootseq = dev->seq;
+ break;
+ default:
+ mode = "";
+ printf("Invalid Boot Mode:0x%x\n", bootmode);
+ break;
+ }
+
+ if (bootseq >= 0) {
+ bootseq_len = snprintf(NULL, 0, "%i", bootseq);
+ debug("Bootseq len: %x\n", bootseq_len);
+ }
+
+ /*
+ * One terminating char + one byte for space between mode
+ * and default boot_targets
+ */
+ env_targets = env_get("boot_targets");
+ if (env_targets)
+ env_targets_len = strlen(env_targets);
+
+ new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
+ bootseq_len);
+ if (!new_targets)
+ return -ENOMEM;
+
+ if (bootseq >= 0)
+ sprintf(new_targets, "%s%x %s", mode, bootseq,
+ env_targets ? env_targets : "");
+ else
+ sprintf(new_targets, "%s %s", mode,
+ env_targets ? env_targets : "");
+
+ env_set("boot_targets", new_targets);
+
+ initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
+ initrd_hi = round_down(initrd_hi, SZ_16M);
+ env_set_addr("initrd_high", (void *)initrd_hi);
+
+ return 0;
+}
+
int dram_init_banksize(void)
{
- fdtdec_setup_memory_banksize();
+ int ret;
+
+ ret = fdtdec_setup_memory_banksize();
+ if (ret)
+ return ret;
+
+ mem_map_fill();
return 0;
}
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 35191b2..7cfe69d 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -52,7 +52,7 @@
env_set("modeboot", "norboot");
break;
case ZYNQ_BM_SD:
- mode = "mmc";
+ mode = "mmc0";
env_set("modeboot", "sdboot");
break;
case ZYNQ_BM_JTAG:
diff --git a/board/xilinx/zynqmp/cmds.c b/board/xilinx/zynqmp/cmds.c
index ed7ba58..f53a1b6 100644
--- a/board/xilinx/zynqmp/cmds.c
+++ b/board/xilinx/zynqmp/cmds.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <env.h>
#include <malloc.h>
+#include <zynqmp_firmware.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
diff --git a/board/xilinx/zynqmp/zynqmp-a2197-g-revA b/board/xilinx/zynqmp/zynqmp-a2197-g-revA
new file mode 120000
index 0000000..a64c140
--- /dev/null
+++ b/board/xilinx/zynqmp/zynqmp-a2197-g-revA
@@ -0,0 +1 @@
+zynqmp-a2197-revA
\ No newline at end of file
diff --git a/board/xilinx/zynqmp/zynqmp-a2197-m-revA b/board/xilinx/zynqmp/zynqmp-a2197-m-revA
new file mode 120000
index 0000000..a64c140
--- /dev/null
+++ b/board/xilinx/zynqmp/zynqmp-a2197-m-revA
@@ -0,0 +1 @@
+zynqmp-a2197-revA
\ No newline at end of file
diff --git a/board/xilinx/zynqmp/zynqmp-a2197-p-revA b/board/xilinx/zynqmp/zynqmp-a2197-p-revA
new file mode 120000
index 0000000..a64c140
--- /dev/null
+++ b/board/xilinx/zynqmp/zynqmp-a2197-p-revA
@@ -0,0 +1 @@
+zynqmp-a2197-revA
\ No newline at end of file
diff --git a/board/xilinx/zynqmp/zynqmp-a2197-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-a2197-revA/psu_init_gpl.c
new file mode 100644
index 0000000..ac4a073
--- /dev/null
+++ b/board/xilinx/zynqmp/zynqmp-a2197-revA/psu_init_gpl.c
@@ -0,0 +1,1171 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+ psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014000U);
+ psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+ mask_poll(0xFF5E0040, 0x00000002U);
+ psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000200U);
+ psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
+ psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
+ psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
+ psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+ mask_poll(0xFF5E0040, 0x00000001U);
+ psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
+ psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000001U);
+ psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+ psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
+ psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000002U);
+ psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U);
+ psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
+ psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014000U);
+ psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+ mask_poll(0xFD1A0044, 0x00000004U);
+ psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+ psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000200U);
+ psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+ psu_mask_write(0xFF5E0050, 0x063F3F07U, 0x06010C00U);
+ psu_mask_write(0xFF180360, 0x00000003U, 0x00000001U);
+ psu_mask_write(0xFF180308, 0x00000006U, 0x00000006U);
+ psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+ psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+ psu_mask_write(0xFF5E0064, 0x023F3F07U, 0x02010600U);
+ psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U);
+ psu_mask_write(0xFF5E006C, 0x013F3F07U, 0x01010800U);
+ psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
+ psu_mask_write(0xFF18030C, 0x00020003U, 0x00000000U);
+ psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+ psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+ psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000400U);
+ psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+ psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+ psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+ psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010B02U);
+ psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U);
+ psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+ psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000104U);
+ psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+ psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+ psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
+ psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+ psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000203U);
+ psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000203U);
+ psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000202U);
+ psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+ psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+ psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+ psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFD070000, 0xE30FBE3DU, 0xC1081020U);
+ psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+ psu_mask_write(0xFD070020, 0x000003F3U, 0x00000202U);
+ psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00516120U);
+ psu_mask_write(0xFD070030, 0x0000007FU, 0x00000008U);
+ psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
+ psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+ psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+ psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+ psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x00418096U);
+ psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+ psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+ psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0030051FU);
+ psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00030413U);
+ psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x006A0000U);
+ psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
+ psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x00440024U);
+ psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00310008U);
+ psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+ psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x00000000U);
+ psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+ psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000077FU);
+ psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x15161117U);
+ psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040422U);
+ psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x060C1310U);
+ psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00F08000U);
+ psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x0A04060CU);
+ psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x01040808U);
+ psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010005U);
+ psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000401U);
+ psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040606U);
+ psu_mask_write(0xFD070124, 0x40070F3FU, 0x0004040DU);
+ psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x440C011CU);
+ psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+ psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x82160010U);
+ psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x01B65B96U);
+ psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x0495820AU);
+ psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+ psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+ psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+ psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x83FF0003U);
+ psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
+ psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000004U);
+ psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00001308U);
+ psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+ psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+ psu_mask_write(0xFD070204, 0x001F1F1FU, 0x00070707U);
+ psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
+ psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x0F000000U);
+ psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+ psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x060F0606U);
+ psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x06060606U);
+ psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+ psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000000U);
+ psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x06060606U);
+ psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x06060606U);
+ psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000006U);
+ psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x04000400U);
+ psu_mask_write(0xFD070244, 0x00003333U, 0x00000000U);
+ psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+ psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+ psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+ psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+ psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+ psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+ psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+ psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+ psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+ psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+ psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+ psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+ psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+ psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+ psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+ psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+ psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+ psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+ psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+ psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+ psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x87001E00U);
+ psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F07E38U);
+ psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+ psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+ psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x42C21590U);
+ psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xD05512C0U);
+ psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
+ psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000DDU);
+ psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0000040DU);
+ psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x0B2E1708U);
+ psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x282B0510U);
+ psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0133U);
+ psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82000501U);
+ psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x012B2B0BU);
+ psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x0044260BU);
+ psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000C18U);
+ psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+ psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+ psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000044U);
+ psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000024U);
+ psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000031U);
+ psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000008U);
+ psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000056U);
+ psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x00000021U);
+ psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+ psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x00000019U);
+ psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000016U);
+ psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+ psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+ psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+ psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+ psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U);
+ psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x0000000AU);
+ psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+ psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000005U);
+ psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300BD99U);
+ psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF1032019U);
+ psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+ psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+ psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAC58U);
+ psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x0001B39BU);
+ psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+ psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+ psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x0001BB9BU);
+ psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00F50CU);
+ psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09091616U);
+ psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00F50CU);
+ psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09091616U);
+ psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00F50CU);
+ psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09091616U);
+ psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+ psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+ psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
+ psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00F50CU);
+ psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09091616U);
+ psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x80803660U);
+ psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x55556000U);
+ psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+ psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x0129A4A4U);
+ psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0C00BD00U);
+ psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09091616U);
+ psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x80803660U);
+ psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x55556000U);
+ psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+ psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x0029A4A4U);
+ psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0C00BD00U);
+ psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09091616U);
+ psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x80803660U);
+ psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x55556000U);
+ psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+ psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x0029A4A4U);
+ psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0C00BD00U);
+ psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09091616U);
+ psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x80803660U);
+ psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x55556000U);
+ psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+ psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x0029A4A4U);
+ psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0C00BD00U);
+ psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09091616U);
+ psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
+ psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
+ psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+ psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
+ psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00BD00U);
+ psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09091616U);
+ psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+ psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x000C1800U);
+ psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x71000000U);
+ psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+ psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+ psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x000C1800U);
+ psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x71000000U);
+ psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x15019FFEU);
+ psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x21100000U);
+ psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01266300U);
+ psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x000C1800U);
+ psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70400000U);
+ psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x15019FFEU);
+ psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x21100000U);
+ psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01266300U);
+ psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x000C1800U);
+ psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70400000U);
+ psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
+ psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U);
+ psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
+ psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x000C1800U);
+ psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
+ psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x01100000U);
+ psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+ return 1;
+}
+
+static unsigned long psu_ddr_qos_init_data(void)
+{
+ return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+ psu_mask_write(0xFF180034, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180038, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180040, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180044, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180048, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180050, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180054, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180058, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000008U);
+ psu_mask_write(0xFF180088, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF180090, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF180094, 0x000000FEU, 0x00000040U);
+ psu_mask_write(0xFF180098, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF18009C, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF1800A0, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF1800A4, 0x000000FEU, 0x000000C0U);
+ psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+ psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180100, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180104, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180108, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180110, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180114, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180118, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180120, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180124, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180128, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000004U);
+ psu_mask_write(0xFF180130, 0x000000FEU, 0x00000060U);
+ psu_mask_write(0xFF180134, 0x000000FEU, 0x00000060U);
+ psu_mask_write(0xFF180204, 0x00FFE000U, 0x00000000U);
+ psu_mask_write(0xFF180208, 0xFFFFE3FCU, 0x00B02240U);
+ psu_mask_write(0xFF18020C, 0x00003FFFU, 0x0000000BU);
+ psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
+ psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
+ psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_peripherals_pre_init_data(void)
+{
+ psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
+
+ return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+ psu_mask_write(0xFD1A0100, 0x0000007CU, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+ psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00000C00U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000060U, 0x00000000U);
+ psu_mask_write(0xFF180310, 0x00008001U, 0x00000001U);
+ psu_mask_write(0xFF180320, 0x33843384U, 0x00801284U);
+ psu_mask_write(0xFF18031C, 0x00007FFEU, 0x00006450U);
+ psu_mask_write(0xFF180358, 0x00080000U, 0x00080000U);
+ psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+ psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+ psu_mask_write(0xFF180324, 0x000003C0U, 0x00000000U);
+ psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
+ psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+ psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
+ psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
+ psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
+ psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
+ psu_mask_write(0xFF010034, 0x000000FFU, 0x00000005U);
+ psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000008FU);
+ psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
+ psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
+ psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+ psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+ psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+ psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+ psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x01FC9F08U);
+ psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+ mask_delay(1);
+ psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U);
+
+ mask_delay(5);
+ psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
+
+ return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+ psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000FU);
+ psu_mask_write(0xFD410004, 0x0000001FU, 0x00000008U);
+ psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD402864, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD406094, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD406368, 0x000000FFU, 0x00000038U);
+ psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
+ psu_mask_write(0xFD406370, 0x000000FFU, 0x000000F4U);
+ psu_mask_write(0xFD406374, 0x000000FFU, 0x00000031U);
+ psu_mask_write(0xFD406378, 0x000000FFU, 0x00000002U);
+ psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
+ psu_mask_write(0xFD40106C, 0x0000000FU, 0x0000000FU);
+ psu_mask_write(0xFD4000F4, 0x0000000BU, 0x0000000BU);
+ psu_mask_write(0xFD40506C, 0x00000003U, 0x00000003U);
+ psu_mask_write(0xFD4040F4, 0x00000003U, 0x00000003U);
+ psu_mask_write(0xFD4050CC, 0x00000020U, 0x00000020U);
+ psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD4018F8, 0x000000FFU, 0x0000007DU);
+ psu_mask_write(0xFD4018FC, 0x000000FFU, 0x0000007DU);
+ psu_mask_write(0xFD401990, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD401924, 0x000000FFU, 0x00000082U);
+ psu_mask_write(0xFD401928, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U);
+ psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD401914, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD401940, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40589C, 0x00000080U, 0x00000080U);
+ psu_mask_write(0xFD4058F8, 0x000000FFU, 0x0000001AU);
+ psu_mask_write(0xFD4058FC, 0x000000FFU, 0x0000001AU);
+ psu_mask_write(0xFD405990, 0x000000FFU, 0x00000010U);
+ psu_mask_write(0xFD405924, 0x000000FFU, 0x000000FEU);
+ psu_mask_write(0xFD405928, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD405900, 0x000000FFU, 0x0000001AU);
+ psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000000U);
+ psu_mask_write(0xFD405980, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD405914, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD405918, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD405940, 0x000000FFU, 0x000000F7U);
+ psu_mask_write(0xFD405944, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+ psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+ psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+ psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+ psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+ psu_mask_write(0xFD410010, 0x00000077U, 0x00000035U);
+ psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U);
+ psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U);
+
+ return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+ psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+ psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00000800U, 0x00000000U);
+ psu_mask_write(0xFF9E0080, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF9E007C, 0x00000001U, 0x00000001U);
+ psu_mask_write(0xFF5E023C, 0x00000280U, 0x00000000U);
+ psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000000U);
+ psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
+ psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+ psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U);
+ psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
+ psu_mask_write(0xFE30C200, 0x00023FFFU, 0x00022457U);
+ psu_mask_write(0xFE30C630, 0x003FFF00U, 0x00000000U);
+ psu_mask_write(0xFE30C12C, 0x00004000U, 0x00004000U);
+ psu_mask_write(0xFE30C11C, 0x00000400U, 0x00000400U);
+ psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+ mask_poll(0xFD4023E4, 0x00000010U);
+ mask_poll(0xFD4063E4, 0x00000010U);
+
+ return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+ psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+ psu_mask_write(0xFF5E023C, 0x00000A80U, 0x00000A80U);
+ psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000001U);
+
+ return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+ psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+ psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+ psu_mask_write(0xFF419000, 0x00000300U, 0x00000000U);
+
+ return 1;
+}
+
+static void dpll_prog(int ddr_pll_fbdiv, int d_lock_dly, int d_lock_cnt,
+ int d_lfhf, int d_cp, int d_res)
+{
+ unsigned int pll_ctrl_regval;
+ unsigned int pll_status_regval;
+
+ pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
+ pll_ctrl_regval = pll_ctrl_regval & (~0x00010000U);
+ pll_ctrl_regval = pll_ctrl_regval | (1 << 16);
+ Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
+
+ pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
+ pll_ctrl_regval = pll_ctrl_regval & (~0xFE000000U);
+ pll_ctrl_regval = pll_ctrl_regval | (d_lock_dly << 25);
+ Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
+
+ pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
+ pll_ctrl_regval = pll_ctrl_regval & (~0x007FE000U);
+ pll_ctrl_regval = pll_ctrl_regval | (d_lock_cnt << 13);
+ Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
+
+ pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
+ pll_ctrl_regval = pll_ctrl_regval & (~0x00000C00U);
+ pll_ctrl_regval = pll_ctrl_regval | (d_lfhf << 10);
+ Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
+
+ pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
+ pll_ctrl_regval = pll_ctrl_regval & (~0x000001E0U);
+ pll_ctrl_regval = pll_ctrl_regval | (d_cp << 5);
+ Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
+
+ pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030));
+ pll_ctrl_regval = pll_ctrl_regval & (~0x0000000FU);
+ pll_ctrl_regval = pll_ctrl_regval | (d_res << 0);
+ Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval);
+
+ pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
+ pll_ctrl_regval = pll_ctrl_regval & (~0x00007F00U);
+ pll_ctrl_regval = pll_ctrl_regval | (ddr_pll_fbdiv << 8);
+ Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
+
+ pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
+ pll_ctrl_regval = pll_ctrl_regval & (~0x00000008U);
+ pll_ctrl_regval = pll_ctrl_regval | (1 << 3);
+ Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
+
+ pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
+ pll_ctrl_regval = pll_ctrl_regval & (~0x00000001U);
+ pll_ctrl_regval = pll_ctrl_regval | (1 << 0);
+ Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
+
+ pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
+ pll_ctrl_regval = pll_ctrl_regval & (~0x00000001U);
+ pll_ctrl_regval = pll_ctrl_regval | (0 << 0);
+ Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
+
+ pll_status_regval = 0x00000000;
+ while ((pll_status_regval & 0x00000002U) != 0x00000002U)
+ pll_status_regval = Xil_In32(((0xFD1A0000U) + 0x00000044));
+
+ pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C));
+ pll_ctrl_regval = pll_ctrl_regval & (~0x00000008U);
+ pll_ctrl_regval = pll_ctrl_regval | (0 << 3);
+ Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval);
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+ unsigned int regval = 0;
+
+ for (int tp = 0; tp < 20; tp++)
+ regval = Xil_In32(0xFD070018);
+ int cur_PLLCR0;
+
+ cur_PLLCR0 = (Xil_In32(0xFD080068U) & 0xFFFFFFFFU) >> 0x00000000U;
+ int cur_DX8SL0PLLCR0;
+
+ cur_DX8SL0PLLCR0 = (Xil_In32(0xFD081404U) & 0xFFFFFFFFU) >> 0x00000000U;
+ int cur_DX8SL1PLLCR0;
+
+ cur_DX8SL1PLLCR0 = (Xil_In32(0xFD081444U) & 0xFFFFFFFFU) >> 0x00000000U;
+ int cur_DX8SL2PLLCR0;
+
+ cur_DX8SL2PLLCR0 = (Xil_In32(0xFD081484U) & 0xFFFFFFFFU) >> 0x00000000U;
+ int cur_DX8SL3PLLCR0;
+
+ cur_DX8SL3PLLCR0 = (Xil_In32(0xFD0814C4U) & 0xFFFFFFFFU) >> 0x00000000U;
+ int cur_DX8SL4PLLCR0;
+
+ cur_DX8SL4PLLCR0 = (Xil_In32(0xFD081504U) & 0xFFFFFFFFU) >> 0x00000000U;
+ int cur_DX8SLBPLLCR0;
+
+ cur_DX8SLBPLLCR0 = (Xil_In32(0xFD0817C4U) & 0xFFFFFFFFU) >> 0x00000000U;
+ Xil_Out32(0xFD080068, 0x02120000);
+ Xil_Out32(0xFD081404, 0x02120000);
+ Xil_Out32(0xFD081444, 0x02120000);
+ Xil_Out32(0xFD081484, 0x02120000);
+ Xil_Out32(0xFD0814C4, 0x02120000);
+ Xil_Out32(0xFD081504, 0x02120000);
+ Xil_Out32(0xFD0817C4, 0x02120000);
+ int cur_fbdiv;
+
+ cur_fbdiv = (Xil_In32(0xFD1A002CU) & 0x00007F00U) >> 0x00000008U;
+ dpll_prog(48, 63, 625, 3, 3, 2);
+ for (int tp = 0; tp < 20; tp++)
+ regval = Xil_In32(0xFD070018);
+ unsigned int pll_retry = 10;
+ unsigned int pll_locked = 0;
+
+ while ((pll_retry > 0) && (!pll_locked)) {
+ Xil_Out32(0xFD080004, 0x00040010);
+ Xil_Out32(0xFD080004, 0x00040011);
+
+ while ((Xil_In32(0xFD080030) & 0x1) != 1)
+ ;
+ pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
+ >> 31;
+ pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
+ >> 16;
+ pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000)
+ >> 16;
+ pll_retry--;
+ }
+ Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
+ if (!pll_locked)
+ return (0);
+
+ Xil_Out32(0xFD080004U, 0x00040063U);
+
+ while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+ ;
+ prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+ while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+ ;
+ Xil_Out32(0xFD070010U, 0x80000018U);
+ Xil_Out32(0xFD0701B0U, 0x00000005U);
+ regval = Xil_In32(0xFD070018);
+ while ((regval & 0x1) != 0x0)
+ regval = Xil_In32(0xFD070018);
+
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ Xil_Out32(0xFD070014U, 0x00000331U);
+ Xil_Out32(0xFD070010U, 0x80000018U);
+ regval = Xil_In32(0xFD070018);
+ while ((regval & 0x1) != 0x0)
+ regval = Xil_In32(0xFD070018);
+
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ Xil_Out32(0xFD070014U, 0x00000B36U);
+ Xil_Out32(0xFD070010U, 0x80000018U);
+ regval = Xil_In32(0xFD070018);
+ while ((regval & 0x1) != 0x0)
+ regval = Xil_In32(0xFD070018);
+
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ Xil_Out32(0xFD070014U, 0x00000C21U);
+ Xil_Out32(0xFD070010U, 0x80000018U);
+ regval = Xil_In32(0xFD070018);
+ while ((regval & 0x1) != 0x0)
+ regval = Xil_In32(0xFD070018);
+
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ Xil_Out32(0xFD070014U, 0x00000E19U);
+ Xil_Out32(0xFD070010U, 0x80000018U);
+ regval = Xil_In32(0xFD070018);
+ while ((regval & 0x1) != 0x0)
+ regval = Xil_In32(0xFD070018);
+
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ regval = Xil_In32(0xFD070018);
+ Xil_Out32(0xFD070014U, 0x00001616U);
+ Xil_Out32(0xFD070010U, 0x80000018U);
+ Xil_Out32(0xFD070010U, 0x80000010U);
+ Xil_Out32(0xFD0701B0U, 0x00000005U);
+ Xil_Out32(0xFD070320U, 0x00000001U);
+ while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+ ;
+ prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000000U);
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+ prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000001U);
+ prog_reg(0xFD080004U, 0x20000000U, 0x0000001DU, 0x00000001U);
+ prog_reg(0xFD08016CU, 0x00000004U, 0x00000002U, 0x00000001U);
+ prog_reg(0xFD080168U, 0x000000F0U, 0x00000004U, 0x00000007U);
+ prog_reg(0xFD080168U, 0x00000F00U, 0x00000008U, 0x00000002U);
+ prog_reg(0xFD080168U, 0x0000000FU, 0x00000000U, 0x00000001U);
+ for (int tp = 0; tp < 20; tp++)
+ regval = Xil_In32(0xFD070018);
+
+ Xil_Out32(0xFD080068, cur_PLLCR0);
+ Xil_Out32(0xFD081404, cur_DX8SL0PLLCR0);
+ Xil_Out32(0xFD081444, cur_DX8SL1PLLCR0);
+ Xil_Out32(0xFD081484, cur_DX8SL2PLLCR0);
+ Xil_Out32(0xFD0814C4, cur_DX8SL3PLLCR0);
+ Xil_Out32(0xFD081504, cur_DX8SL4PLLCR0);
+ Xil_Out32(0xFD0817C4, cur_DX8SLBPLLCR0);
+ for (int tp = 0; tp < 20; tp++)
+ regval = Xil_In32(0xFD070018);
+
+ dpll_prog(cur_fbdiv, 63, 625, 3, 3, 2);
+ for (int tp = 0; tp < 2000; tp++)
+ regval = Xil_In32(0xFD070018);
+
+ prog_reg(0xFD080004U, 0x20000000U, 0x0000001DU, 0x00000000U);
+ prog_reg(0xFD080004U, 0x00040000U, 0x00000012U, 0x00000001U);
+ prog_reg(0xFD080004U, 0x00000040U, 0x00000006U, 0x00000001U);
+ prog_reg(0xFD080004U, 0x00000020U, 0x00000005U, 0x00000001U);
+ prog_reg(0xFD080004U, 0x00000010U, 0x00000004U, 0x00000001U);
+ prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+ while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+ ;
+ prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+ while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+ ;
+ for (int tp = 0; tp < 2000; tp++)
+ regval = Xil_In32(0xFD070018);
+
+ prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000000U);
+ prog_reg(0xFD08016CU, 0x00000004U, 0x00000002U, 0x00000001U);
+ prog_reg(0xFD080168U, 0x000000F0U, 0x00000004U, 0x00000007U);
+ prog_reg(0xFD080168U, 0x00000F00U, 0x00000008U, 0x00000003U);
+ prog_reg(0xFD080168U, 0x0000000FU, 0x00000000U, 0x00000001U);
+ for (int tp = 0; tp < 2000; tp++)
+ regval = Xil_In32(0xFD070018);
+
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+ Xil_Out32(0xFD080004, 0x0014FE01);
+
+ regval = Xil_In32(0xFD080030);
+ while (regval != 0x8000007E)
+ regval = Xil_In32(0xFD080030);
+
+ Xil_Out32(0xFD080200U, 0x000091C7U);
+ regval = Xil_In32(0xFD080030);
+ while (regval != 0x80008FFF)
+ regval = Xil_In32(0xFD080030);
+
+ Xil_Out32(0xFD080200U, 0x800091C7U);
+ regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+ if (regval != 0)
+ return (0);
+
+ Xil_Out32(0xFD080200U, 0x800091C7U);
+ int cur_R006_tREFPRD;
+
+ cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U;
+ prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+ prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+ prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+ prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+ Xil_Out32(0xFD080004, 0x00060001);
+ regval = Xil_In32(0xFD080030);
+ while ((regval & 0x80004001) != 0x80004001)
+ regval = Xil_In32(0xFD080030);
+
+ prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+ prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+ Xil_Out32(0xFD080200U, 0x800091C7U);
+ prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+ Xil_Out32(0xFD080004, 0x0000C001);
+ regval = Xil_In32(0xFD080030);
+ while ((regval & 0x80000C01) != 0x80000C01)
+ regval = Xil_In32(0xFD080030);
+
+ prog_reg(0xFD070320U, 0x00000001U, 0x00000000U, 0x00000000U);
+ prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000001U);
+ prog_reg(0xFD0701A0U, 0x80000000U, 0x0000001FU, 0x00000000U);
+ prog_reg(0xFD070320U, 0x00000001U, 0x00000000U, 0x00000001U);
+ Xil_Out32(0xFD070180U, 0x02160010U);
+ Xil_Out32(0xFD070060U, 0x00000000U);
+ prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+ for (int tp = 0; tp < 4000; tp++)
+ regval = Xil_In32(0xFD070018);
+
+ prog_reg(0xFD080090U, 0x00000FC0U, 0x00000006U, 0x00000007U);
+ prog_reg(0xFD080090U, 0x00000004U, 0x00000002U, 0x00000001U);
+ prog_reg(0xFD08070CU, 0x02000000U, 0x00000019U, 0x00000000U);
+ prog_reg(0xFD08080CU, 0x02000000U, 0x00000019U, 0x00000000U);
+ prog_reg(0xFD08090CU, 0x02000000U, 0x00000019U, 0x00000000U);
+ prog_reg(0xFD080A0CU, 0x02000000U, 0x00000019U, 0x00000000U);
+ prog_reg(0xFD080F0CU, 0x02000000U, 0x00000019U, 0x00000000U);
+ prog_reg(0xFD080200U, 0x00000010U, 0x00000004U, 0x00000001U);
+ prog_reg(0xFD080250U, 0x00000002U, 0x00000001U, 0x00000000U);
+ prog_reg(0xFD080250U, 0x0000000CU, 0x00000002U, 0x00000001U);
+ prog_reg(0xFD080250U, 0x000000F0U, 0x00000004U, 0x00000000U);
+ prog_reg(0xFD080250U, 0x00300000U, 0x00000014U, 0x00000001U);
+ prog_reg(0xFD080250U, 0xF0000000U, 0x0000001CU, 0x00000002U);
+ prog_reg(0xFD08070CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+ prog_reg(0xFD08080CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+ prog_reg(0xFD08090CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+ prog_reg(0xFD080A0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+ prog_reg(0xFD080B0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+ prog_reg(0xFD080C0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+ prog_reg(0xFD080D0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+ prog_reg(0xFD080E0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+ prog_reg(0xFD080F0CU, 0x08000000U, 0x0000001BU, 0x00000000U);
+ prog_reg(0xFD080254U, 0x000000FFU, 0x00000000U, 0x00000001U);
+ prog_reg(0xFD080254U, 0x000F0000U, 0x00000010U, 0x0000000AU);
+ prog_reg(0xFD080250U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+ return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+ Xil_Out32(0xFD402094, 0x00000010);
+ Xil_Out32(0xFD406094, 0x00000010);
+ Xil_Out32(0xFD40A094, 0x00000010);
+ Xil_Out32(0xFD40E094, 0x00000010);
+ return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+ int maskstatus = 1;
+ unsigned int rdata = 0;
+ unsigned int match_pmos_code[23];
+ unsigned int match_nmos_code[23];
+ unsigned int match_ical_code[7];
+ unsigned int match_rcal_code[7];
+ unsigned int p_code = 0;
+ unsigned int n_code = 0;
+ unsigned int i_code = 0;
+ unsigned int r_code = 0;
+ unsigned int repeat_count = 0;
+ unsigned int L3_TM_CALIB_DIG20 = 0;
+ unsigned int L3_TM_CALIB_DIG19 = 0;
+ unsigned int L3_TM_CALIB_DIG18 = 0;
+ unsigned int L3_TM_CALIB_DIG16 = 0;
+ unsigned int L3_TM_CALIB_DIG15 = 0;
+ unsigned int L3_TM_CALIB_DIG14 = 0;
+ int i = 0, count = 0;
+
+ rdata = Xil_In32(0xFD40289C);
+ rdata = rdata & ~0x03;
+ rdata = rdata | 0x1;
+ Xil_Out32(0xFD40289C, rdata);
+
+ do {
+ if (count == 1100000)
+ break;
+ rdata = Xil_In32(0xFD402B1C);
+ count++;
+ } while ((rdata & 0x0000000E) != 0x0000000E);
+
+ for (i = 0; i < 23; i++) {
+ match_pmos_code[i] = 0;
+ match_nmos_code[i] = 0;
+ }
+ for (i = 0; i < 7; i++) {
+ match_ical_code[i] = 0;
+ match_rcal_code[i] = 0;
+ }
+
+ do {
+ Xil_Out32(0xFD410010, 0x00000000);
+ Xil_Out32(0xFD410014, 0x00000000);
+
+ Xil_Out32(0xFD410010, 0x00000001);
+ Xil_Out32(0xFD410014, 0x00000000);
+
+ maskstatus = mask_poll(0xFD40EF14, 0x2);
+ if (maskstatus == 0) {
+ xil_printf("#SERDES initialization timed out\n\r");
+ return maskstatus;
+ }
+
+ p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+ n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+ ;
+ i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+ r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+ ;
+
+ if (p_code >= 0x26 && p_code <= 0x3C)
+ match_pmos_code[p_code - 0x26] += 1;
+
+ if (n_code >= 0x26 && n_code <= 0x3C)
+ match_nmos_code[n_code - 0x26] += 1;
+
+ if (i_code >= 0xC && i_code <= 0x12)
+ match_ical_code[i_code - 0xC] += 1;
+
+ if (r_code >= 0x6 && r_code <= 0xC)
+ match_rcal_code[r_code - 0x6] += 1;
+
+ } while (repeat_count++ < 10);
+
+ for (i = 0; i < 23; i++) {
+ if (match_pmos_code[i] >= match_pmos_code[0]) {
+ match_pmos_code[0] = match_pmos_code[i];
+ p_code = 0x26 + i;
+ }
+ if (match_nmos_code[i] >= match_nmos_code[0]) {
+ match_nmos_code[0] = match_nmos_code[i];
+ n_code = 0x26 + i;
+ }
+ }
+
+ for (i = 0; i < 7; i++) {
+ if (match_ical_code[i] >= match_ical_code[0]) {
+ match_ical_code[0] = match_ical_code[i];
+ i_code = 0xC + i;
+ }
+ if (match_rcal_code[i] >= match_rcal_code[0]) {
+ match_rcal_code[0] = match_rcal_code[i];
+ r_code = 0x6 + i;
+ }
+ }
+
+ L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+ L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+ L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+ L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+ | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+ L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+ L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+ L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+ L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+ L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+ L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+ | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+ L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+ L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+ Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+ Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+ Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+ Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+ Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+ Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+ return maskstatus;
+}
+
+static int init_serdes(void)
+{
+ int status = 1;
+
+ status &= psu_resetin_init_data();
+
+ status &= serdes_fixcal_code();
+ status &= serdes_enb_coarse_saturation();
+
+ status &= psu_serdes_init_data();
+ status &= psu_resetout_init_data();
+
+ return status;
+}
+
+static void init_peripheral(void)
+{
+ psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+ int status = 1;
+
+ status &= psu_mio_init_data();
+ status &= psu_peripherals_pre_init_data();
+ status &= psu_pll_init_data();
+ status &= psu_clock_init_data();
+ status &= psu_ddr_init_data();
+ status &= psu_ddr_phybringup_data();
+ status &= psu_peripherals_init_data();
+ status &= init_serdes();
+ init_peripheral();
+
+ status &= psu_afi_config();
+ psu_ddr_qos_init_data();
+
+ if (status == 0)
+ return 1;
+ return 0;
+}
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index d649dab..b949364 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -21,7 +21,9 @@
#include <usb.h>
#include <dwc3-uboot.h>
#include <zynqmppl.h>
+#include <zynqmp_firmware.h>
#include <g_dnl.h>
+#include <linux/sizes.h>
#include "pm_cfg_obj.h"
@@ -173,6 +175,14 @@
.id = 0x66,
.name = "39dr",
},
+ {
+ .id = 0x7b,
+ .name = "48dr",
+ },
+ {
+ .id = 0x7e,
+ .name = "49dr",
+ },
};
#endif
@@ -308,18 +318,6 @@
int board_early_init_f(void)
{
int ret = 0;
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
- u32 pm_api_version;
-
- pm_api_version = zynqmp_pmufw_version();
- printf("PMUFW:\tv%d.%d\n",
- pm_api_version >> ZYNQMP_PM_VERSION_MAJOR_SHIFT,
- pm_api_version & ZYNQMP_PM_VERSION_MINOR_MASK);
-
- if (pm_api_version < ZYNQMP_PM_VERSION)
- panic("PMUFW version error. Expected: v%d.%d\n",
- ZYNQMP_PM_VERSION_MAJOR, ZYNQMP_PM_VERSION_MINOR);
-#endif
#if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
ret = psu_init();
@@ -330,6 +328,12 @@
int board_init(void)
{
+ struct udevice *dev;
+
+ uclass_get_device_by_name(UCLASS_FIRMWARE, "zynqmp-power", &dev);
+ if (!dev)
+ panic("PMU Firmware device not found - Enable it");
+
#if defined(CONFIG_SPL_BUILD)
/* Check *at build time* if the filename is an non-empty string */
if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
@@ -530,6 +534,7 @@
char *new_targets;
char *env_targets;
int ret;
+ ulong initrd_hi;
#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
usb_ether_init();
@@ -562,7 +567,7 @@
break;
case JTAG_MODE:
puts("JTAG_MODE\n");
- mode = "pxe dhcp";
+ mode = "jtag pxe dhcp";
env_set("modeboot", "jtagboot");
break;
case QSPI_MODE_24BIT:
@@ -647,6 +652,10 @@
env_set("boot_targets", new_targets);
+ initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
+ initrd_hi = round_down(initrd_hi, SZ_16M);
+ env_set_addr("initrd_high", (void *)initrd_hi);
+
reset_reason();
return 0;
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 8e55b34..07060c6 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -48,6 +48,8 @@
config SYS_PROMPT
string "Shell prompt"
+ default "Zynq> " if ARCH_ZYNQ
+ default "ZynqMP> " if ARCH_ZYNQMP
default "=> "
help
This string is displayed in the command line to the left of the
diff --git a/cmd/itest.c b/cmd/itest.c
index 8b630d7..e21e1f1 100644
--- a/cmd/itest.c
+++ b/cmd/itest.c
@@ -73,6 +73,11 @@
case 4:
l = (long)(*(u32 *)buf);
break;
+#ifdef CONFIG_PHYS_64BIT
+ case 8:
+ l = (long)(*(unsigned long *)buf);
+ break;
+#endif
}
unmap_physmem(buf, w);
return l;
@@ -186,6 +191,9 @@
case 1:
case 2:
case 4:
+#ifdef CONFIG_PHYS_64BIT
+ case 8:
+#endif
value = binary_test (argv[2], argv[1], argv[3], w);
break;
case -2:
@@ -204,5 +212,9 @@
U_BOOT_CMD(
itest, 4, 0, do_itest,
"return true/false on integer compare",
+#ifdef CONFIG_PHYS_64BIT
+ "[.b, .w, .l, .q, .s] [*]value1 <op> [*]value2"
+#else
"[.b, .w, .l, .s] [*]value1 <op> [*]value2"
+#endif
);
diff --git a/cmd/test.c b/cmd/test.c
index fa0c349..258bfd8 100644
--- a/cmd/test.c
+++ b/cmd/test.c
@@ -113,28 +113,28 @@
expr = strcmp(ap[0], ap[2]) > 0;
break;
case OP_INT_EQ:
- expr = simple_strtol(ap[0], NULL, 10) ==
- simple_strtol(ap[2], NULL, 10);
+ expr = simple_strtol(ap[0], NULL, 0) ==
+ simple_strtol(ap[2], NULL, 0);
break;
case OP_INT_NEQ:
- expr = simple_strtol(ap[0], NULL, 10) !=
- simple_strtol(ap[2], NULL, 10);
+ expr = simple_strtol(ap[0], NULL, 0) !=
+ simple_strtol(ap[2], NULL, 0);
break;
case OP_INT_LT:
- expr = simple_strtol(ap[0], NULL, 10) <
- simple_strtol(ap[2], NULL, 10);
+ expr = simple_strtol(ap[0], NULL, 0) <
+ simple_strtol(ap[2], NULL, 0);
break;
case OP_INT_LE:
- expr = simple_strtol(ap[0], NULL, 10) <=
- simple_strtol(ap[2], NULL, 10);
+ expr = simple_strtol(ap[0], NULL, 0) <=
+ simple_strtol(ap[2], NULL, 0);
break;
case OP_INT_GT:
- expr = simple_strtol(ap[0], NULL, 10) >
- simple_strtol(ap[2], NULL, 10);
+ expr = simple_strtol(ap[0], NULL, 0) >
+ simple_strtol(ap[2], NULL, 0);
break;
case OP_INT_GE:
- expr = simple_strtol(ap[0], NULL, 10) >=
- simple_strtol(ap[2], NULL, 10);
+ expr = simple_strtol(ap[0], NULL, 0) >=
+ simple_strtol(ap[2], NULL, 0);
break;
case OP_FILE_EXISTS:
expr = file_exists(ap[1], ap[2], ap[3], FS_TYPE_ANY);
diff --git a/cmd/ti/ddr3.c b/cmd/ti/ddr3.c
index b82cbe1..448a7f5 100644
--- a/cmd/ti/ddr3.c
+++ b/cmd/ti/ddr3.c
@@ -202,10 +202,6 @@
writel(val2, addr);
val3 = readl(addr);
- printf("\tECC test: addr 0x%x, read data 0x%x, written data 0x%x, err pattern: 0x%x, read after write data 0x%x\n",
- addr, val1, val2, ecc_err, val3);
-
- puts("\tECC test: Enabling DDR ECC ...\n");
#ifdef CONFIG_ARCH_KEYSTONE
ecc_ctrl = ECC_START_ADDR1 | (ECC_END_ADDR1 << 16);
writel(ecc_ctrl, EMIF1_BASE + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET);
@@ -214,6 +210,11 @@
writel(ecc_ctrl, &emif->emif_ecc_ctrl_reg);
#endif
+ printf("\tECC test: addr 0x%x, read data 0x%x, written data 0x%x, err pattern: 0x%x, read after write data 0x%x\n",
+ addr, val1, val2, ecc_err, val3);
+
+ puts("\tECC test: Enabled DDR ECC ...\n");
+
val1 = readl(addr);
printf("\tECC test: addr 0x%x, read data 0x%x\n", addr, val1);
@@ -242,8 +243,8 @@
if (ecc_ctrl & EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK) {
start_addr = ((range & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16)
+ CONFIG_SYS_SDRAM_BASE;
- end_addr = start_addr + (range & EMIF_ECC_REG_ECC_END_ADDR_MASK)
- + 0xFFFF;
+ end_addr = (range & EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0xFFFF +
+ CONFIG_SYS_SDRAM_BASE;
if ((addr >= start_addr) && (addr <= end_addr))
/* addr within ecc address range 1 */
return 1;
@@ -254,8 +255,8 @@
range = readl(&emif->emif_ecc_address_range_2);
start_addr = ((range & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16)
+ CONFIG_SYS_SDRAM_BASE;
- end_addr = start_addr + (range & EMIF_ECC_REG_ECC_END_ADDR_MASK)
- + 0xFFFF;
+ end_addr = (range & EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0xFFFF +
+ CONFIG_SYS_SDRAM_BASE;
if ((addr >= start_addr) && (addr <= end_addr))
/* addr within ecc address range 2 */
return 1;
diff --git a/common/image.c b/common/image.c
index 62ba6b3..f17fa40 100644
--- a/common/image.c
+++ b/common/image.c
@@ -583,7 +583,7 @@
#if defined(CONFIG_SYS_SDRAM_BASE)
return CONFIG_SYS_SDRAM_BASE;
-#elif defined(CONFIG_ARM)
+#elif defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE)
return gd->bd->bi_dram[0].start;
#else
return 0;
@@ -600,7 +600,8 @@
return tmp;
}
-#if defined(CONFIG_ARM) && defined(CONFIG_NR_DRAM_BANKS)
+#if (defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE)) && \
+ defined(CONFIG_NR_DRAM_BANKS)
start = gd->bd->bi_dram[0].start;
size = gd->bd->bi_dram[0].size;
#else
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 57d06cc..562eafe 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -25,6 +25,15 @@
supports MMC, NAND and YMODEM and other methods loading of U-Boot
and the Linux Kernel. If unsure, say Y.
+config SPL_FRAMEWORK_BOARD_INIT_F
+ bool "Define a generic function board_init_f"
+ depends on SPL_FRAMEWORK
+ help
+ Define a generic function board_init_f that:
+ - initialize the spl (spl_early_init)
+ - initialize the serial (preloader_console_init)
+ Unless you want to provide your own board_init_f, you should say Y.
+
config SPL_SIZE_LIMIT
hex "Maximum size of SPL image"
depends on SPL
@@ -139,6 +148,7 @@
default 0x10060 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN9I
default 0x20060 if MACH_SUN50I_H6
default 0x00060 if ARCH_SUNXI
+ default 0xfffc0000 if ARCH_ZYNQMP
default 0x0
help
The address in memory that SPL will be running from.
@@ -315,6 +325,12 @@
Address on the MMC to load U-Boot from, when the MMC is being used
in raw mode. Units: MMC sectors (1 sector = 512 bytes).
+config SYS_MMCSD_RAW_MODE_EMMC_BOOT_PARTITION
+ int "Number of the eMMC boot partition to use"
+ default 1
+ help
+ eMMC boot partition number to use when the eMMC in raw mode.
+
config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
bool "MMC Raw mode: by partition"
help
@@ -681,6 +697,13 @@
Enable support for loading payloads from UBI. See
README.ubispl for more info.
+if SPL_DM
+config SPL_DM_SPI
+ bool "Support SPI DM drivers in SPL"
+ help
+ Enable support for SPI DM drivers in SPL.
+
+endif
if SPL_UBI
config SPL_UBI_LOAD_BY_VOLNAME
bool "Support loading volumes by name"
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 5fdd6d0..a9d3e84 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -555,6 +555,24 @@
return -ENODEV;
}
+#if defined(CONFIG_SPL_FRAMEWORK_BOARD_INIT_F)
+void board_init_f(ulong dummy)
+{
+ if (CONFIG_IS_ENABLED(OF_CONTROL)) {
+ int ret;
+
+ ret = spl_early_init();
+ if (ret) {
+ debug("spl_early_init() failed: %d\n", ret);
+ hang();
+ }
+ }
+
+ if (CONFIG_IS_ENABLED(SERIAL_SUPPORT))
+ preloader_console_init();
+}
+#endif
+
void board_init_r(gd_t *dummy1, ulong dummy2)
{
u32 spl_boot_list[] = {
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index ebc5660..c5cae97 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -355,28 +355,32 @@
err = -EINVAL;
switch (boot_mode) {
case MMCSD_MODE_EMMCBOOT:
- /*
- * We need to check what the partition is configured to.
- * 1 and 2 match up to boot0 / boot1 and 7 is user data
- * which is the first physical partition (0).
- */
- part = (mmc->part_config >> 3) & PART_ACCESS_MASK;
+#ifdef CONFIG_SYS_MMCSD_RAW_MODE_EMMC_BOOT_PARTITION
+ part = CONFIG_SYS_MMCSD_RAW_MODE_EMMC_BOOT_PARTITION;
+#else
+ /*
+ * We need to check what the partition is configured to.
+ * 1 and 2 match up to boot0 / boot1 and 7 is user data
+ * which is the first physical partition (0).
+ */
+ part = (mmc->part_config >> 3) & PART_ACCESS_MASK;
- if (part == 7)
- part = 0;
-
- if (CONFIG_IS_ENABLED(MMC_TINY))
- err = mmc_switch_part(mmc, part);
- else
- err = blk_dselect_hwpart(mmc_get_blk_desc(mmc), part);
-
- if (err) {
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
- puts("spl: mmc partition switch failed\n");
+ if (part == 7)
+ part = 0;
#endif
- return err;
- }
- /* Fall through */
+
+ if (CONFIG_IS_ENABLED(MMC_TINY))
+ err = mmc_switch_part(mmc, part);
+ else
+ err = blk_dselect_hwpart(mmc_get_blk_desc(mmc), part);
+
+ if (err) {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+ puts("spl: mmc partition switch failed\n");
+#endif
+ return err;
+ }
+ /* Fall through */
case MMCSD_MODE_RAW:
debug("spl: mmc boot mode: raw\n");
diff --git a/common/spl/spl_ymodem.c b/common/spl/spl_ymodem.c
index 20f4260..c02c056 100644
--- a/common/spl/spl_ymodem.c
+++ b/common/spl/spl_ymodem.c
@@ -44,7 +44,8 @@
while (info->image_read < offset) {
res = xyzModem_stream_read(buf, BUF_SIZE, &err);
if (res <= 0)
- return res;
+ break;
+
info->image_read += res;
}
@@ -57,7 +58,7 @@
while (info->image_read < offset + size) {
res = xyzModem_stream_read(buf, BUF_SIZE, &err);
if (res <= 0)
- return res;
+ break;
memcpy(addr, buf, res);
info->image_read += res;
@@ -67,8 +68,8 @@
return size;
}
-static int spl_ymodem_load_image(struct spl_image_info *spl_image,
- struct spl_boot_device *bootdev)
+int spl_ymodem_load_image(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
{
ulong size = 0;
int err;
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index 2aa9b65..93a28b2 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -77,3 +77,5 @@
CONFIG_RSA=y
CONFIG_LZO=y
# CONFIG_OF_LIBFDT_OVERLAY is not set
+CONFIG_CLK=y
+CONFIG_CLK_CDCE9XX=y
diff --git a/configs/am335x_guardian_defconfig b/configs/am335x_guardian_defconfig
index 3cada51..3ce3241 100644
--- a/configs/am335x_guardian_defconfig
+++ b/configs/am335x_guardian_defconfig
@@ -6,11 +6,10 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_AM33XX=y
CONFIG_TARGET_AM335X_GUARDIAN=y
-CONFIG_SPL_MMC_SUPPORT=y
+# CONFIG_SPL_MMC_SUPPORT is not set
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_ENV_SIZE=0x040000
-CONFIG_ENV_OFFSET=0x300000
CONFIG_SPL=y
CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_SPL_LIBDISK_SUPPORT=y
@@ -21,6 +20,7 @@
CONFIG_ARCH_MISC_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SEPARATE_BSS=y
+# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_ETH_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
@@ -30,8 +30,8 @@
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_USB_ETHER=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
+# CONFIG_SPL_WATCHDOG_SUPPORT is not set
+# CONFIG_SPL_YMODEM_SUPPORT is not set
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR="d"
@@ -43,14 +43,14 @@
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
+# CONFIG_CMD_MMC is not set
CONFIG_CMD_MTD=y
CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(SPL),256k(SPL.backup1),256k(SPL.backup2),256k(SPL.backup3),1m(u-boot),1m(u-boot.backup1),256k(u-boot-env),256k(u-boot-env.backup1),-(UBI)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(SPL),256k(SPL.backup1),256k(SPL.backup2),256k(SPL.backup3),1m(u-boot),1m(u-boot.backup1),-(UBI)"
CONFIG_CMD_UBI=y
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
@@ -58,14 +58,17 @@
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-guardian"
-CONFIG_ENV_IS_IN_NAND=y
+CONFIG_OF_SEPARATE=y
+CONFIG_ENV_IS_NOWHERE=y
CONFIG_SPL_ENV_IS_NOWHERE=y
CONFIG_SPL_DM=y
+CONFIG_SPL_DM_USB=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
-CONFIG_MMC_OMAP_HS=y
+# CONFIG_DM_MMC is not set
+# CONFIG_MMC is not set
+# CONFIG_MMC_OMAP_HS is not set
CONFIG_MTD=y
CONFIG_NAND=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
@@ -78,15 +81,19 @@
CONFIG_NOP_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_SINGLE=y
+# CONFIG_WATCHDOG is not set
+CONFIG_SPL_WDT=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_SPL_DM_USB_GADGET=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_TI=y
+CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
CONFIG_USB_ETHER=y
+# CONFIG_USB_STORAGE is not set
CONFIG_FAT_WRITE=y
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index 7c74047..5e3e01c 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -18,6 +18,7 @@
CONFIG_SPL_NET_SUPPORT=y
CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_USB_ETHER=y
CONFIG_CMD_SPL=y
@@ -78,3 +79,5 @@
CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_ETHER=y
+CONFIG_CLK=y
+CONFIG_CLK_CDCE9XX=y
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index 3b613e1..e2f558c 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -98,3 +98,5 @@
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
+CONFIG_CLK=y
+CONFIG_CLK_CDCE9XX=y
diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig
index e5b127c..c60978c 100644
--- a/configs/am65x_evm_a53_defconfig
+++ b/configs/am65x_evm_a53_defconfig
@@ -12,13 +12,13 @@
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+# CONFIG_PSCI_RESET is not set
CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
-# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
@@ -35,6 +35,7 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
+CONFIG_CMD_REMOTEPROC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
# CONFIG_ISO_PARTITION is not set
@@ -83,6 +84,7 @@
CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_REMOTEPROC_TI_K3_R5F=y
CONFIG_DM_RESET=y
CONFIG_RESET_TI_SCI=y
CONFIG_DM_SERIAL=y
diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig
index 077aa37..d0619e9 100644
--- a/configs/am65x_evm_r5_defconfig
+++ b/configs/am65x_evm_r5_defconfig
@@ -5,6 +5,7 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x55000
CONFIG_SOC_K3_AM6=y
+CONFIG_K3_EARLY_CONS=y
CONFIG_TARGET_AM654_R5_EVM=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
diff --git a/configs/am65x_hs_evm_a53_defconfig b/configs/am65x_hs_evm_a53_defconfig
index e9fceea..caee953 100644
--- a/configs/am65x_hs_evm_a53_defconfig
+++ b/configs/am65x_hs_evm_a53_defconfig
@@ -21,7 +21,6 @@
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_fit_${boot}; run get_overlaystring; run run_fit"
-# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
diff --git a/configs/avnet_ultra96_rev1_defconfig b/configs/avnet_ultra96_rev1_defconfig
index feffcc0..b5e61e6 100644
--- a/configs/avnet_ultra96_rev1_defconfig
+++ b/configs/avnet_ultra96_rev1_defconfig
@@ -8,7 +8,6 @@
CONFIG_ZYNQ_SDHCI_MAX_FREQ=15000000
CONFIG_ZYNQMP_USB=y
CONFIG_DEBUG_UART=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -18,7 +17,6 @@
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_CMD_BOOTMENU=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_BIND=y
diff --git a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig
index 31e1bda..b9bb0c9 100644
--- a/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig
+++ b/configs/avnet_ultrazedev_cc_v1_0_ultrazedev_som_v1_0_defconfig
@@ -9,7 +9,6 @@
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_SPL_ZYNQMP_TWO_SDHCI=y
CONFIG_DEBUG_UART=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -17,7 +16,6 @@
CONFIG_BOOTDELAY=0
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADP=y
diff --git a/configs/bcm963158_ram_defconfig b/configs/bcm963158_ram_defconfig
index 1d8a81e..74557de 100644
--- a/configs/bcm963158_ram_defconfig
+++ b/configs/bcm963158_ram_defconfig
@@ -20,6 +20,7 @@
CONFIG_CMD_GPIO=y
CONFIG_CMD_MTD=y
CONFIG_CMD_NAND=y
+CONFIG_CMD_SF=y
CONFIG_CMD_CACHE=y
CONFIG_DOS_PARTITION=y
CONFIG_ISO_PARTITION=y
@@ -38,11 +39,17 @@
CONFIG_NAND=y
CONFIG_NAND_BRCMNAND=y
CONFIG_NAND_BRCMNAND_63158=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_CONS_INDEX=0
CONFIG_DM_SERIAL=y
CONFIG_SERIAL_SEARCH_ALL=y
CONFIG_PL01X_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_BCM63XX_HSSPI=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_WDT_BCM6345=y
diff --git a/configs/bcm968580xref_ram_defconfig b/configs/bcm968580xref_ram_defconfig
index 62f9077..6c6f57d 100644
--- a/configs/bcm968580xref_ram_defconfig
+++ b/configs/bcm968580xref_ram_defconfig
@@ -16,6 +16,8 @@
CONFIG_CMD_MTD=y
CONFIG_CMD_NAND=y
CONFIG_CMD_PART=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
CONFIG_DOS_PARTITION=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
@@ -33,11 +35,18 @@
CONFIG_NAND=y
CONFIG_NAND_BRCMNAND=y
CONFIG_NAND_BRCMNAND_6858=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_CONS_INDEX=0
CONFIG_DM_SERIAL=y
CONFIG_SERIAL_SEARCH_ALL=y
CONFIG_BCM6345_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_BCM63XX_HSSPI=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_WDT_BCM6345=y
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index 5cb933d..6729e03 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -14,12 +14,12 @@
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
+# CONFIG_PSCI_RESET is not set
CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
-CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
-# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
@@ -34,6 +34,7 @@
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_REMOTEPROC=y
CONFIG_CMD_SF=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
@@ -72,6 +73,8 @@
CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_REMOTEPROC_TI_K3_DSP=y
+CONFIG_REMOTEPROC_TI_K3_R5F=y
CONFIG_DM_RESET=y
CONFIG_RESET_TI_SCI=y
CONFIG_DM_SERIAL=y
diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig
index 94b9c78..7d2859c 100644
--- a/configs/microblaze-generic_defconfig
+++ b/configs/microblaze-generic_defconfig
@@ -37,10 +37,12 @@
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
CONFIG_CMD_JFFS2=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
CONFIG_SPL_DM=y
CONFIG_XILINX_GPIO=y
diff --git a/configs/sandbox_noblk_defconfig b/configs/sandbox_noblk_defconfig
deleted file mode 100644
index 381bad2..0000000
--- a/configs/sandbox_noblk_defconfig
+++ /dev/null
@@ -1,178 +0,0 @@
-CONFIG_SYS_TEXT_BASE=0
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_BOOTSTAGE_STASH_ADDR=0x0
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_FIT=y
-CONFIG_FIT_SIGNATURE=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_BOOTSTAGE=y
-CONFIG_BOOTSTAGE_REPORT=y
-CONFIG_BOOTSTAGE_FDT=y
-CONFIG_BOOTSTAGE_STASH=y
-CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_CONSOLE_RECORD=y
-CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
-CONFIG_SILENT_CONSOLE=y
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-# CONFIG_AVB_VERIFY is not set
-CONFIG_CMD_CPU=y
-CONFIG_CMD_LICENSE=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_ELF is not set
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_ENV_CALLBACK=y
-CONFIG_CMD_ENV_FLAGS=y
-CONFIG_LOOPW=y
-CONFIG_CMD_MD5SUM=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_CMD_MX_CYCLIC=y
-CONFIG_CMD_DEMO=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_OSD=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_REMOTEPROC=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_TFTPSRV=y
-CONFIG_CMD_RARP=y
-CONFIG_CMD_CDP=y
-CONFIG_CMD_SNTP=y
-CONFIG_CMD_DNS=y
-CONFIG_CMD_LINK_LOCAL=y
-CONFIG_CMD_BMP=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_TIMER=y
-CONFIG_CMD_SOUND=y
-CONFIG_CMD_BOOTSTAGE=y
-CONFIG_CMD_PMIC=y
-CONFIG_CMD_REGULATOR=y
-CONFIG_CMD_TPM=y
-CONFIG_CMD_TPM_TEST=y
-CONFIG_CMD_CBFS=y
-CONFIG_CMD_CRAMFS=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_MAC_PARTITION=y
-CONFIG_AMIGA_PARTITION=y
-CONFIG_OF_CONTROL=y
-CONFIG_OF_HOSTFILE=y
-CONFIG_DEFAULT_DEVICE_TREE="sandbox"
-CONFIG_NETCONSOLE=y
-CONFIG_IP_DEFRAG=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_DEVRES=y
-CONFIG_DEBUG_DEVRES=y
-CONFIG_ADC=y
-CONFIG_ADC_SANDBOX=y
-# CONFIG_BLK is not set
-CONFIG_CLK=y
-CONFIG_CPU=y
-CONFIG_DM_DEMO=y
-CONFIG_DM_DEMO_SIMPLE=y
-CONFIG_DM_DEMO_SHAPE=y
-CONFIG_BOARD=y
-CONFIG_BOARD_SANDBOX=y
-CONFIG_PM8916_GPIO=y
-CONFIG_SANDBOX_GPIO=y
-CONFIG_I2C_CROS_EC_TUNNEL=y
-CONFIG_I2C_CROS_EC_LDO=y
-CONFIG_DM_I2C_GPIO=y
-CONFIG_SYS_I2C_SANDBOX=y
-CONFIG_I2C_MUX=y
-CONFIG_SPL_I2C_MUX=y
-CONFIG_I2C_ARB_GPIO_CHALLENGE=y
-CONFIG_CROS_EC_KEYB=y
-CONFIG_I8042_KEYB=y
-CONFIG_LED=y
-CONFIG_LED_BLINK=y
-CONFIG_LED_GPIO=y
-CONFIG_CROS_EC=y
-CONFIG_CROS_EC_I2C=y
-CONFIG_CROS_EC_LPC=y
-CONFIG_CROS_EC_SANDBOX=y
-CONFIG_CROS_EC_SPI=y
-CONFIG_PWRSEQ=y
-CONFIG_SPL_PWRSEQ=y
-# CONFIG_MMC is not set
-CONFIG_SPI_FLASH_SANDBOX=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_ETH=y
-CONFIG_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_DM_PCI_COMPAT=y
-CONFIG_PCI_SANDBOX=y
-CONFIG_PHY=y
-CONFIG_PHY_SANDBOX=y
-CONFIG_PINCTRL=y
-CONFIG_PINCONF=y
-CONFIG_PINCTRL_SANDBOX=y
-CONFIG_DM_PMIC=y
-CONFIG_PMIC_ACT8846=y
-CONFIG_DM_PMIC_PFUZE100=y
-CONFIG_DM_PMIC_MAX77686=y
-CONFIG_PMIC_PM8916=y
-CONFIG_PMIC_RK8XX=y
-CONFIG_PMIC_S2MPS11=y
-CONFIG_DM_PMIC_SANDBOX=y
-CONFIG_PMIC_S5M8767=y
-CONFIG_PMIC_TPS65090=y
-CONFIG_DM_REGULATOR=y
-CONFIG_REGULATOR_ACT8846=y
-CONFIG_DM_REGULATOR_PFUZE100=y
-CONFIG_DM_REGULATOR_MAX77686=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_REGULATOR_RK8XX=y
-CONFIG_REGULATOR_S5M8767=y
-CONFIG_DM_REGULATOR_SANDBOX=y
-CONFIG_REGULATOR_TPS65090=y
-CONFIG_DM_PWM=y
-CONFIG_PWM_SANDBOX=y
-CONFIG_RAM=y
-CONFIG_REMOTEPROC_SANDBOX=y
-CONFIG_DM_RTC=y
-CONFIG_SANDBOX_SERIAL=y
-CONFIG_SOUND=y
-CONFIG_SOUND_SANDBOX=y
-CONFIG_SANDBOX_SPI=y
-CONFIG_SPMI=y
-CONFIG_SPMI_SANDBOX=y
-CONFIG_SYSRESET=y
-CONFIG_TIMER=y
-CONFIG_TIMER_EARLY=y
-CONFIG_SANDBOX_TIMER=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_EMUL=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_DM_VIDEO=y
-CONFIG_CONSOLE_ROTATION=y
-CONFIG_CONSOLE_TRUETYPE=y
-CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y
-CONFIG_VIDEO_SANDBOX_SDL=y
-CONFIG_OSD=y
-CONFIG_SANDBOX_OSD=y
-# CONFIG_VIRTIO_BLK is not set
-CONFIG_FS_CBFS=y
-CONFIG_FS_CRAMFS=y
-CONFIG_CMD_DHRYSTONE=y
-CONFIG_TPM=y
-CONFIG_LZ4=y
-CONFIG_ERRNO_STR=y
-CONFIG_UNIT_TEST=y
-CONFIG_UT_TIME=y
-CONFIG_UT_DM=y
diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig
index 8b72983..6f89372 100644
--- a/configs/syzygy_hub_defconfig
+++ b/configs/syzygy_hub_defconfig
@@ -19,7 +19,6 @@
CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADFS=y
diff --git a/configs/xilinx_versal_mini_defconfig b/configs/xilinx_versal_mini_defconfig
index 012ba3e..742aa12 100644
--- a/configs/xilinx_versal_mini_defconfig
+++ b/configs/xilinx_versal_mini_defconfig
@@ -8,8 +8,11 @@
CONFIG_SYS_MALLOC_LEN=0x2000
CONFIG_SYS_MEM_RSVD_FOR_MMU=y
CONFIG_COUNTER_FREQUENCY=2720000
+# CONFIG_PSCI_RESET is not set
+# CONFIG_EXPERT is not set
# CONFIG_LEGACY_IMAGE_FORMAT is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_BOARD_LATE_INIT is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_CMDLINE_EDITING is not set
diff --git a/configs/xilinx_versal_mini_emmc0_defconfig b/configs/xilinx_versal_mini_emmc0_defconfig
index 440035f..7610abf 100644
--- a/configs/xilinx_versal_mini_emmc0_defconfig
+++ b/configs/xilinx_versal_mini_emmc0_defconfig
@@ -7,7 +7,10 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_COUNTER_FREQUENCY=2720000
+# CONFIG_PSCI_RESET is not set
+# CONFIG_EXPERT is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_BOARD_LATE_INIT is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_CMDLINE_EDITING is not set
@@ -49,4 +52,5 @@
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_FAT_WRITE=y
# CONFIG_EFI_LOADER is not set
diff --git a/configs/xilinx_versal_mini_emmc1_defconfig b/configs/xilinx_versal_mini_emmc1_defconfig
index 07ec6eb..ffc913a 100644
--- a/configs/xilinx_versal_mini_emmc1_defconfig
+++ b/configs/xilinx_versal_mini_emmc1_defconfig
@@ -7,7 +7,10 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MALLOC_LEN=0x80000
CONFIG_COUNTER_FREQUENCY=2720000
+# CONFIG_PSCI_RESET is not set
+# CONFIG_EXPERT is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_BOARD_LATE_INIT is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_CMDLINE_EDITING is not set
@@ -49,4 +52,5 @@
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_FAT_WRITE=y
# CONFIG_EFI_LOADER is not set
diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig
index 3b07545..3ff23a2 100644
--- a/configs/xilinx_versal_virt_defconfig
+++ b/configs/xilinx_versal_virt_defconfig
@@ -2,16 +2,14 @@
CONFIG_ARCH_VERSAL=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_DEBUG_UART_BASE=0xff000000
-CONFIG_DEBUG_UART_CLOCK=0
CONFIG_COUNTER_FREQUENCY=62500000
-CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_BOOTDELAY=-1
CONFIG_SUPPORT_RAW_INITRD=y
+# CONFIG_BOARD_LATE_INIT is not set
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
@@ -44,6 +42,7 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=4096
+CONFIG_CLK_VERSAL=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
@@ -66,8 +65,6 @@
CONFIG_PHY_GIGE=y
CONFIG_MII=y
CONFIG_ZYNQ_GEM=y
-CONFIG_DEBUG_UART_PL011=y
-CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_PL01X_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
diff --git a/configs/xilinx_zynqmp_a2197_g_revA_defconfig b/configs/xilinx_zynqmp_a2197_g_revA_defconfig
new file mode 100644
index 0000000..47a98c6
--- /dev/null
+++ b/configs/xilinx_zynqmp_a2197_g_revA_defconfig
@@ -0,0 +1,115 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal"
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_ZYNQMP_USB=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
+CONFIG_CMD_THOR_DOWNLOAD=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SDRAM=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-a2197-g-revA"
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SATA_CEVA=y
+CONFIG_CLK_ZYNQMP=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_DM_GPIO=y
+CONFIG_XILINX_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x0
+CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TI=y
+CONFIG_PHY_VITESSE=y
+CONFIG_PHY_FIXED=y
+CONFIG_PHY_GIGE=y
+CONFIG_MII=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
+CONFIG_ZYNQMP_GQSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_ZYNQMP=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
+CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
+CONFIG_USB_FUNCTION_THOR=y
+CONFIG_SPL_GZIP=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_a2197_m_revA_defconfig b/configs/xilinx_zynqmp_a2197_m_revA_defconfig
new file mode 100644
index 0000000..fb4020b
--- /dev/null
+++ b/configs/xilinx_zynqmp_a2197_m_revA_defconfig
@@ -0,0 +1,115 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal"
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_ZYNQMP_USB=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
+CONFIG_CMD_THOR_DOWNLOAD=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SDRAM=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-a2197-m-revA"
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SATA_CEVA=y
+CONFIG_CLK_ZYNQMP=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_DM_GPIO=y
+CONFIG_XILINX_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x0
+CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TI=y
+CONFIG_PHY_VITESSE=y
+CONFIG_PHY_FIXED=y
+CONFIG_PHY_GIGE=y
+CONFIG_MII=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
+CONFIG_ZYNQMP_GQSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_ZYNQMP=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
+CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
+CONFIG_USB_FUNCTION_THOR=y
+CONFIG_SPL_GZIP=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_a2197_p_revA_defconfig b/configs/xilinx_zynqmp_a2197_p_revA_defconfig
new file mode 100644
index 0000000..d19c6b3
--- /dev/null
+++ b/configs/xilinx_zynqmp_a2197_p_revA_defconfig
@@ -0,0 +1,116 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal"
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_ZYNQMP_USB=y
+CONFIG_SPL_ZYNQMP_TWO_SDHCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
+CONFIG_CMD_THOR_DOWNLOAD=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SDRAM=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-a2197-p-revA"
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SATA_CEVA=y
+CONFIG_CLK_ZYNQMP=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_DM_GPIO=y
+CONFIG_XILINX_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x0
+CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TI=y
+CONFIG_PHY_VITESSE=y
+CONFIG_PHY_FIXED=y
+CONFIG_PHY_GIGE=y
+CONFIG_MII=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
+CONFIG_ZYNQMP_GQSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_ZYNQMP=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
+CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
+CONFIG_USB_FUNCTION_THOR=y
+CONFIG_SPL_GZIP=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_a2197_revA_defconfig b/configs/xilinx_zynqmp_a2197_revA_defconfig
new file mode 100644
index 0000000..3498483
--- /dev/null
+++ b/configs/xilinx_zynqmp_a2197_revA_defconfig
@@ -0,0 +1,117 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal"
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_ZYNQMP_USB=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
+CONFIG_CMD_THOR_DOWNLOAD=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SDRAM=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-a2197-revA"
+CONFIG_OF_LIST="zynqmp-a2197-revA zynqmp-a2197-g-revA zynqmp-a2197-p-revA zynqmp-a2197-m-revA"
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SATA_CEVA=y
+CONFIG_CLK_ZYNQMP=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_DM_GPIO=y
+CONFIG_XILINX_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x0
+CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TI=y
+CONFIG_PHY_VITESSE=y
+CONFIG_PHY_FIXED=y
+CONFIG_PHY_GIGE=y
+CONFIG_MII=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
+CONFIG_ZYNQMP_GQSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_ZYNQMP=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
+CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
+CONFIG_USB_FUNCTION_THOR=y
+CONFIG_SPL_GZIP=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_mini_defconfig b/configs/xilinx_zynqmp_mini_defconfig
index 93fa7d8..4b7fe5d 100644
--- a/configs/xilinx_zynqmp_mini_defconfig
+++ b/configs/xilinx_zynqmp_mini_defconfig
@@ -13,7 +13,6 @@
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
# CONFIG_SYS_LONGHELP is not set
-CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_AUTOBOOT is not set
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig
index f15c093..282e93f 100644
--- a/configs/xilinx_zynqmp_mini_emmc0_defconfig
+++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig
@@ -7,7 +7,6 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
# CONFIG_CMD_ZYNQMP is not set
-CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
# CONFIG_BOARD_LATE_INIT is not set
@@ -15,7 +14,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_AUTOBOOT is not set
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig
index fb9a182..be70988 100644
--- a/configs/xilinx_zynqmp_mini_emmc1_defconfig
+++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig
@@ -7,7 +7,6 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
# CONFIG_CMD_ZYNQMP is not set
-CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
# CONFIG_BOARD_LATE_INIT is not set
@@ -15,7 +14,6 @@
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_AUTOBOOT is not set
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
diff --git a/configs/xilinx_zynqmp_mini_nand_defconfig b/configs/xilinx_zynqmp_mini_nand_defconfig
index 4be6248..35776ab 100644
--- a/configs/xilinx_zynqmp_mini_nand_defconfig
+++ b/configs/xilinx_zynqmp_mini_nand_defconfig
@@ -14,7 +14,6 @@
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
# CONFIG_SYS_LONGHELP is not set
-CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_AUTOBOOT is not set
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
@@ -49,4 +48,5 @@
# CONFIG_MMC is not set
CONFIG_NAND=y
CONFIG_NAND_ARASAN=y
+CONFIG_SYS_NAND_MAX_CHIPS=2
# CONFIG_EFI_LOADER is not set
diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig
index bc63c08..383f868 100644
--- a/configs/xilinx_zynqmp_mini_qspi_defconfig
+++ b/configs/xilinx_zynqmp_mini_qspi_defconfig
@@ -10,7 +10,6 @@
CONFIG_ZYNQMP_NO_DDR=y
# CONFIG_PSCI_RESET is not set
# CONFIG_CMD_ZYNQMP is not set
-CONFIG_SPL_TEXT_BASE=0xfffc0000
# CONFIG_EXPERT is not set
# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_BOARD_LATE_INIT is not set
@@ -18,7 +17,6 @@
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
# CONFIG_SYS_LONGHELP is not set
-CONFIG_SYS_PROMPT="ZynqMP> "
# CONFIG_AUTOBOOT is not set
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig
new file mode 100644
index 0000000..14eb06a
--- /dev/null
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -0,0 +1,108 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_ZYNQMP_USB=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
+CONFIG_CMD_THOR_DOWNLOAD=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SDRAM=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_BOARD=y
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SATA_CEVA=y
+CONFIG_CLK_ZYNQMP=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_DM_GPIO=y
+CONFIG_XILINX_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x20
+CONFIG_SYS_I2C_EEPROM_ADDR=0x0
+CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TI=y
+CONFIG_PHY_VITESSE=y
+CONFIG_PHY_FIXED=y
+CONFIG_PHY_GIGE=y
+CONFIG_MII=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
+CONFIG_ZYNQMP_GQSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_ZYNQMP=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
+CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
+CONFIG_USB_FUNCTION_THOR=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zc1232_revA_defconfig b/configs/xilinx_zynqmp_zc1232_revA_defconfig
index beb6d43..255217d 100644
--- a/configs/xilinx_zynqmp_zc1232_revA_defconfig
+++ b/configs/xilinx_zynqmp_zc1232_revA_defconfig
@@ -8,7 +8,6 @@
# CONFIG_SPL_FS_FAT is not set
# CONFIG_SPL_LIBDISK_SUPPORT is not set
CONFIG_DEBUG_UART=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -18,7 +17,6 @@
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/xilinx_zynqmp_zc1254_revA_defconfig b/configs/xilinx_zynqmp_zc1254_revA_defconfig
index 849a398..e058195 100644
--- a/configs/xilinx_zynqmp_zc1254_revA_defconfig
+++ b/configs/xilinx_zynqmp_zc1254_revA_defconfig
@@ -8,7 +8,6 @@
# CONFIG_SPL_FS_FAT is not set
# CONFIG_SPL_LIBDISK_SUPPORT is not set
CONFIG_DEBUG_UART=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -18,7 +17,6 @@
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index a1e69b2..bbf387a 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -9,7 +9,6 @@
CONFIG_SPL_ZYNQMP_TWO_SDHCI=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -20,7 +19,6 @@
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
index 02f6d4a..d5434ee 100644
--- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
@@ -9,7 +9,6 @@
# CONFIG_SPL_LIBDISK_SUPPORT is not set
CONFIG_ZYNQMP_USB=y
CONFIG_DEBUG_UART=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -20,7 +19,6 @@
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig
index c243064..4ff5229 100644
--- a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig
@@ -8,7 +8,6 @@
CONFIG_ZYNQMP_USB=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -18,7 +17,6 @@
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
index e964fab..a5a7fc2 100644
--- a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
@@ -6,7 +6,6 @@
CONFIG_DEBUG_UART_BASE=0xff000000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_DEBUG_UART=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -17,7 +16,6 @@
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_CLK=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
index 5856d95..5b8cf77 100644
--- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
@@ -6,7 +6,6 @@
CONFIG_DEBUG_UART_BASE=0xff000000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_DEBUG_UART=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -17,7 +16,6 @@
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_CLK=y
diff --git a/configs/xilinx_zynqmp_zcu100_revC_defconfig b/configs/xilinx_zynqmp_zcu100_revC_defconfig
index 1ec1bdc..fc917f0 100644
--- a/configs/xilinx_zynqmp_zcu100_revC_defconfig
+++ b/configs/xilinx_zynqmp_zcu100_revC_defconfig
@@ -8,7 +8,6 @@
CONFIG_ZYNQ_SDHCI_MAX_FREQ=15000000
CONFIG_ZYNQMP_USB=y
CONFIG_DEBUG_UART=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -18,7 +17,6 @@
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_CMD_BOOTMENU=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_BIND=y
diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
index b27887e..b64956d 100644
--- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
@@ -10,7 +10,6 @@
CONFIG_ZYNQMP_USB=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -21,7 +20,6 @@
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
@@ -59,6 +57,7 @@
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
+CONFIG_GPIO_HOG=y
CONFIG_XILINX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig b/configs/xilinx_zynqmp_zcu102_revA_defconfig
index 7746305..8b1a1ce 100644
--- a/configs/xilinx_zynqmp_zcu102_revA_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig
@@ -10,7 +10,6 @@
CONFIG_ZYNQMP_USB=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -21,7 +20,6 @@
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
@@ -59,6 +57,7 @@
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
+CONFIG_GPIO_HOG=y
CONFIG_XILINX_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index 3d58c01..2aab26d 100644
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -10,7 +10,6 @@
CONFIG_ZYNQMP_USB=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -21,7 +20,6 @@
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
@@ -59,6 +57,7 @@
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
+CONFIG_GPIO_HOG=y
CONFIG_XILINX_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
diff --git a/configs/xilinx_zynqmp_zcu104_revA_defconfig b/configs/xilinx_zynqmp_zcu104_revA_defconfig
index e21c34c..07e58b1 100644
--- a/configs/xilinx_zynqmp_zcu104_revA_defconfig
+++ b/configs/xilinx_zynqmp_zcu104_revA_defconfig
@@ -8,7 +8,6 @@
CONFIG_ZYNQMP_USB=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -18,7 +17,6 @@
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
diff --git a/configs/xilinx_zynqmp_zcu104_revC_defconfig b/configs/xilinx_zynqmp_zcu104_revC_defconfig
index 3d66d0a..4829df6 100644
--- a/configs/xilinx_zynqmp_zcu104_revC_defconfig
+++ b/configs/xilinx_zynqmp_zcu104_revC_defconfig
@@ -5,10 +5,11 @@
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xff000000
CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ZYNQMP_USB=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -17,8 +18,8 @@
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
diff --git a/configs/xilinx_zynqmp_zcu106_revA_defconfig b/configs/xilinx_zynqmp_zcu106_revA_defconfig
index 300d3b2..72b3ce1 100644
--- a/configs/xilinx_zynqmp_zcu106_revA_defconfig
+++ b/configs/xilinx_zynqmp_zcu106_revA_defconfig
@@ -10,7 +10,6 @@
CONFIG_ZYNQMP_USB=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -20,7 +19,6 @@
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
diff --git a/configs/xilinx_zynqmp_zcu111_revA_defconfig b/configs/xilinx_zynqmp_zcu111_revA_defconfig
index a4caaff..de739ed 100644
--- a/configs/xilinx_zynqmp_zcu111_revA_defconfig
+++ b/configs/xilinx_zynqmp_zcu111_revA_defconfig
@@ -8,7 +8,6 @@
CONFIG_ZYNQMP_USB=y
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -18,7 +17,6 @@
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
diff --git a/configs/xilinx_zynqmp_zcu1275_revA_defconfig b/configs/xilinx_zynqmp_zcu1275_revA_defconfig
index 4790061..d86c5d1 100644
--- a/configs/xilinx_zynqmp_zcu1275_revA_defconfig
+++ b/configs/xilinx_zynqmp_zcu1275_revA_defconfig
@@ -8,7 +8,6 @@
# CONFIG_SPL_FS_FAT is not set
# CONFIG_SPL_LIBDISK_SUPPORT is not set
CONFIG_DEBUG_UART=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -18,7 +17,6 @@
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/xilinx_zynqmp_zcu1275_revB_defconfig b/configs/xilinx_zynqmp_zcu1275_revB_defconfig
index ce2aa24..957b883 100644
--- a/configs/xilinx_zynqmp_zcu1275_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu1275_revB_defconfig
@@ -8,7 +8,6 @@
# CONFIG_SPL_FS_FAT is not set
# CONFIG_SPL_LIBDISK_SUPPORT is not set
CONFIG_DEBUG_UART=y
-CONFIG_SPL_TEXT_BASE=0xfffc0000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
@@ -18,7 +17,6 @@
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_ATF=y
-CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/zynq_cc108_defconfig b/configs/zynq_cc108_defconfig
index 9bfe5ce..495c5df 100644
--- a/configs/zynq_cc108_defconfig
+++ b/configs/zynq_cc108_defconfig
@@ -18,7 +18,6 @@
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
-CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig
index 0910d3b..8740997 100644
--- a/configs/zynq_cse_nand_defconfig
+++ b/configs/zynq_cse_nand_defconfig
@@ -17,7 +17,6 @@
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
# CONFIG_SYS_LONGHELP is not set
-CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_AUTOBOOT is not set
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig
index 0a6b172..a786fa2 100644
--- a/configs/zynq_cse_nor_defconfig
+++ b/configs/zynq_cse_nor_defconfig
@@ -17,7 +17,6 @@
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
# CONFIG_SYS_LONGHELP is not set
-CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_AUTOBOOT is not set
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig
index 4972d70..0cc6976 100644
--- a/configs/zynq_cse_qspi_defconfig
+++ b/configs/zynq_cse_qspi_defconfig
@@ -26,7 +26,6 @@
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
# CONFIG_SYS_LONGHELP is not set
-CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_AUTOBOOT is not set
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
diff --git a/configs/zynq_dlc20_rev1_0_defconfig b/configs/zynq_dlc20_rev1_0_defconfig
index b6751ad..00d1a59 100644
--- a/configs/zynq_dlc20_rev1_0_defconfig
+++ b/configs/zynq_dlc20_rev1_0_defconfig
@@ -21,7 +21,6 @@
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
-CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig
index d30581b..751d373 100644
--- a/configs/zynq_microzed_defconfig
+++ b/configs/zynq_microzed_defconfig
@@ -16,7 +16,6 @@
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
-CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/zynq_minized_defconfig b/configs/zynq_minized_defconfig
index 3c95f0a..d9657f9 100644
--- a/configs/zynq_minized_defconfig
+++ b/configs/zynq_minized_defconfig
@@ -16,7 +16,6 @@
CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig
index 6457876..c72307a 100644
--- a/configs/zynq_picozed_defconfig
+++ b/configs/zynq_picozed_defconfig
@@ -10,7 +10,6 @@
CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/zynq_virt_defconfig b/configs/zynq_virt_defconfig
new file mode 100644
index 0000000..58ce970
--- /dev/null
+++ b/configs/zynq_virt_defconfig
@@ -0,0 +1,79 @@
+CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_ZYNQ=y
+CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL_STACK_R_ADDR=0x200000
+CONFIG_SPL=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_CUSTOM_LDSCRIPT=y
+CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_USE_PREBOOT=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
+CONFIG_CMD_THOR_DOWNLOAD=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADFS=y
+CONFIG_CMD_FPGA_LOADMK=y
+CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_BOARD=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQPL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x0
+CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=30000000
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_XILINX=y
+CONFIG_MII=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_ZYNQ_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
+CONFIG_USB_GADGET_VENDOR_NUM=0x03fd
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_THOR=y
diff --git a/configs/zynq_z_turn_defconfig b/configs/zynq_z_turn_defconfig
index d133fea..799277c 100644
--- a/configs/zynq_z_turn_defconfig
+++ b/configs/zynq_z_turn_defconfig
@@ -19,7 +19,6 @@
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
-CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig
index 6b670ae..74e8b3e 100644
--- a/configs/zynq_zc702_defconfig
+++ b/configs/zynq_zc702_defconfig
@@ -20,7 +20,6 @@
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
-CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DFU=y
diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig
index 3d0cd31..f831039 100644
--- a/configs/zynq_zc706_defconfig
+++ b/configs/zynq_zc706_defconfig
@@ -23,7 +23,6 @@
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
-CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig
index 53108ff..301bc2d 100644
--- a/configs/zynq_zc770_xm010_defconfig
+++ b/configs/zynq_zc770_xm010_defconfig
@@ -20,7 +20,6 @@
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
-CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADFS=y
diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig
index feedb32..8bc49ea 100644
--- a/configs/zynq_zc770_xm011_defconfig
+++ b/configs/zynq_zc770_xm011_defconfig
@@ -19,7 +19,6 @@
CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADFS=y
diff --git a/configs/zynq_zc770_xm011_x16_defconfig b/configs/zynq_zc770_xm011_x16_defconfig
index 28d63c9..70429a2 100644
--- a/configs/zynq_zc770_xm011_x16_defconfig
+++ b/configs/zynq_zc770_xm011_x16_defconfig
@@ -19,7 +19,6 @@
CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADFS=y
diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig
index 01e3d5f..78cdd9c 100644
--- a/configs/zynq_zc770_xm012_defconfig
+++ b/configs/zynq_zc770_xm012_defconfig
@@ -16,7 +16,6 @@
CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_IMLS=y
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADFS=y
diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig
index 30bb0ef..c667878 100644
--- a/configs/zynq_zc770_xm013_defconfig
+++ b/configs/zynq_zc770_xm013_defconfig
@@ -18,7 +18,6 @@
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
-CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADFS=y
diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig
index 9b6d754..38bf3e4 100644
--- a/configs/zynq_zed_defconfig
+++ b/configs/zynq_zed_defconfig
@@ -19,7 +19,6 @@
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
-CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig
index 2abc6db..71d1638 100644
--- a/configs/zynq_zybo_defconfig
+++ b/configs/zynq_zybo_defconfig
@@ -19,7 +19,6 @@
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
-CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
diff --git a/configs/zynq_zybo_z7_defconfig b/configs/zynq_zybo_z7_defconfig
index eda1416..0cc525c 100644
--- a/configs/zynq_zybo_z7_defconfig
+++ b/configs/zynq_zybo_z7_defconfig
@@ -19,7 +19,6 @@
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
-CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
diff --git a/doc/arch/sandbox.rst b/doc/arch/sandbox.rst
index 54933b5..e1f4dde 100644
--- a/doc/arch/sandbox.rst
+++ b/doc/arch/sandbox.rst
@@ -209,17 +209,12 @@
We need this build so that we can test those inline functions, and we
cannot build with both the inline functions and the non-inline functions
since they are named the same.
-sandbox_noblk:
- builds without CONFIG_BLK, which means the legacy block
- drivers are used. We cannot use both the legacy and driver-model block
- drivers since they implement the same functions
sandbox_spl:
builds sandbox with SPL support, so you can run spl/u-boot-spl
and it will start up and then load ./u-boot. It is also possible to
run ./u-boot directly.
-Of these sandbox_noblk can be removed once CONFIG_BLK is used everwhere, and
-sandbox_spl can probably be removed since it is a superset of sandbox.
+Of these sandbox_spl can probably be removed since it is a superset of sandbox.
Most of the config options should be identical between these variants.
diff --git a/doc/board/xilinx/index.rst b/doc/board/xilinx/index.rst
index 2416fbd..47f0929 100644
--- a/doc/board/xilinx/index.rst
+++ b/doc/board/xilinx/index.rst
@@ -6,4 +6,5 @@
.. toctree::
:maxdepth: 2
+ xilinx
zynq
diff --git a/doc/board/xilinx/xilinx.rst b/doc/board/xilinx/xilinx.rst
new file mode 100644
index 0000000..f6ea5db
--- /dev/null
+++ b/doc/board/xilinx/xilinx.rst
@@ -0,0 +1,38 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. (C) Copyright 2019 Xilinx, Inc.
+
+U-Boot device tree bindings
+----------------------------
+
+All the device tree bindings used in U-Boot are specified in Linux
+kernel. Please refer dt bindings from below specified paths in Linux
+kernel.
+
+* ata
+ - Documentation/devicetree/bindings/ata/ahci-ceva.txt
+* gpio
+ - Documentation/devicetree/bindings/gpio/gpio-xilinx.txt
+ - Documentation/devicetree/bindings/gpio/gpio-zynq.txt
+* i2c
+ - Documentation/devicetree/bindings/i2c/i2c-xiic.txt
+ - Documentation/devicetree/bindings/i2c/i2c-cadence.txt
+* mmc
+ - Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
+* net
+ - Documentation/devicetree/bindings/net/macb.txt
+ - Documentation/devicetree/bindings/net/xilinx_axienet.txt
+ - Documentation/devicetree/bindings/net/xilinx_emaclite.txt
+* serial
+ - Documentation/devicetree/bindings/serial/cdns,uart.txt
+ - Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.txt
+* spi
+ - Documentation/devicetree/bindings/spi/spi-cadence.txt
+ - Documentation/devicetree/bindings/spi/spi-xilinx.txt
+ - Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt
+ - Documentation/devicetree/bindings/spi/spi-zynq-qspi.txt
+* usb
+ - Documentation/devicetree/bindings/usb/dwc3-xilinx.txt
+ - Documentation/devicetree/bindings/usb/dwc3.txt
+ - Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt
+* wdt
+ - Documentation/devicetree/bindings/watchdog/of-xilinx-wdt.txt
diff --git a/doc/device-tree-bindings/clock/ti,cdce9xx.txt b/doc/device-tree-bindings/clock/ti,cdce9xx.txt
new file mode 100644
index 0000000..0d01f2d
--- /dev/null
+++ b/doc/device-tree-bindings/clock/ti,cdce9xx.txt
@@ -0,0 +1,49 @@
+Binding for TI CDCE913/925/937/949 programmable I2C clock synthesizers.
+
+Reference
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] http://www.ti.com/product/cdce913
+[3] http://www.ti.com/product/cdce925
+[4] http://www.ti.com/product/cdce937
+[5] http://www.ti.com/product/cdce949
+
+The driver provides clock sources for each output Y1 through Y5.
+
+Required properties:
+ - compatible: Shall be one of the following:
+ - "ti,cdce913": 1-PLL, 3 Outputs
+ - "ti,cdce925": 2-PLL, 5 Outputs
+ - "ti,cdce937": 3-PLL, 7 Outputs
+ - "ti,cdce949": 4-PLL, 9 Outputs
+ - reg: I2C device address.
+ - clocks: Points to a fixed parent clock that provides the input frequency.
+ - #clock-cells: From common clock bindings: Shall be 1.
+
+Optional properties:
+ - xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a
+ board, or to compensate for external influences.
+
+For all PLL1, PLL2, ... an optional child node can be used to specify spread
+spectrum clocking parameters for a board.
+ - spread-spectrum: SSC mode as defined in the data sheet.
+ - spread-spectrum-center: Use "centered" mode instead of "max" mode. When
+ present, the clock runs at the requested frequency on average. Otherwise
+ the requested frequency is the maximum value of the SCC range.
+
+
+Example:
+
+ clockgen: cdce925pw@64 {
+ compatible = "cdce925";
+ reg = <0x64>;
+ clocks = <&xtal_27Mhz>;
+ #clock-cells = <1>;
+ xtal-load-pf = <5>;
+ /* PLL options to get SSC 1% centered */
+ PLL2 {
+ spread-spectrum = <4>;
+ spread-spectrum-center;
+ };
+ };
diff --git a/doc/device-tree-bindings/pci/mediatek-pcie.txt b/doc/device-tree-bindings/pci/mediatek-pcie.txt
new file mode 100644
index 0000000..2f9f549
--- /dev/null
+++ b/doc/device-tree-bindings/pci/mediatek-pcie.txt
@@ -0,0 +1,122 @@
+MediaTek Gen2 PCIe controller
+
+Required properties:
+- compatible: Should contain one of the following strings:
+ "mediatek,mt7623-pcie"
+- device_type: Must be "pci"
+- reg: Base addresses and lengths of the PCIe subsys and root ports.
+- reg-names: Names of the above areas to use during resource lookup.
+- #address-cells: Address representation for root ports (must be 3)
+- #size-cells: Size representation for root ports (must be 2)
+- clocks: Must contain an entry for each entry in clock-names.
+- clock-names:
+ Mandatory entries:
+ - sys_ckN :transaction layer and data link layer clock
+ Required entries for MT7623:
+ - free_ck :for reference clock of PCIe subsys
+ where N starting from 0 to one less than the number of root ports.
+- phys: List of PHY specifiers (used by generic PHY framework).
+- phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
+ number of PHYs as specified in *phys* property.
+- power-domains: A phandle and power domain specifier pair to the power domain
+ which is responsible for collapsing and restoring power to the peripheral.
+- bus-range: Range of bus numbers associated with this controller.
+- ranges: Ranges for the PCI memory and I/O regions.
+
+Required properties for MT7623:
+- #interrupt-cells: Size representation for interrupts (must be 1)
+- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
+ Please refer to the standard PCI bus binding document for a more detailed
+ explanation.
+- resets: Must contain an entry for each entry in reset-names.
+- reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
+ number of root ports.
+
+In addition, the device tree node must have sub-nodes describing each
+PCIe port interface, having the following mandatory properties:
+
+Required properties:
+- device_type: Must be "pci"
+- reg: Only the first four bytes are used to refer to the correct bus number
+ and device number.
+- #address-cells: Must be 3
+- #size-cells: Must be 2
+- #interrupt-cells: Must be 1
+- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
+ Please refer to the standard PCI bus binding document for a more detailed
+ explanation.
+- ranges: Sub-ranges distributed from the PCIe controller node. An empty
+ property is sufficient.
+
+Examples for MT7623:
+
+ hifsys: syscon@1a000000 {
+ compatible = "mediatek,mt7623-hifsys",
+ "syscon";
+ reg = <0x1a000000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ pcie: pcie@1a140000 {
+ compatible = "mediatek,mt7623-pcie";
+ device_type = "pci";
+ reg = <0x1a140000 0x1000>, /* PCIe shared registers */
+ <0x1a142000 0x1000>, /* Port0 registers */
+ <0x1a143000 0x1000>, /* Port1 registers */
+ <0x1a144000 0x1000>; /* Port2 registers */
+ reg-names = "subsys", "port0", "port1", "port2";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 0>;
+ interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
+ <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
+ <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
+ <&hifsys CLK_HIFSYS_PCIE0>,
+ <&hifsys CLK_HIFSYS_PCIE1>,
+ <&hifsys CLK_HIFSYS_PCIE2>;
+ clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
+ resets = <&hifsys HIFSYS_PCIE0_RST>,
+ <&hifsys HIFSYS_PCIE1_RST>,
+ <&hifsys HIFSYS_PCIE2_RST>;
+ reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
+ phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>,
+ <&pcie2_phy PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
+ power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x81000000 0 0x1a160000 0x1a160000 0 0x00010000 /* I/O space */
+ 0x83000000 0 0x60000000 0x60000000 0 0x10000000>; /* memory space */
+
+ pcie@0,0 {
+ reg = <0x0000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
+ ranges;
+ };
+
+ pcie@1,0 {
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
+ ranges;
+ };
+
+ pcie@2,0 {
+ reg = <0x1000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
+ ranges;
+ };
+ };
diff --git a/doc/device-tree-bindings/phy/phy-mtk-tphy.txt b/doc/device-tree-bindings/phy/phy-mtk-tphy.txt
new file mode 100644
index 0000000..037c5a4
--- /dev/null
+++ b/doc/device-tree-bindings/phy/phy-mtk-tphy.txt
@@ -0,0 +1,86 @@
+MediaTek T-PHY binding
+--------------------------
+
+T-phy controller supports physical layer functionality for a number of
+controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA.
+
+Required properties (controller (parent) node):
+ - compatible : should be one of
+ "mediatek,generic-tphy-v1"
+ - clocks : (deprecated, use port's clocks instead) a list of phandle +
+ clock-specifier pairs, one for each entry in clock-names
+ - clock-names : (deprecated, use port's one instead) must contain
+ "u3phya_ref": for reference clock of usb3.0 analog phy.
+
+Required nodes : a sub-node is required for each port the controller
+ provides. Address range information including the usual
+ 'reg' property is used inside these nodes to describe
+ the controller's topology.
+
+Optional properties (controller (parent) node):
+ - reg : offset and length of register shared by multiple ports,
+ exclude port's private register.
+ - mediatek,src-ref-clk-mhz : frequency of reference clock for slew rate
+ calibrate
+ - mediatek,src-coef : coefficient for slew rate calibrate, depends on
+ SoC process
+
+Required properties (port (child) node):
+- reg : address and length of the register set for the port.
+- clocks : a list of phandle + clock-specifier pairs, one for each
+ entry in clock-names
+- clock-names : must contain
+ "ref": 48M reference clock for HighSpeed analog phy; and 26M
+ reference clock for SuperSpeed analog phy, sometimes is
+ 24M, 25M or 27M, depended on platform.
+- #phy-cells : should be 1 (See second example)
+ cell after port phandle is phy type from:
+ - PHY_TYPE_USB2
+ - PHY_TYPE_USB3
+ - PHY_TYPE_PCIE
+ - PHY_TYPE_SATA
+
+Example:
+
+ u3phy2: usb-phy@1a244000 {
+ compatible = "mediatek,generic-tphy-v1";
+ reg = <0x1a244000 0x0700>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ u2port1: usb-phy@1a244800 {
+ reg = <0x1a244800 0x0100>;
+ clocks = <&topckgen CLK_TOP_USB_PHY48M>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ u3port1: usb-phy@1a244900 {
+ reg = <0x1a244900 0x0700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
+
+Specifying phy control of devices
+---------------------------------
+
+Device nodes should specify the configuration required in their "phys"
+property, containing a phandle to the phy port node and a device type;
+phy-names for each port are optional.
+
+Example:
+
+#include <dt-bindings/phy/phy.h>
+
+usb30: usb@11270000 {
+ ...
+ phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
+ phy-names = "usb2-0", "usb3-0";
+ ...
+};
diff --git a/doc/device-tree-bindings/remoteproc/ti,k3-dsp-rproc.txt b/doc/device-tree-bindings/remoteproc/ti,k3-dsp-rproc.txt
new file mode 100644
index 0000000..80ab7a4
--- /dev/null
+++ b/doc/device-tree-bindings/remoteproc/ti,k3-dsp-rproc.txt
@@ -0,0 +1,101 @@
+TI K3 DSP devices
+=================
+
+The TI K3 family of SoCs usually have one or more TI DSP Core sub-systems that
+are used to offload some of the processor-intensive tasks or algorithms, for
+achieving various system level goals.
+
+These processor sub-systems usually contain additional sub-modules like L1
+and/or L2 caches/SRAMs, an Interrupt Controller, an external memory controller,
+a dedicated local power/sleep controller etc. The DSP processor cores in the
+K3 SoCs is usually either a TMS320C66x CorePac processor or a TMS320C71x CorePac
+processor.
+
+DSP Device Node:
+================
+Each DSP Core sub-system is represented as a single DT node. Each node has a
+number of required or optional properties that enable the OS running on the
+host processor (Arm CorePac) to perform the device management of the remote
+processor and to communicate with the remote processor.
+
+Required properties:
+--------------------
+The following are the mandatory properties:
+
+- compatible: Should be one of the following,
+ "ti,j721e-c66-dsp" for C66x DSPs on K3 J721E SoCs
+ "ti,j721e-c71-dsp" for C71x DSPs on K3 J721E SoCs
+
+- reg: Should contain an entry for each value in 'reg-names'.
+ Each entry should have the memory region's start address
+ and the size of the region, the representation matching
+ the parent node's '#address-cells' and '#size-cells' values.
+
+- reg-names: Should contain strings with the following names, each
+ representing a specific internal memory region (if
+ present), and should be defined in this order,
+ "l2sram", "l1pram", "l1dram"
+ NOTE: C71x DSPs do not have a "l1pram" memory.
+
+- ti,sci: Should be a phandle to the TI-SCI System Controller node
+
+- ti,sci-dev-id: Should contain the TI-SCI device id corresponding to the
+ DSP Core. Please refer to the corresponding System
+ Controller documentation for valid values for the DSP
+ cores.
+
+- ti,sci-proc-ids: Should contain 2 integer values. The first cell should
+ contain the TI-SCI processor id for the DSP core device
+ and the second cell should contain the TI-SCI host id to
+ which the processor control ownership should be
+ transferred to.
+
+- resets: Should contain the phandle to the reset controller node
+ managing the resets for this device, and a reset
+ specifier. Please refer to the following reset bindings
+ for the reset argument specifier,
+ Documentation/devicetree/bindings/reset/ti,sci-reset.txt
+
+Example:
+---------
+
+1. J721E SoC
+ /* J721E remoteproc alias */
+ aliases {
+ rproc6 = &c66_0;
+ rproc8 = &c71_0;
+ };
+
+ cbass_main: interconnect@100000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71_0 */
+ <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
+ <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>; /* C66_1 */
+
+ /* J721E C66_0 DSP node */
+ c66_0: dsp@4d80800000 {
+ compatible = "ti,j721e-c66-dsp";
+ reg = <0x4d 0x80800000 0x00 0x00048000>,
+ <0x4d 0x80e00000 0x00 0x00008000>,
+ <0x4d 0x80f00000 0x00 0x00008000>;
+ reg-names = "l2sram", "l1pram", "l1dram";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <142>;
+ ti,sci-proc-ids = <0x03 0xFF>;
+ resets = <&k3_reset 142 1>;
+ };
+
+ /* J721E C71_0 DSP node */
+ c71_0: dsp@64800000 {
+ compatible = "ti,j721e-c71-dsp";
+ reg = <0x00 0x64800000 0x00 0x00080000>,
+ <0x00 0x64e00000 0x00 0x0000c000>;
+ reg-names = "l2sram", "l1dram";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <15>;
+ ti,sci-proc-ids = <0x30 0xFF>;
+ resets = <&k3_reset 15 1>;
+ };
+ };
diff --git a/doc/device-tree-bindings/remoteproc/ti,k3-r5f-rproc.txt b/doc/device-tree-bindings/remoteproc/ti,k3-r5f-rproc.txt
new file mode 100644
index 0000000..c2fa6e8
--- /dev/null
+++ b/doc/device-tree-bindings/remoteproc/ti,k3-r5f-rproc.txt
@@ -0,0 +1,164 @@
+TI K3 R5F processor subsystems
+==============================
+
+The TI K3 family of SoCs usually have one or more dual-core Arm Cortex
+R5F processor subsystems/clusters (R5FSS). The dual core cluster can be
+used either in a LockStep mode providing safety/fault tolerance features
+or in a Split mode providing two individual compute cores for doubling
+the compute capacity. These are used together with other processors
+present on the SoC to achieve various system level goals.
+
+R5F Sub-System Device Node:
+===========================
+Each Dual-Core R5F sub-system is represented as a single DTS node representing
+the cluster, with a pair of child DT nodes representing the individual R5F
+cores. Each node has a number of required or optional properties that enable
+the OS running on the host processor to perform the device management of the
+remote processor and to communicate with the remote processor.
+
+Required properties:
+--------------------
+The following are the mandatory properties:
+
+- compatible: Should be one of the following,
+ "ti,am654-r5fss" for R5F clusters/subsystems on
+ K3 AM65x SoCs
+ "ti,j721e-r5fss" for R5F clusters/subsystems on
+ K3 J721E SoCs
+- power-domains: Should contain a phandle to a PM domain provider node
+ and an args specifier containing the R5FSS device id
+ value. This property is as per the binding,
+ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+- #address-cells: Should be 1
+- #size-cells: Should be 1
+- ranges: Standard ranges definition providing translations for
+ R5F TCM address spaces
+
+Optional properties:
+--------------------
+- lockstep-mode: Configuration Mode for the Dual R5F cores within the R5F
+ cluster. Should be either a value of 1 (LockStep mode) or
+ 0 (Split mode), default is LockStep mode if omitted.
+
+
+R5F Processor Child Nodes:
+==========================
+The R5F Sub-System device node should define two R5F child nodes, each node
+representing a TI instantiation of the Arm Cortex R5F core. There are some
+specific integration differences for the IP like the usage of a Region Address
+Translator (RAT) for translating the larger SoC bus addresses into a 32-bit
+address space for the processor.
+
+Required properties:
+--------------------
+The following are the mandatory properties:
+
+- compatible: Should be one of the following,
+ "ti,am654-r5f" for the R5F cores in K3 AM65x SoCs
+ "ti,j721e-r5f" for the R5F cores in K3 J721E SOCs
+- reg: Should contain an entry for each value in 'reg-names'.
+ Each entry should have the memory region's start address
+ and the size of the region, the representation matching
+ the parent node's '#address-cells' and '#size-cells' values.
+- reg-names: Should contain strings with the following names, each
+ representing a specific internal memory region, and
+ should be defined in this order,
+ "atcm", "btcm"
+- ti,sci: Should be a phandle to the TI-SCI System Controller node
+- ti,sci-dev-id: Should contain the TI-SCI device id corresponding to the
+ R5F Core. Please refer to the corresponding System
+ Controller documentation for valid values for the R5F
+ cores.
+- ti,sci-proc-ids: Should contain 2 integer values. The first cell should
+ contain the TI-SCI processor id for the R5F core device
+ and the second cell should contain the TI-SCI host id to
+ which the processor control ownership should be
+ transferred to.
+- resets: Should contain the phandle to the reset controller node
+ managing the resets for this device, and a reset
+ specifier. Please refer to the following reset bindings
+ for the reset argument specifier,
+ Documentation/devicetree/bindings/reset/ti,sci-reset.txt
+ for AM65x and J721E SoCs
+
+Optional properties:
+--------------------
+The following properties are optional properties for each of the R5F cores:
+
+- atcm-enable: R5F core configuration mode dictating if ATCM should be
+ enabled. Should be either a value of 1 (enabled) or
+ 0 (disabled), default is disabled if omitted. R5F view
+ of ATCM dictated by loczrama property.
+- btcm-enable: R5F core configuration mode dictating if BTCM should be
+ enabled. Should be either a value of 1 (enabled) or
+ 0 (disabled), default is enabled if omitted. R5F view
+ of BTCM dictated by loczrama property.
+- loczrama: R5F core configuration mode dictating which TCM should
+ appear at address 0 (from core's view). Should be either
+ a value of 1 (ATCM at 0x0) or 0 (BTCM at 0x0), default
+ value is 1 if omitted.
+
+Example:
+--------
+1. AM654 SoC
+ /* AM65x remoteproc alias */
+ aliases {
+ remoteproc0 = &mcu_r5fss0_core0;
+ };
+
+ cbass_main: interconnect@100000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
+ <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
+ <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>;
+
+ cbass_mcu: interconnect@28380000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
+ <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
+ <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>; /* MCU SRAM */
+
+ /* AM65x MCU R5FSS node */
+ mcu_r5fss0: r5fss@41000000 {
+ compatible = "ti,am654-r5fss";
+ power-domains = <&k3_pds 129>;
+ lockstep-mode = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x41000000 0x00 0x41000000 0x20000>,
+ <0x41400000 0x00 0x41400000 0x20000>;
+
+ mcu_r5f0: r5f@41000000 {
+ compatible = "ti,am654-r5f";
+ reg = <0x41000000 0x00008000>,
+ <0x41010000 0x00008000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <159>;
+ ti,sci-proc-ids = <0x01 0xFF>;
+ resets = <&k3_reset 159 1>;
+ atcm-enable = <1>;
+ btcm-enable = <1>;
+ loczrama = <1>;
+ };
+
+ mcu_r5f1: r5f@41400000 {
+ compatible = "ti,am654-r5f";
+ reg = <0x41400000 0x00008000>,
+ <0x41410000 0x00008000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <245>;
+ ti,sci-proc-ids = <0x02 0xFF>;
+ resets = <&k3_reset 245 1>;
+ atcm-enable = <1>;
+ btcm-enable = <1>;
+ loczrama = <1>;
+ };
+ };
+ };
+ };
diff --git a/drivers/ata/ahci-pci.c b/drivers/ata/ahci-pci.c
index 1ca439d..11ec98b 100644
--- a/drivers/ata/ahci-pci.c
+++ b/drivers/ata/ahci-pci.c
@@ -35,6 +35,7 @@
static struct pci_device_id ahci_pci_supported[] = {
{ PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_SATA_AHCI, ~0) },
+ { PCI_DEVICE(0x1b21, 0x0611) },
{},
};
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 9a08575..21a89eb 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -548,6 +548,7 @@
{
struct ahci_ioports *pp = &(uc_priv->port[port]);
void __iomem *port_mmio = pp->port_mmio;
+ u64 dma_addr;
u32 port_status;
void __iomem *mem;
@@ -593,10 +594,12 @@
pp->cmd_tbl_sg =
(struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
- writel_with_flush((unsigned long)pp->cmd_slot,
- port_mmio + PORT_LST_ADDR);
-
- writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
+ dma_addr = (ulong)pp->cmd_slot;
+ writel_with_flush(dma_addr, port_mmio + PORT_LST_ADDR);
+ writel_with_flush(dma_addr >> 32, port_mmio + PORT_LST_ADDR_HI);
+ dma_addr = (ulong)pp->rx_fis;
+ writel_with_flush(dma_addr, port_mmio + PORT_FIS_ADDR);
+ writel_with_flush(dma_addr >> 32, port_mmio + PORT_FIS_ADDR_HI);
#ifdef CONFIG_SUNXI_AHCI
sunxi_dma_init(port_mmio);
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 95fe0ae..16d4237 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -95,6 +95,14 @@
help
Enable this to support the cgu clocks on Synopsys ARC HSDK
+config CLK_VERSAL
+ bool "Enable clock driver support for Versal"
+ depends on ARCH_VERSAL
+ select ZYNQMP_FIRMWARE
+ help
+ This clock driver adds support for clock realted settings for
+ Versal platform.
+
config CLK_VEXPRESS_OSC
bool "Enable driver for Arm Versatile Express OSC clock generators"
depends on CLK && VEXPRESS_CONFIG
@@ -113,6 +121,7 @@
config CLK_ZYNQMP
bool "Enable clock driver support for ZynqMP"
depends on ARCH_ZYNQMP
+ select ZYNQMP_FIRMWARE
help
This clock driver adds support for clock realted settings for
ZynqMP platform.
@@ -125,6 +134,13 @@
Enable the STM32 clock (RCC) driver. Enable support for
manipulating STM32MP1's on-SoC clocks.
+config CLK_CDCE9XX
+ bool "Enable CDCD9XX clock driver"
+ depends on CLK
+ help
+ Enable the clock synthesizer driver for CDCE913/925/937/949
+ series of chips.
+
source "drivers/clk/analogbits/Kconfig"
source "drivers/clk/at91/Kconfig"
source "drivers/clk/exynos/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 68aabe1..8de6777 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -43,3 +43,5 @@
obj-$(CONFIG_SANDBOX_CLK_CCF) += clk_sandbox_ccf.o
obj-$(CONFIG_STM32H7) += clk_stm32h7.o
obj-$(CONFIG_CLK_TI_SCI) += clk-ti-sci.o
+obj-$(CONFIG_CLK_VERSAL) += clk_versal.o
+obj-$(CONFIG_CLK_CDCE9XX) += clk-cdce9xx.o
diff --git a/drivers/clk/clk-cdce9xx.c b/drivers/clk/clk-cdce9xx.c
new file mode 100644
index 0000000..5d1489a
--- /dev/null
+++ b/drivers/clk/clk-cdce9xx.c
@@ -0,0 +1,254 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments CDCE913/925/937/949 clock synthesizer driver
+ *
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * Based on Linux kernel clk-cdce925.c.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <clk-uclass.h>
+#include <i2c.h>
+
+#define MAX_NUMBER_OF_PLLS 4
+#define MAX_NUMER_OF_OUTPUTS 9
+
+#define CDCE9XX_REG_GLOBAL1 0x01
+#define CDCE9XX_REG_Y1SPIPDIVH 0x02
+#define CDCE9XX_REG_PDIV1L 0x03
+#define CDCE9XX_REG_XCSEL 0x05
+
+#define CDCE9XX_PDIV1_H_MASK 0x3
+
+#define CDCE9XX_REG_PDIV(clk) (0x16 + (((clk) - 1) & 1) + \
+ ((clk) - 1) / 2 * 0x10)
+
+#define CDCE9XX_PDIV_MASK 0x7f
+
+#define CDCE9XX_BYTE_TRANSFER BIT(7)
+
+struct cdce9xx_chip_info {
+ int num_plls;
+ int num_outputs;
+};
+
+struct cdce9xx_clk_data {
+ struct udevice *i2c;
+ struct cdce9xx_chip_info *chip;
+ u32 xtal_rate;
+};
+
+static const struct cdce9xx_chip_info cdce913_chip_info = {
+ .num_plls = 1, .num_outputs = 3,
+};
+
+static const struct cdce9xx_chip_info cdce925_chip_info = {
+ .num_plls = 2, .num_outputs = 5,
+};
+
+static const struct cdce9xx_chip_info cdce937_chip_info = {
+ .num_plls = 3, .num_outputs = 7,
+};
+
+static const struct cdce9xx_chip_info cdce949_chip_info = {
+ .num_plls = 4, .num_outputs = 9,
+};
+
+static int cdce9xx_reg_read(struct udevice *dev, u8 addr, u8 *buf)
+{
+ struct cdce9xx_clk_data *data = dev_get_priv(dev);
+ int ret;
+
+ ret = dm_i2c_read(data->i2c, addr | CDCE9XX_BYTE_TRANSFER, buf, 1);
+ if (ret)
+ dev_err(dev, "%s: failed for addr:%x, ret:%d\n", __func__,
+ addr, ret);
+
+ return ret;
+}
+
+static int cdce9xx_reg_write(struct udevice *dev, u8 addr, u8 val)
+{
+ struct cdce9xx_clk_data *data = dev_get_priv(dev);
+ int ret;
+
+ ret = dm_i2c_write(data->i2c, addr | CDCE9XX_BYTE_TRANSFER, &val, 1);
+ if (ret)
+ dev_err(dev, "%s: failed for addr:%x, ret:%d\n", __func__,
+ addr, ret);
+
+ return ret;
+}
+
+static int cdce9xx_clk_of_xlate(struct clk *clk,
+ struct ofnode_phandle_args *args)
+{
+ struct cdce9xx_clk_data *data = dev_get_priv(clk->dev);
+
+ if (args->args_count != 1)
+ return -EINVAL;
+
+ if (args->args[0] > data->chip->num_outputs)
+ return -EINVAL;
+
+ clk->id = args->args[0];
+
+ return 0;
+}
+
+static int cdce9xx_clk_probe(struct udevice *dev)
+{
+ struct cdce9xx_clk_data *data = dev_get_priv(dev);
+ struct cdce9xx_chip_info *chip = (void *)dev_get_driver_data(dev);
+ int ret;
+ u32 val;
+ struct clk clk;
+
+ val = (u32)dev_read_addr_ptr(dev);
+
+ ret = i2c_get_chip(dev->parent, val, 1, &data->i2c);
+ if (ret) {
+ dev_err(dev, "I2C probe failed.\n");
+ return ret;
+ }
+
+ data->chip = chip;
+
+ ret = clk_get_by_index(dev, 0, &clk);
+ data->xtal_rate = clk_get_rate(&clk);
+
+ val = dev_read_u32_default(dev, "xtal-load-pf", -1);
+ if (val >= 0)
+ cdce9xx_reg_write(dev, CDCE9XX_REG_XCSEL, val << 3);
+
+ return 0;
+}
+
+static u16 cdce9xx_clk_get_pdiv(struct clk *clk)
+{
+ u8 val;
+ u16 pdiv;
+ int ret;
+
+ if (clk->id == 0) {
+ ret = cdce9xx_reg_read(clk->dev, CDCE9XX_REG_Y1SPIPDIVH, &val);
+ if (ret)
+ return 0;
+
+ pdiv = (val & CDCE9XX_PDIV1_H_MASK) << 8;
+
+ ret = cdce9xx_reg_read(clk->dev, CDCE9XX_REG_PDIV1L, &val);
+ if (ret)
+ return 0;
+
+ pdiv |= val;
+ } else {
+ ret = cdce9xx_reg_read(clk->dev, CDCE9XX_REG_PDIV(clk->id),
+ &val);
+ if (ret)
+ return 0;
+
+ pdiv = val & CDCE9XX_PDIV_MASK;
+ }
+
+ return pdiv;
+}
+
+static u32 cdce9xx_clk_get_parent_rate(struct clk *clk)
+{
+ struct cdce9xx_clk_data *data = dev_get_priv(clk->dev);
+
+ return data->xtal_rate;
+}
+
+static ulong cdce9xx_clk_get_rate(struct clk *clk)
+{
+ u32 parent_rate;
+ u16 pdiv;
+
+ parent_rate = cdce9xx_clk_get_parent_rate(clk);
+
+ pdiv = cdce9xx_clk_get_pdiv(clk);
+
+ return parent_rate / pdiv;
+}
+
+static ulong cdce9xx_clk_set_rate(struct clk *clk, ulong rate)
+{
+ u32 parent_rate;
+ int pdiv;
+ u32 diff;
+ u8 val;
+ int ret;
+
+ parent_rate = cdce9xx_clk_get_parent_rate(clk);
+
+ pdiv = parent_rate / rate;
+
+ diff = rate - parent_rate / pdiv;
+
+ if (rate - parent_rate / (pdiv + 1) < diff)
+ pdiv++;
+
+ if (clk->id == 0) {
+ ret = cdce9xx_reg_read(clk->dev, CDCE9XX_REG_Y1SPIPDIVH, &val);
+ if (ret)
+ return ret;
+
+ val &= ~CDCE9XX_PDIV1_H_MASK;
+
+ val |= (pdiv >> 8);
+
+ ret = cdce9xx_reg_write(clk->dev, CDCE9XX_REG_Y1SPIPDIVH, val);
+ if (ret)
+ return ret;
+
+ ret = cdce9xx_reg_write(clk->dev, CDCE9XX_REG_PDIV1L,
+ (pdiv & 0xff));
+ if (ret)
+ return ret;
+ } else {
+ ret = cdce9xx_reg_read(clk->dev, CDCE9XX_REG_PDIV(clk->id),
+ &val);
+ if (ret)
+ return ret;
+
+ val &= ~CDCE9XX_PDIV_MASK;
+
+ val |= pdiv;
+
+ ret = cdce9xx_reg_write(clk->dev, CDCE9XX_REG_PDIV(clk->id),
+ val);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id cdce9xx_clk_of_match[] = {
+ { .compatible = "ti,cdce913", .data = (u32)&cdce913_chip_info },
+ { .compatible = "ti,cdce925", .data = (u32)&cdce925_chip_info },
+ { .compatible = "ti,cdce937", .data = (u32)&cdce937_chip_info },
+ { .compatible = "ti,cdce949", .data = (u32)&cdce949_chip_info },
+ { /* sentinel */ },
+};
+
+static const struct clk_ops cdce9xx_clk_ops = {
+ .of_xlate = cdce9xx_clk_of_xlate,
+ .get_rate = cdce9xx_clk_get_rate,
+ .set_rate = cdce9xx_clk_set_rate,
+};
+
+U_BOOT_DRIVER(cdce9xx_clk) = {
+ .name = "cdce9xx-clk",
+ .id = UCLASS_CLK,
+ .of_match = cdce9xx_clk_of_match,
+ .probe = cdce9xx_clk_probe,
+ .priv_auto_alloc_size = sizeof(struct cdce9xx_clk_data),
+ .ops = &cdce9xx_clk_ops,
+};
diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c
new file mode 100644
index 0000000..df87645
--- /dev/null
+++ b/drivers/clk/clk_versal.c
@@ -0,0 +1,746 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Xilinx, Inc.
+ * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
+ */
+
+#include <common.h>
+#include <linux/bitops.h>
+#include <linux/bitfield.h>
+#include <malloc.h>
+#include <clk-uclass.h>
+#include <clk.h>
+#include <dm.h>
+#include <asm/arch/sys_proto.h>
+
+#define MAX_PARENT 100
+#define MAX_NODES 6
+#define MAX_NAME_LEN 50
+
+#define CLK_TYPE_SHIFT 2
+
+#define PM_API_PAYLOAD_LEN 3
+
+#define NA_PARENT 0xFFFFFFFF
+#define DUMMY_PARENT 0xFFFFFFFE
+
+#define CLK_TYPE_FIELD_LEN 4
+#define CLK_TOPOLOGY_NODE_OFFSET 16
+#define NODES_PER_RESP 3
+
+#define CLK_TYPE_FIELD_MASK 0xF
+#define CLK_FLAG_FIELD_MASK GENMASK(21, 8)
+#define CLK_TYPE_FLAG_FIELD_MASK GENMASK(31, 24)
+#define CLK_TYPE_FLAG2_FIELD_MASK GENMASK(7, 4)
+#define CLK_TYPE_FLAG_BITS 8
+
+#define CLK_PARENTS_ID_LEN 16
+#define CLK_PARENTS_ID_MASK 0xFFFF
+
+#define END_OF_TOPOLOGY_NODE 1
+#define END_OF_PARENTS 1
+
+#define CLK_VALID_MASK 0x1
+#define NODE_CLASS_SHIFT 26U
+#define NODE_SUBCLASS_SHIFT 20U
+#define NODE_TYPE_SHIFT 14U
+#define NODE_INDEX_SHIFT 0U
+
+#define CLK_GET_NAME_RESP_LEN 16
+#define CLK_GET_TOPOLOGY_RESP_WORDS 3
+#define CLK_GET_PARENTS_RESP_WORDS 3
+#define CLK_GET_ATTR_RESP_WORDS 1
+
+#define NODE_SUBCLASS_CLOCK_PLL 1
+#define NODE_SUBCLASS_CLOCK_OUT 2
+#define NODE_SUBCLASS_CLOCK_REF 3
+
+#define NODE_CLASS_CLOCK 2
+#define NODE_CLASS_MASK 0x3F
+
+#define CLOCK_NODE_TYPE_MUX 1
+#define CLOCK_NODE_TYPE_DIV 4
+#define CLOCK_NODE_TYPE_GATE 6
+
+enum pm_query_id {
+ PM_QID_INVALID,
+ PM_QID_CLOCK_GET_NAME,
+ PM_QID_CLOCK_GET_TOPOLOGY,
+ PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
+ PM_QID_CLOCK_GET_PARENTS,
+ PM_QID_CLOCK_GET_ATTRIBUTES,
+ PM_QID_PINCTRL_GET_NUM_PINS,
+ PM_QID_PINCTRL_GET_NUM_FUNCTIONS,
+ PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS,
+ PM_QID_PINCTRL_GET_FUNCTION_NAME,
+ PM_QID_PINCTRL_GET_FUNCTION_GROUPS,
+ PM_QID_PINCTRL_GET_PIN_GROUPS,
+ PM_QID_CLOCK_GET_NUM_CLOCKS,
+ PM_QID_CLOCK_GET_MAX_DIVISOR,
+};
+
+enum clk_type {
+ CLK_TYPE_OUTPUT,
+ CLK_TYPE_EXTERNAL,
+};
+
+struct clock_parent {
+ char name[MAX_NAME_LEN];
+ int id;
+ u32 flag;
+};
+
+struct clock_topology {
+ u32 type;
+ u32 flag;
+ u32 type_flag;
+};
+
+struct versal_clock {
+ char clk_name[MAX_NAME_LEN];
+ u32 valid;
+ enum clk_type type;
+ struct clock_topology node[MAX_NODES];
+ u32 num_nodes;
+ struct clock_parent parent[MAX_PARENT];
+ u32 num_parents;
+ u32 clk_id;
+};
+
+struct versal_clk_priv {
+ struct versal_clock *clk;
+};
+
+static ulong alt_ref_clk;
+static ulong pl_alt_ref_clk;
+static ulong ref_clk;
+
+struct versal_pm_query_data {
+ u32 qid;
+ u32 arg1;
+ u32 arg2;
+ u32 arg3;
+};
+
+static struct versal_clock *clock;
+static unsigned int clock_max_idx;
+
+#define PM_QUERY_DATA 35
+
+static int versal_pm_query(struct versal_pm_query_data qdata, u32 *ret_payload)
+{
+ struct pt_regs regs;
+
+ regs.regs[0] = PM_SIP_SVC | PM_QUERY_DATA;
+ regs.regs[1] = ((u64)qdata.arg1 << 32) | qdata.qid;
+ regs.regs[2] = ((u64)qdata.arg3 << 32) | qdata.arg2;
+
+ smc_call(®s);
+
+ if (ret_payload) {
+ ret_payload[0] = (u32)regs.regs[0];
+ ret_payload[1] = upper_32_bits(regs.regs[0]);
+ ret_payload[2] = (u32)regs.regs[1];
+ ret_payload[3] = upper_32_bits(regs.regs[1]);
+ ret_payload[4] = (u32)regs.regs[2];
+ }
+
+ return qdata.qid == PM_QID_CLOCK_GET_NAME ? 0 : regs.regs[0];
+}
+
+static inline int versal_is_valid_clock(u32 clk_id)
+{
+ if (clk_id >= clock_max_idx)
+ return -ENODEV;
+
+ return clock[clk_id].valid;
+}
+
+static int versal_get_clock_name(u32 clk_id, char *clk_name)
+{
+ int ret;
+
+ ret = versal_is_valid_clock(clk_id);
+ if (ret == 1) {
+ strncpy(clk_name, clock[clk_id].clk_name, MAX_NAME_LEN);
+ return 0;
+ }
+
+ return ret == 0 ? -EINVAL : ret;
+}
+
+static int versal_get_clock_type(u32 clk_id, u32 *type)
+{
+ int ret;
+
+ ret = versal_is_valid_clock(clk_id);
+ if (ret == 1) {
+ *type = clock[clk_id].type;
+ return 0;
+ }
+
+ return ret == 0 ? -EINVAL : ret;
+}
+
+static int versal_pm_clock_get_num_clocks(u32 *nclocks)
+{
+ struct versal_pm_query_data qdata = {0};
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+ int ret;
+
+ qdata.qid = PM_QID_CLOCK_GET_NUM_CLOCKS;
+
+ ret = versal_pm_query(qdata, ret_payload);
+ *nclocks = ret_payload[1];
+
+ return ret;
+}
+
+static int versal_pm_clock_get_name(u32 clock_id, char *name)
+{
+ struct versal_pm_query_data qdata = {0};
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+ int ret;
+
+ qdata.qid = PM_QID_CLOCK_GET_NAME;
+ qdata.arg1 = clock_id;
+
+ ret = versal_pm_query(qdata, ret_payload);
+ if (ret)
+ return ret;
+ memcpy(name, ret_payload, CLK_GET_NAME_RESP_LEN);
+
+ return 0;
+}
+
+static int versal_pm_clock_get_topology(u32 clock_id, u32 index, u32 *topology)
+{
+ struct versal_pm_query_data qdata = {0};
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+ int ret;
+
+ qdata.qid = PM_QID_CLOCK_GET_TOPOLOGY;
+ qdata.arg1 = clock_id;
+ qdata.arg2 = index;
+
+ ret = versal_pm_query(qdata, ret_payload);
+ memcpy(topology, &ret_payload[1], CLK_GET_TOPOLOGY_RESP_WORDS * 4);
+
+ return ret;
+}
+
+static int versal_pm_clock_get_parents(u32 clock_id, u32 index, u32 *parents)
+{
+ struct versal_pm_query_data qdata = {0};
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+ int ret;
+
+ qdata.qid = PM_QID_CLOCK_GET_PARENTS;
+ qdata.arg1 = clock_id;
+ qdata.arg2 = index;
+
+ ret = versal_pm_query(qdata, ret_payload);
+ memcpy(parents, &ret_payload[1], CLK_GET_PARENTS_RESP_WORDS * 4);
+
+ return ret;
+}
+
+static int versal_pm_clock_get_attributes(u32 clock_id, u32 *attr)
+{
+ struct versal_pm_query_data qdata = {0};
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+ int ret;
+
+ qdata.qid = PM_QID_CLOCK_GET_ATTRIBUTES;
+ qdata.arg1 = clock_id;
+
+ ret = versal_pm_query(qdata, ret_payload);
+ memcpy(attr, &ret_payload[1], CLK_GET_ATTR_RESP_WORDS * 4);
+
+ return ret;
+}
+
+static int __versal_clock_get_topology(struct clock_topology *topology,
+ u32 *data, u32 *nnodes)
+{
+ int i;
+
+ for (i = 0; i < PM_API_PAYLOAD_LEN; i++) {
+ if (!(data[i] & CLK_TYPE_FIELD_MASK))
+ return END_OF_TOPOLOGY_NODE;
+ topology[*nnodes].type = data[i] & CLK_TYPE_FIELD_MASK;
+ topology[*nnodes].flag = FIELD_GET(CLK_FLAG_FIELD_MASK,
+ data[i]);
+ topology[*nnodes].type_flag =
+ FIELD_GET(CLK_TYPE_FLAG_FIELD_MASK, data[i]);
+ topology[*nnodes].type_flag |=
+ FIELD_GET(CLK_TYPE_FLAG2_FIELD_MASK, data[i]) <<
+ CLK_TYPE_FLAG_BITS;
+ debug("topology type:0x%x, flag:0x%x, type_flag:0x%x\n",
+ topology[*nnodes].type, topology[*nnodes].flag,
+ topology[*nnodes].type_flag);
+ (*nnodes)++;
+ }
+
+ return 0;
+}
+
+static int versal_clock_get_topology(u32 clk_id,
+ struct clock_topology *topology,
+ u32 *num_nodes)
+{
+ int j, ret;
+ u32 pm_resp[PM_API_PAYLOAD_LEN] = {0};
+
+ *num_nodes = 0;
+ for (j = 0; j <= MAX_NODES; j += 3) {
+ ret = versal_pm_clock_get_topology(clock[clk_id].clk_id, j,
+ pm_resp);
+ if (ret)
+ return ret;
+ ret = __versal_clock_get_topology(topology, pm_resp, num_nodes);
+ if (ret == END_OF_TOPOLOGY_NODE)
+ return 0;
+ }
+
+ return 0;
+}
+
+static int __versal_clock_get_parents(struct clock_parent *parents, u32 *data,
+ u32 *nparent)
+{
+ int i;
+ struct clock_parent *parent;
+
+ for (i = 0; i < PM_API_PAYLOAD_LEN; i++) {
+ if (data[i] == NA_PARENT)
+ return END_OF_PARENTS;
+
+ parent = &parents[i];
+ parent->id = data[i] & CLK_PARENTS_ID_MASK;
+ if (data[i] == DUMMY_PARENT) {
+ strcpy(parent->name, "dummy_name");
+ parent->flag = 0;
+ } else {
+ parent->flag = data[i] >> CLK_PARENTS_ID_LEN;
+ if (versal_get_clock_name(parent->id, parent->name))
+ continue;
+ }
+ debug("parent name:%s\n", parent->name);
+ *nparent += 1;
+ }
+
+ return 0;
+}
+
+static int versal_clock_get_parents(u32 clk_id, struct clock_parent *parents,
+ u32 *num_parents)
+{
+ int j = 0, ret;
+ u32 pm_resp[PM_API_PAYLOAD_LEN] = {0};
+
+ *num_parents = 0;
+ do {
+ /* Get parents from firmware */
+ ret = versal_pm_clock_get_parents(clock[clk_id].clk_id, j,
+ pm_resp);
+ if (ret)
+ return ret;
+
+ ret = __versal_clock_get_parents(&parents[j], pm_resp,
+ num_parents);
+ if (ret == END_OF_PARENTS)
+ return 0;
+ j += PM_API_PAYLOAD_LEN;
+ } while (*num_parents <= MAX_PARENT);
+
+ return 0;
+}
+
+static u32 versal_clock_get_div(u32 clk_id)
+{
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+ u32 div;
+
+ versal_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
+ div = ret_payload[1];
+
+ return div;
+}
+
+static u32 versal_clock_set_div(u32 clk_id, u32 div)
+{
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+
+ versal_pm_request(PM_CLOCK_SETDIVIDER, clk_id, div, 0, 0, ret_payload);
+
+ return div;
+}
+
+static u64 versal_clock_ref(u32 clk_id)
+{
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+ int ref;
+
+ versal_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0, ret_payload);
+ ref = ret_payload[0];
+ if (!(ref & 1))
+ return ref_clk;
+ if (ref & 2)
+ return pl_alt_ref_clk;
+ return 0;
+}
+
+static u64 versal_clock_get_pll_rate(u32 clk_id)
+{
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+ u32 fbdiv;
+ u32 res;
+ u32 frac;
+ u64 freq;
+ u32 parent_rate, parent_id;
+ u32 id = clk_id & 0xFFF;
+
+ versal_pm_request(PM_CLOCK_GETSTATE, clk_id, 0, 0, 0, ret_payload);
+ res = ret_payload[1];
+ if (!res) {
+ printf("0%x PLL not enabled\n", clk_id);
+ return 0;
+ }
+
+ parent_id = clock[clock[id].parent[0].id].clk_id;
+ parent_rate = versal_clock_ref(parent_id);
+
+ versal_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
+ fbdiv = ret_payload[1];
+ versal_pm_request(PM_CLOCK_PLL_GETPARAM, clk_id, 2, 0, 0, ret_payload);
+ frac = ret_payload[1];
+
+ freq = (fbdiv * parent_rate) >> (1 << frac);
+
+ return freq;
+}
+
+static u32 versal_clock_mux(u32 clk_id)
+{
+ int i;
+ u32 id = clk_id & 0xFFF;
+
+ for (i = 0; i < clock[id].num_nodes; i++)
+ if (clock[id].node[i].type == CLOCK_NODE_TYPE_MUX)
+ return 1;
+
+ return 0;
+}
+
+static u32 versal_clock_get_parentid(u32 clk_id)
+{
+ u32 parent_id = 0;
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+ u32 id = clk_id & 0xFFF;
+
+ if (versal_clock_mux(clk_id)) {
+ versal_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0,
+ ret_payload);
+ parent_id = ret_payload[1];
+ }
+
+ debug("parent_id:0x%x\n", clock[clock[id].parent[parent_id].id].clk_id);
+ return clock[clock[id].parent[parent_id].id].clk_id;
+}
+
+static u32 versal_clock_gate(u32 clk_id)
+{
+ u32 id = clk_id & 0xFFF;
+ int i;
+
+ for (i = 0; i < clock[id].num_nodes; i++)
+ if (clock[id].node[i].type == CLOCK_NODE_TYPE_GATE)
+ return 1;
+
+ return 0;
+}
+
+static u32 versal_clock_div(u32 clk_id)
+{
+ int i;
+ u32 id = clk_id & 0xFFF;
+
+ for (i = 0; i < clock[id].num_nodes; i++)
+ if (clock[id].node[i].type == CLOCK_NODE_TYPE_DIV)
+ return 1;
+
+ return 0;
+}
+
+static u32 versal_clock_pll(u32 clk_id, u64 *clk_rate)
+{
+ if (((clk_id >> NODE_SUBCLASS_SHIFT) & NODE_CLASS_MASK) ==
+ NODE_SUBCLASS_CLOCK_PLL &&
+ ((clk_id >> NODE_CLASS_SHIFT) & NODE_CLASS_MASK) ==
+ NODE_CLASS_CLOCK) {
+ *clk_rate = versal_clock_get_pll_rate(clk_id);
+ return 1;
+ }
+
+ return 0;
+}
+
+static u64 versal_clock_calc(u32 clk_id)
+{
+ u32 parent_id;
+ u64 clk_rate;
+ u32 div;
+
+ if (versal_clock_pll(clk_id, &clk_rate))
+ return clk_rate;
+
+ parent_id = versal_clock_get_parentid(clk_id);
+ if (((parent_id >> NODE_SUBCLASS_SHIFT) &
+ NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_REF)
+ return versal_clock_ref(clk_id);
+
+ clk_rate = versal_clock_calc(parent_id);
+
+ if (versal_clock_div(clk_id)) {
+ div = versal_clock_get_div(clk_id);
+ clk_rate = DIV_ROUND_CLOSEST(clk_rate, div);
+ }
+
+ return clk_rate;
+}
+
+static int versal_clock_get_rate(u32 clk_id, u64 *clk_rate)
+{
+ if (((clk_id >> NODE_SUBCLASS_SHIFT) &
+ NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_REF)
+ *clk_rate = versal_clock_ref(clk_id);
+
+ if (versal_clock_pll(clk_id, clk_rate))
+ return 0;
+
+ if (((clk_id >> NODE_SUBCLASS_SHIFT) &
+ NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_OUT &&
+ ((clk_id >> NODE_CLASS_SHIFT) &
+ NODE_CLASS_MASK) == NODE_CLASS_CLOCK) {
+ if (!versal_clock_gate(clk_id))
+ return -EINVAL;
+ *clk_rate = versal_clock_calc(clk_id);
+ return 0;
+ }
+
+ return 0;
+}
+
+int soc_clk_dump(void)
+{
+ u64 clk_rate = 0;
+ u32 type, ret, i = 0;
+
+ printf("\n ****** VERSAL CLOCKS *****\n");
+
+ printf("alt_ref_clk:%ld pl_alt_ref_clk:%ld ref_clk:%ld\n",
+ alt_ref_clk, pl_alt_ref_clk, ref_clk);
+ for (i = 0; i < clock_max_idx; i++) {
+ debug("%s\n", clock[i].clk_name);
+ ret = versal_get_clock_type(i, &type);
+ if (ret || type != CLK_TYPE_OUTPUT)
+ continue;
+
+ ret = versal_clock_get_rate(clock[i].clk_id, &clk_rate);
+
+ if (ret != -EINVAL)
+ printf("clk: %s freq:%lld\n",
+ clock[i].clk_name, clk_rate);
+ }
+
+ return 0;
+}
+
+static void versal_get_clock_info(void)
+{
+ int i, ret;
+ u32 attr, type = 0, nodetype, subclass, class;
+
+ for (i = 0; i < clock_max_idx; i++) {
+ ret = versal_pm_clock_get_attributes(i, &attr);
+ if (ret)
+ continue;
+
+ clock[i].valid = attr & CLK_VALID_MASK;
+ clock[i].type = ((attr >> CLK_TYPE_SHIFT) & 0x1) ?
+ CLK_TYPE_EXTERNAL : CLK_TYPE_OUTPUT;
+ nodetype = (attr >> NODE_TYPE_SHIFT) & NODE_CLASS_MASK;
+ subclass = (attr >> NODE_SUBCLASS_SHIFT) & NODE_CLASS_MASK;
+ class = (attr >> NODE_CLASS_SHIFT) & NODE_CLASS_MASK;
+
+ clock[i].clk_id = (class << NODE_CLASS_SHIFT) |
+ (subclass << NODE_SUBCLASS_SHIFT) |
+ (nodetype << NODE_TYPE_SHIFT) |
+ (i << NODE_INDEX_SHIFT);
+
+ ret = versal_pm_clock_get_name(clock[i].clk_id,
+ clock[i].clk_name);
+ if (ret)
+ continue;
+ debug("clk name:%s, Valid:%d, type:%d, clk_id:0x%x\n",
+ clock[i].clk_name, clock[i].valid,
+ clock[i].type, clock[i].clk_id);
+ }
+
+ /* Get topology of all clock */
+ for (i = 0; i < clock_max_idx; i++) {
+ ret = versal_get_clock_type(i, &type);
+ if (ret || type != CLK_TYPE_OUTPUT)
+ continue;
+ debug("clk name:%s\n", clock[i].clk_name);
+ ret = versal_clock_get_topology(i, clock[i].node,
+ &clock[i].num_nodes);
+ if (ret)
+ continue;
+
+ ret = versal_clock_get_parents(i, clock[i].parent,
+ &clock[i].num_parents);
+ if (ret)
+ continue;
+ }
+}
+
+int versal_clock_setup(void)
+{
+ int ret;
+
+ ret = versal_pm_clock_get_num_clocks(&clock_max_idx);
+ if (ret)
+ return ret;
+
+ debug("%s, clock_max_idx:0x%x\n", __func__, clock_max_idx);
+ clock = calloc(clock_max_idx, sizeof(*clock));
+ if (!clock)
+ return -ENOMEM;
+
+ versal_get_clock_info();
+
+ return 0;
+}
+
+static int versal_clock_get_freq_by_name(char *name, struct udevice *dev,
+ ulong *freq)
+{
+ struct clk clk;
+ int ret;
+
+ ret = clk_get_by_name(dev, name, &clk);
+ if (ret < 0) {
+ dev_err(dev, "failed to get %s\n", name);
+ return ret;
+ }
+
+ *freq = clk_get_rate(&clk);
+ if (IS_ERR_VALUE(*freq)) {
+ dev_err(dev, "failed to get rate %s\n", name);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int versal_clk_probe(struct udevice *dev)
+{
+ int ret;
+ struct versal_clk_priv *priv = dev_get_priv(dev);
+
+ debug("%s\n", __func__);
+
+ ret = versal_clock_get_freq_by_name("alt_ref_clk", dev, &alt_ref_clk);
+ if (ret < 0)
+ return -EINVAL;
+
+ ret = versal_clock_get_freq_by_name("pl_alt_ref_clk",
+ dev, &pl_alt_ref_clk);
+ if (ret < 0)
+ return -EINVAL;
+
+ ret = versal_clock_get_freq_by_name("ref_clk", dev, &ref_clk);
+ if (ret < 0)
+ return -EINVAL;
+
+ versal_clock_setup();
+
+ priv->clk = clock;
+
+ return ret;
+}
+
+static ulong versal_clk_get_rate(struct clk *clk)
+{
+ struct versal_clk_priv *priv = dev_get_priv(clk->dev);
+ u32 id = clk->id;
+ u32 clk_id;
+ u64 clk_rate = 0;
+
+ debug("%s\n", __func__);
+
+ clk_id = priv->clk[id].clk_id;
+
+ versal_clock_get_rate(clk_id, &clk_rate);
+
+ return clk_rate;
+}
+
+static ulong versal_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct versal_clk_priv *priv = dev_get_priv(clk->dev);
+ u32 id = clk->id;
+ u32 clk_id;
+ u64 clk_rate = 0;
+ u32 div;
+ int ret;
+
+ debug("%s\n", __func__);
+
+ clk_id = priv->clk[id].clk_id;
+
+ ret = versal_clock_get_rate(clk_id, &clk_rate);
+ if (ret) {
+ printf("Clock is not a Gate:0x%x\n", clk_id);
+ return 0;
+ }
+
+ do {
+ if (versal_clock_div(clk_id)) {
+ div = versal_clock_get_div(clk_id);
+ clk_rate *= div;
+ div = DIV_ROUND_CLOSEST(clk_rate, rate);
+ versal_clock_set_div(clk_id, div);
+ debug("%s, div:%d, newrate:%lld\n", __func__,
+ div, DIV_ROUND_CLOSEST(clk_rate, div));
+ return DIV_ROUND_CLOSEST(clk_rate, div);
+ }
+ clk_id = versal_clock_get_parentid(clk_id);
+ } while (((clk_id >> NODE_SUBCLASS_SHIFT) &
+ NODE_CLASS_MASK) != NODE_SUBCLASS_CLOCK_REF);
+
+ printf("Clock didn't has Divisors:0x%x\n", priv->clk[id].clk_id);
+
+ return clk_rate;
+}
+
+static struct clk_ops versal_clk_ops = {
+ .set_rate = versal_clk_set_rate,
+ .get_rate = versal_clk_get_rate,
+};
+
+static const struct udevice_id versal_clk_ids[] = {
+ { .compatible = "xlnx,versal-clk" },
+ { }
+};
+
+U_BOOT_DRIVER(versal_clk) = {
+ .name = "versal-clk",
+ .id = UCLASS_CLK,
+ .of_match = versal_clk_ids,
+ .probe = versal_clk_probe,
+ .ops = &versal_clk_ops,
+ .priv_auto_alloc_size = sizeof(struct versal_clk_priv),
+};
diff --git a/drivers/core/device.c b/drivers/core/device.c
index 84f0f0f..ce66c72 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -568,6 +568,17 @@
return -ENODEV;
}
+int device_get_child_count(struct udevice *parent)
+{
+ struct udevice *dev;
+ int count = 0;
+
+ list_for_each_entry(dev, &parent->child_head, sibling_node)
+ count++;
+
+ return count;
+}
+
int device_find_child_by_seq(struct udevice *parent, int seq_or_req_seq,
bool find_req_seq, struct udevice **devp)
{
diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig
index 873bc8c..b70a206 100644
--- a/drivers/firmware/Kconfig
+++ b/drivers/firmware/Kconfig
@@ -26,3 +26,13 @@
This protocol library is used by client drivers to use the features
provided by the system controller.
+
+config ZYNQMP_FIRMWARE
+ bool "ZynqMP Firmware interface"
+ select FIRMWARE
+ help
+ Firmware interface driver is used by different
+ drivers to communicate with the firmware for
+ various platform management services.
+ Say yes to enable ZynqMP firmware interface driver.
+ If in doubt, say N.
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index 6c3e129..a0c250a 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -2,3 +2,4 @@
obj-$(CONFIG_$(SPL_)ARM_PSCI_FW) += psci.o
obj-$(CONFIG_TI_SCI_PROTOCOL) += ti_sci.o
obj-$(CONFIG_SANDBOX) += firmware-sandbox.o
+obj-$(CONFIG_ZYNQMP_FIRMWARE) += firmware-zynqmp.o
diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c
new file mode 100644
index 0000000..15e82ac
--- /dev/null
+++ b/drivers/firmware/firmware-zynqmp.c
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Zynq MPSoC Firmware driver
+ *
+ * Copyright (C) 2018-2019 Xilinx, Inc.
+ */
+
+#include <common.h>
+#include <dm.h>
+
+#if defined(CONFIG_ZYNQMP_IPI)
+#include <mailbox.h>
+#include <zynqmp_firmware.h>
+#include <asm/arch/sys_proto.h>
+
+#define PMUFW_PAYLOAD_ARG_CNT 8
+
+struct zynqmp_power {
+ struct mbox_chan tx_chan;
+ struct mbox_chan rx_chan;
+} zynqmp_power;
+
+static int ipi_req(const u32 *req, size_t req_len, u32 *res, size_t res_maxlen)
+{
+ struct zynqmp_ipi_msg msg;
+ int ret;
+
+ if (req_len > PMUFW_PAYLOAD_ARG_CNT ||
+ res_maxlen > PMUFW_PAYLOAD_ARG_CNT)
+ return -EINVAL;
+
+ if (!(zynqmp_power.tx_chan.dev) || !(&zynqmp_power.rx_chan.dev))
+ return -EINVAL;
+
+ msg.buf = (u32 *)req;
+ msg.len = req_len;
+ ret = mbox_send(&zynqmp_power.tx_chan, &msg);
+ if (ret) {
+ debug("%s: Sending message failed\n", __func__);
+ return ret;
+ }
+
+ msg.buf = res;
+ msg.len = res_maxlen;
+ ret = mbox_recv(&zynqmp_power.rx_chan, &msg, 100);
+ if (ret)
+ debug("%s: Receiving message failed\n", __func__);
+
+ return ret;
+}
+
+static int send_req(const u32 *req, size_t req_len, u32 *res, size_t res_maxlen)
+{
+ if (IS_ENABLED(CONFIG_SPL_BUILD))
+ return ipi_req(req, req_len, res, res_maxlen);
+
+ return invoke_smc(req[0] + PM_SIP_SVC, 0, 0, 0, 0, res);
+}
+
+unsigned int zynqmp_firmware_version(void)
+{
+ int ret;
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+ static u32 pm_api_version = ZYNQMP_PM_VERSION_INVALID;
+
+ /*
+ * Get PMU version only once and later
+ * just return stored values instead of
+ * asking PMUFW again.
+ **/
+ if (pm_api_version == ZYNQMP_PM_VERSION_INVALID) {
+ const u32 request[] = { PM_GET_API_VERSION };
+
+ ret = send_req(request, ARRAY_SIZE(request), ret_payload, 2);
+ if (ret)
+ panic("PMUFW is not found - Please load it!\n");
+
+ pm_api_version = ret_payload[1];
+ if (pm_api_version < ZYNQMP_PM_VERSION)
+ panic("PMUFW version error. Expected: v%d.%d\n",
+ ZYNQMP_PM_VERSION_MAJOR, ZYNQMP_PM_VERSION_MINOR);
+ }
+
+ return pm_api_version;
+};
+
+/**
+ * Send a configuration object to the PMU firmware.
+ *
+ * @cfg_obj: Pointer to the configuration object
+ * @size: Size of @cfg_obj in bytes
+ */
+void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size)
+{
+ const u32 request[] = {
+ PM_SET_CONFIGURATION,
+ (u32)((u64)cfg_obj)
+ };
+ u32 response;
+ int err;
+
+ printf("Loading new PMUFW cfg obj (%ld bytes)\n", size);
+
+ err = send_req(request, ARRAY_SIZE(request), &response, 1);
+ if (err)
+ panic("Cannot load PMUFW configuration object (%d)\n", err);
+ if (response != 0)
+ panic("PMUFW returned 0x%08x status!\n", response);
+}
+
+static int zynqmp_power_probe(struct udevice *dev)
+{
+ int ret = 0;
+
+ debug("%s, (dev=%p)\n", __func__, dev);
+
+ ret = mbox_get_by_name(dev, "tx", &zynqmp_power.tx_chan);
+ if (ret) {
+ debug("%s, cannot tx mailbox\n", __func__);
+ return ret;
+ }
+
+ ret = mbox_get_by_name(dev, "rx", &zynqmp_power.rx_chan);
+ if (ret) {
+ debug("%s, cannot rx mailbox\n", __func__);
+ return ret;
+ }
+
+ ret = zynqmp_firmware_version();
+ printf("PMUFW:\tv%d.%d\n",
+ ret >> ZYNQMP_PM_VERSION_MAJOR_SHIFT,
+ ret & ZYNQMP_PM_VERSION_MINOR_MASK);
+
+ return 0;
+};
+
+static const struct udevice_id zynqmp_power_ids[] = {
+ { .compatible = "xlnx,zynqmp-power" },
+ { }
+};
+
+U_BOOT_DRIVER(zynqmp_power) = {
+ .name = "zynqmp_power",
+ .id = UCLASS_FIRMWARE,
+ .of_match = zynqmp_power_ids,
+ .probe = zynqmp_power_probe,
+};
+#endif
+
+static const struct udevice_id zynqmp_firmware_ids[] = {
+ { .compatible = "xlnx,zynqmp-firmware" },
+ { .compatible = "xlnx,versal-firmware"},
+ { }
+};
+
+U_BOOT_DRIVER(zynqmp_firmware) = {
+ .id = UCLASS_FIRMWARE,
+ .name = "zynqmp-firmware",
+ .probe = dm_scan_fdt_dev,
+ .of_match = zynqmp_firmware_ids,
+};
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 105a299..fe398a1 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -56,6 +56,15 @@
Enable FPGA driver for loading bitstream in BIT and BIN format
on Xilinx Zynq UltraScale+ (ZynqMP) device.
+config FPGA_VERSALPL
+ bool "Enable Xilinx FPGA driver for Versal"
+ depends on FPGA_XILINX
+ help
+ Enable FPGA driver for loading bitstream in PDI format on Xilinx
+ Versal device. PDI is a new programmable device image format for
+ Versal. The bitstream will only be generated as PDI for Versal
+ platform.
+
config FPGA_SPARTAN3
bool "Enable Spartan3 FPGA driver"
depends on FPGA_XILINX
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 5a778c1..04e6480 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -6,6 +6,7 @@
obj-y += fpga.o
obj-$(CONFIG_FPGA_SPARTAN2) += spartan2.o
obj-$(CONFIG_FPGA_SPARTAN3) += spartan3.o
+obj-$(CONFIG_FPGA_VERSALPL) += versalpl.o
obj-$(CONFIG_FPGA_VIRTEX2) += virtex2.o
obj-$(CONFIG_FPGA_ZYNQPL) += zynqpl.o
obj-$(CONFIG_FPGA_ZYNQMPPL) += zynqmppl.o
diff --git a/drivers/fpga/versalpl.c b/drivers/fpga/versalpl.c
new file mode 100644
index 0000000..69617a9
--- /dev/null
+++ b/drivers/fpga/versalpl.c
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2019, Xilinx, Inc,
+ * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <memalign.h>
+#include <versalpl.h>
+
+static ulong versal_align_dma_buffer(ulong *buf, u32 len)
+{
+ ulong *new_buf;
+
+ if ((ulong)buf != ALIGN((ulong)buf, ARCH_DMA_MINALIGN)) {
+ new_buf = (ulong *)ALIGN((ulong)buf, ARCH_DMA_MINALIGN);
+ memcpy(new_buf, buf, len);
+ buf = new_buf;
+ }
+
+ return (ulong)buf;
+}
+
+static int versal_load(xilinx_desc *desc, const void *buf, size_t bsize,
+ bitstream_type bstype)
+{
+ ulong bin_buf;
+ int ret;
+ u32 buf_lo, buf_hi;
+ u32 ret_payload[5];
+
+ bin_buf = versal_align_dma_buffer((ulong *)buf, bsize);
+
+ debug("%s called!\n", __func__);
+ flush_dcache_range(bin_buf, bin_buf + bsize);
+
+ buf_lo = lower_32_bits(bin_buf);
+ buf_hi = upper_32_bits(bin_buf);
+
+ ret = versal_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
+ buf_hi, 0, ret_payload);
+ if (ret)
+ puts("PL FPGA LOAD fail\n");
+
+ return ret;
+}
+
+struct xilinx_fpga_op versal_op = {
+ .load = versal_load,
+};
diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c
index f513550..4b0334b 100644
--- a/drivers/fpga/xilinx.c
+++ b/drivers/fpga/xilinx.c
@@ -226,7 +226,10 @@
case xilinx_zynqmp:
printf("ZynqMP PL\n");
break;
- /* Add new family types here */
+ case xilinx_versal:
+ printf("Versal PL\n");
+ break;
+ /* Add new family types here */
default:
printf ("Unknown family type, %d\n", desc->family);
}
@@ -257,6 +260,9 @@
case csu_dma:
printf("csu_dma configuration interface (ZynqMP)\n");
break;
+ case cfi:
+ printf("CFI configuration interface (Versal)\n");
+ break;
/* Add new interface types here */
default:
printf ("Unsupported interface type, %d\n", desc->iface);
diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c
index 22bfdd8..c267027 100644
--- a/drivers/fpga/zynqmppl.c
+++ b/drivers/fpga/zynqmppl.c
@@ -8,6 +8,7 @@
#include <console.h>
#include <common.h>
#include <zynqmppl.h>
+#include <zynqmp_firmware.h>
#include <linux/sizes.h>
#include <asm/arch/sys_proto.h>
#include <memalign.h>
@@ -151,9 +152,9 @@
buf = new_buf;
} else if ((swap != SWAP_DONE) &&
- (zynqmp_pmufw_version() <= PMUFW_V1_0)) {
+ (zynqmp_firmware_version() <= PMUFW_V1_0)) {
/* For bitstream which are aligned */
- u32 *new_buf = (u32 *)buf;
+ new_buf = buf;
printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
swap);
@@ -204,7 +205,7 @@
u32 ret_payload[PAYLOAD_ARG_CNT];
bool xilfpga_old = false;
- if (zynqmp_pmufw_version() <= PMUFW_V1_0) {
+ if (zynqmp_firmware_version() <= PMUFW_V1_0) {
puts("WARN: PMUFW v1.0 or less is detected\n");
puts("WARN: Not all bitstream formats are supported\n");
puts("WARN: Please upgrade PMUFW\n");
diff --git a/drivers/gpio/zynq_gpio.c b/drivers/gpio/zynq_gpio.c
index 55a5cba..a760c5b 100644
--- a/drivers/gpio/zynq_gpio.c
+++ b/drivers/gpio/zynq_gpio.c
@@ -292,7 +292,7 @@
writel(reg, platdata->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
/* set the state of the pin */
- gpio_set_value(gpio, value);
+ zynq_gpio_set_value(dev, gpio, value);
return 0;
}
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index 11bf552..85c2a82 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -41,4 +41,10 @@
Select this driver if your platform has support for this hardware
block.
+config ZYNQMP_IPI
+ bool "Xilinx ZynqMP IPI controller support"
+ depends on DM_MAILBOX && ARCH_ZYNQMP
+ help
+ This enables support for the Xilinx ZynqMP Inter Processor Interrupt
+ communication controller.
endmenu
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index a753cc4..d2ace8c 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -9,3 +9,4 @@
obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o
obj-$(CONFIG_TEGRA_HSP) += tegra-hsp.o
obj-$(CONFIG_K3_SEC_PROXY) += k3-sec-proxy.o
+obj-$(CONFIG_ZYNQMP_IPI) += zynqmp-ipi.o
diff --git a/drivers/mailbox/mailbox-uclass.c b/drivers/mailbox/mailbox-uclass.c
index 1b4a586..9fdb627 100644
--- a/drivers/mailbox/mailbox-uclass.c
+++ b/drivers/mailbox/mailbox-uclass.c
@@ -49,7 +49,16 @@
if (ret) {
debug("%s: uclass_get_device_by_of_offset failed: %d\n",
__func__, ret);
- return ret;
+
+ /* Test with parent node */
+ ret = uclass_get_device_by_ofnode(UCLASS_MAILBOX,
+ ofnode_get_parent(args.node),
+ &dev_mbox);
+ if (ret) {
+ debug("%s: mbox node from parent failed: %d\n",
+ __func__, ret);
+ return ret;
+ };
}
ops = mbox_dev_ops(dev_mbox);
@@ -63,7 +72,8 @@
return ret;
}
- ret = ops->request(chan);
+ if (ops->request)
+ ret = ops->request(chan);
if (ret) {
debug("ops->request() failed: %d\n", ret);
return ret;
@@ -94,7 +104,10 @@
debug("%s(chan=%p)\n", __func__, chan);
- return ops->free(chan);
+ if (ops->free)
+ return ops->free(chan);
+
+ return 0;
}
int mbox_send(struct mbox_chan *chan, const void *data)
diff --git a/drivers/mailbox/zynqmp-ipi.c b/drivers/mailbox/zynqmp-ipi.c
new file mode 100644
index 0000000..c181a7b
--- /dev/null
+++ b/drivers/mailbox/zynqmp-ipi.c
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx Zynq MPSoC Mailbox driver
+ *
+ * Copyright (C) 2018-2019 Xilinx, Inc.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <mailbox-uclass.h>
+#include <mach/sys_proto.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+#include <wait_bit.h>
+
+/* IPI bitmasks, register base */
+/* TODO: move reg base to DT */
+#define IPI_BIT_MASK_PMU0 0x10000
+#define IPI_INT_REG_BASE_APU 0xFF300000
+
+struct ipi_int_regs {
+ u32 trig; /* 0x0 */
+ u32 obs; /* 0x4 */
+ u32 ist; /* 0x8 */
+ u32 imr; /* 0xC */
+ u32 ier; /* 0x10 */
+ u32 idr; /* 0x14 */
+};
+
+#define ipi_int_apu ((struct ipi_int_regs *)IPI_INT_REG_BASE_APU)
+
+struct zynqmp_ipi {
+ void __iomem *local_req_regs;
+ void __iomem *local_res_regs;
+ void __iomem *remote_req_regs;
+ void __iomem *remote_res_regs;
+};
+
+static int zynqmp_ipi_send(struct mbox_chan *chan, const void *data)
+{
+ const struct zynqmp_ipi_msg *msg = (struct zynqmp_ipi_msg *)data;
+ struct zynqmp_ipi *zynqmp = dev_get_priv(chan->dev);
+ u32 ret;
+ u32 *mbx = (u32 *)zynqmp->local_req_regs;
+
+ for (size_t i = 0; i < msg->len; i++)
+ writel(msg->buf[i], &mbx[i]);
+
+ /* Write trigger interrupt */
+ writel(IPI_BIT_MASK_PMU0, &ipi_int_apu->trig);
+
+ /* Wait until observation bit is cleared */
+ ret = wait_for_bit_le32(&ipi_int_apu->obs, IPI_BIT_MASK_PMU0, false,
+ 100, false);
+
+ debug("%s, send %ld bytes\n", __func__, msg->len);
+ return ret;
+};
+
+static int zynqmp_ipi_recv(struct mbox_chan *chan, void *data)
+{
+ struct zynqmp_ipi_msg *msg = (struct zynqmp_ipi_msg *)data;
+ struct zynqmp_ipi *zynqmp = dev_get_priv(chan->dev);
+ u32 *mbx = (u32 *)zynqmp->local_res_regs;
+
+ for (size_t i = 0; i < msg->len; i++)
+ msg->buf[i] = readl(&mbx[i]);
+
+ debug("%s, recv %ld bytes\n", __func__, msg->len);
+ return 0;
+};
+
+static int zynqmp_ipi_probe(struct udevice *dev)
+{
+ struct zynqmp_ipi *zynqmp = dev_get_priv(dev);
+ struct resource res;
+ ofnode node;
+
+ debug("%s(dev=%p)\n", __func__, dev);
+
+ /* Get subnode where the regs are defined */
+ /* Note IPI mailbox node needs to be the first one in DT */
+ node = ofnode_first_subnode(dev_ofnode(dev));
+
+ if (ofnode_read_resource_byname(node, "local_request_region", &res)) {
+ dev_err(dev, "No reg property for local_request_region\n");
+ return -EINVAL;
+ };
+ zynqmp->local_req_regs = devm_ioremap(dev, res.start,
+ (res.start - res.end));
+
+ if (ofnode_read_resource_byname(node, "local_response_region", &res)) {
+ dev_err(dev, "No reg property for local_response_region\n");
+ return -EINVAL;
+ };
+ zynqmp->local_res_regs = devm_ioremap(dev, res.start,
+ (res.start - res.end));
+
+ if (ofnode_read_resource_byname(node, "remote_request_region", &res)) {
+ dev_err(dev, "No reg property for remote_request_region\n");
+ return -EINVAL;
+ };
+ zynqmp->remote_req_regs = devm_ioremap(dev, res.start,
+ (res.start - res.end));
+
+ if (ofnode_read_resource_byname(node, "remote_response_region", &res)) {
+ dev_err(dev, "No reg property for remote_response_region\n");
+ return -EINVAL;
+ };
+ zynqmp->remote_res_regs = devm_ioremap(dev, res.start,
+ (res.start - res.end));
+
+ return 0;
+};
+
+static const struct udevice_id zynqmp_ipi_ids[] = {
+ { .compatible = "xlnx,zynqmp-ipi-mailbox" },
+ { }
+};
+
+struct mbox_ops zynqmp_ipi_mbox_ops = {
+ .send = zynqmp_ipi_send,
+ .recv = zynqmp_ipi_recv,
+};
+
+U_BOOT_DRIVER(zynqmp_ipi) = {
+ .name = "zynqmp-ipi",
+ .id = UCLASS_MAILBOX,
+ .of_match = zynqmp_ipi_ids,
+ .probe = zynqmp_ipi_probe,
+ .priv_auto_alloc_size = sizeof(struct zynqmp_ipi),
+ .ops = &zynqmp_ipi_mbox_ops,
+};
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 7361bca..2bc9d8d 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -634,6 +634,12 @@
help
Set the minimum frequency of the controller.
+config ZYNQ_HISPD_BROKEN
+ bool "High speed broken for Zynq SDHCI controller"
+ depends on MMC_SDHCI_ZYNQ
+ help
+ Set if high speed mode is broken.
+
config MMC_SUNXI
bool "Allwinner sunxi SD/MMC Host Controller support"
depends on ARCH_SUNXI && !UART0_PORT_F
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index 1793a3f..7cd5516 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -219,23 +219,10 @@
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct sdhci_host *host = dev_get_priv(dev);
struct mmc_config *cfg = &plat->cfg;
- struct power_domain sdhci_pwrdmn;
struct clk clk;
unsigned long clock;
int ret;
- ret = power_domain_get_by_index(dev, &sdhci_pwrdmn, 0);
- if (!ret) {
- ret = power_domain_on(&sdhci_pwrdmn);
- if (ret) {
- dev_err(dev, "Power domain on failed (%d)\n", ret);
- return ret;
- }
- } else if (ret != -ENOENT && ret != -ENODEV && ret != -ENOSYS) {
- dev_err(dev, "failed to get power domain (%d)\n", ret);
- return ret;
- }
-
ret = clk_get_by_index(dev, 0, &clk);
if (ret) {
dev_err(dev, "failed to get clock\n");
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 3225a7a..529eec9 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -190,7 +190,7 @@
}
#endif
-#if defined(CONFIG_DM_MMC) && defined(CONFIG_ARCH_ZYNQMP)
+#if defined(CONFIG_ARCH_ZYNQMP)
const struct sdhci_ops arasan_ops = {
.platform_execute_tuning = &arasan_sdhci_execute_tuning,
.set_delay = &arasan_sdhci_set_tapdelay,
@@ -266,7 +266,7 @@
priv->host->name = dev->name;
-#if defined(CONFIG_DM_MMC) && defined(CONFIG_ARCH_ZYNQMP)
+#if defined(CONFIG_ARCH_ZYNQMP)
priv->host->ops = &arasan_ops;
#endif
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 2a3da06..30bd8e7 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -228,6 +228,13 @@
config PHY_XILINX
bool "Xilinx Ethernet PHYs support"
+config PHY_XILINX_GMII2RGMII
+ bool "Xilinx GMII to RGMII Ethernet PHYs support"
+ help
+ This adds support for Xilinx GMII to RGMII IP core. This IP acts
+ as bridge between MAC connected over GMII and external phy that
+ is connected over RGMII interface.
+
config PHY_FIXED
bool "Fixed-Link PHY"
depends on DM_ETH
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 555da83..76b6197 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -27,6 +27,7 @@
obj-$(CONFIG_PHY_TERANETICS) += teranetics.o
obj-$(CONFIG_PHY_TI) += ti.o
obj-$(CONFIG_PHY_XILINX) += xilinx_phy.o
+obj-$(CONFIG_PHY_XILINX_GMII2RGMII) += xilinx_gmii2rgmii.o
obj-$(CONFIG_PHY_VITESSE) += vitesse.o
obj-$(CONFIG_PHY_MSCC) += mscc.o
obj-$(CONFIG_PHY_FIXED) += fixed.o
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index ae37dd6..f2d17aa 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -458,6 +458,11 @@
.shutdown = genphy_shutdown,
};
+int genphy_init(void)
+{
+ return phy_register(&genphy_driver);
+}
+
static LIST_HEAD(phy_drivers);
int phy_init(void)
@@ -540,6 +545,11 @@
#ifdef CONFIG_PHY_FIXED
phy_fixed_init();
#endif
+#ifdef CONFIG_PHY_XILINX_GMII2RGMII
+ phy_xilinx_gmii2rgmii_init();
+#endif
+ genphy_init();
+
return 0;
}
@@ -911,6 +921,41 @@
debug("%s connected to %s\n", dev->name, phydev->drv->name);
}
+#ifdef CONFIG_PHY_XILINX_GMII2RGMII
+#ifdef CONFIG_DM_ETH
+static struct phy_device *phy_connect_gmii2rgmii(struct mii_dev *bus,
+ struct udevice *dev,
+ phy_interface_t interface)
+#else
+static struct phy_device *phy_connect_gmii2rgmii(struct mii_dev *bus,
+ struct eth_device *dev,
+ phy_interface_t interface)
+#endif
+{
+ struct phy_device *phydev = NULL;
+ int sn = dev_of_offset(dev);
+ int off;
+
+ while (sn > 0) {
+ off = fdt_node_offset_by_compatible(gd->fdt_blob, sn,
+ "xlnx,gmii-to-rgmii-1.0");
+ if (off > 0) {
+ phydev = phy_device_create(bus, off,
+ PHY_GMII2RGMII_ID, false,
+ interface);
+ break;
+ }
+ if (off == -FDT_ERR_NOTFOUND)
+ sn = fdt_first_subnode(gd->fdt_blob, sn);
+ else
+ printf("%s: Error finding compat string:%d\n",
+ __func__, off);
+ }
+
+ return phydev;
+}
+#endif
+
#ifdef CONFIG_PHY_FIXED
#ifdef CONFIG_DM_ETH
static struct phy_device *phy_connect_fixed(struct mii_dev *bus,
@@ -957,6 +1002,10 @@
#ifdef CONFIG_PHY_FIXED
phydev = phy_connect_fixed(bus, dev, interface);
#endif
+#ifdef CONFIG_PHY_XILINX_GMII2RGMII
+ if (!phydev)
+ phydev = phy_connect_gmii2rgmii(bus, dev, interface);
+#endif
if (!phydev)
phydev = phy_find_by_mask(bus, mask, interface);
diff --git a/drivers/net/phy/xilinx_gmii2rgmii.c b/drivers/net/phy/xilinx_gmii2rgmii.c
new file mode 100644
index 0000000..8c20da2
--- /dev/null
+++ b/drivers/net/phy/xilinx_gmii2rgmii.c
@@ -0,0 +1,144 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx GMII2RGMII phy driver
+ *
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+
+#include <dm.h>
+#include <phy.h>
+#include <config.h>
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ZYNQ_GMII2RGMII_REG 0x10
+#define ZYNQ_GMII2RGMII_SPEED_MASK (BMCR_SPEED1000 | BMCR_SPEED100)
+
+static int xilinxgmiitorgmii_config(struct phy_device *phydev)
+{
+ struct phy_device *ext_phydev = phydev->priv;
+
+ debug("%s\n", __func__);
+ if (ext_phydev->drv->config)
+ ext_phydev->drv->config(ext_phydev);
+
+ return 0;
+}
+
+static int xilinxgmiitorgmii_extread(struct phy_device *phydev, int addr,
+ int devaddr, int regnum)
+{
+ struct phy_device *ext_phydev = phydev->priv;
+
+ debug("%s\n", __func__);
+ if (ext_phydev->drv->readext)
+ ext_phydev->drv->readext(ext_phydev, addr, devaddr, regnum);
+
+ return 0;
+}
+
+static int xilinxgmiitorgmii_extwrite(struct phy_device *phydev, int addr,
+ int devaddr, int regnum, u16 val)
+
+{
+ struct phy_device *ext_phydev = phydev->priv;
+
+ debug("%s\n", __func__);
+ if (ext_phydev->drv->writeext)
+ ext_phydev->drv->writeext(ext_phydev, addr, devaddr, regnum,
+ val);
+
+ return 0;
+}
+
+static int xilinxgmiitorgmii_startup(struct phy_device *phydev)
+{
+ u16 val = 0;
+ struct phy_device *ext_phydev = phydev->priv;
+
+ debug("%s\n", __func__);
+ ext_phydev->dev = phydev->dev;
+ if (ext_phydev->drv->startup)
+ ext_phydev->drv->startup(ext_phydev);
+
+ val = phy_read(phydev, phydev->addr, ZYNQ_GMII2RGMII_REG);
+ val &= ~ZYNQ_GMII2RGMII_SPEED_MASK;
+
+ if (ext_phydev->speed == SPEED_1000)
+ val |= BMCR_SPEED1000;
+ else if (ext_phydev->speed == SPEED_100)
+ val |= BMCR_SPEED100;
+
+ phy_write(phydev, phydev->addr, ZYNQ_GMII2RGMII_REG, val |
+ BMCR_FULLDPLX);
+
+ phydev->duplex = ext_phydev->duplex;
+ phydev->speed = ext_phydev->speed;
+ phydev->link = ext_phydev->link;
+
+ return 0;
+}
+
+static int xilinxgmiitorgmii_probe(struct phy_device *phydev)
+{
+ int ofnode = phydev->addr;
+ u32 phy_of_handle;
+ int ext_phyaddr = -1;
+ struct phy_device *ext_phydev;
+
+ debug("%s\n", __func__);
+
+ if (phydev->interface != PHY_INTERFACE_MODE_GMII) {
+ printf("Incorrect interface type\n");
+ return -EINVAL;
+ }
+
+ /*
+ * Read the phy address again as the one we read in ethernet driver
+ * was overwritten for the purpose of storing the ofnode
+ */
+ phydev->addr = fdtdec_get_int(gd->fdt_blob, ofnode, "reg", -1);
+ phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, ofnode,
+ "phy-handle");
+ if (phy_of_handle > 0)
+ ext_phyaddr = fdtdec_get_int(gd->fdt_blob,
+ phy_of_handle,
+ "reg", -1);
+ ext_phydev = phy_find_by_mask(phydev->bus,
+ 1 << ext_phyaddr,
+ PHY_INTERFACE_MODE_RGMII);
+ if (!ext_phydev) {
+ printf("%s, No external phy device found\n", __func__);
+ return -EINVAL;
+ }
+
+ ext_phydev->node = offset_to_ofnode(phy_of_handle);
+ phydev->priv = ext_phydev;
+
+ debug("%s, gmii2rgmmi:0x%x, extphy:0x%x\n", __func__, phydev->addr,
+ ext_phyaddr);
+
+ phydev->flags |= PHY_FLAG_BROKEN_RESET;
+
+ return 0;
+}
+
+static struct phy_driver gmii2rgmii_driver = {
+ .name = "XILINX GMII2RGMII",
+ .uid = PHY_GMII2RGMII_ID,
+ .mask = 0xffffffff,
+ .features = PHY_GBIT_FEATURES,
+ .probe = xilinxgmiitorgmii_probe,
+ .config = xilinxgmiitorgmii_config,
+ .startup = xilinxgmiitorgmii_startup,
+ .writeext = xilinxgmiitorgmii_extwrite,
+ .readext = xilinxgmiitorgmii_extread,
+};
+
+int phy_xilinx_gmii2rgmii_init(void)
+{
+ phy_register(&gmii2rgmii_driver);
+
+ return 0;
+}
diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index 26c21c6..36d6511 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -93,6 +93,7 @@
struct phy_device *phydev;
struct mii_dev *bus;
u8 eth_hasnobuf;
+ int phy_of_handle;
};
/* BD descriptors */
@@ -276,6 +277,8 @@
phydev->supported &= supported;
phydev->advertising = phydev->supported;
priv->phydev = phydev;
+ if (priv->phy_of_handle)
+ priv->phydev->node = offset_to_ofnode(priv->phy_of_handle);
phy_config(phydev);
return 0;
@@ -736,8 +739,10 @@
priv->phyaddr = -1;
offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
- if (offset > 0)
+ if (offset > 0) {
priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
+ priv->phy_of_handle = offset;
+ }
phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
if (phy_mode)
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 033efb8..a7a6ce9 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -26,8 +26,6 @@
#include <asm/arch/sys_proto.h>
#include <linux/errno.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Bit/mask specification */
#define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
#define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */
@@ -465,7 +463,6 @@
break;
}
-#if !defined(CONFIG_ARCH_VERSAL)
ret = clk_set_rate(&priv->clk, clk_rate);
if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
dev_err(dev, "failed to set tx clock rate\n");
@@ -477,9 +474,6 @@
dev_err(dev, "failed to enable tx clock\n");
return ret;
}
-#else
- debug("requested clk_rate %ld\n", clk_rate);
-#endif
setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
ZYNQ_GEM_NWCTRL_TXEN_MASK);
@@ -753,6 +747,7 @@
}
static const struct udevice_id zynq_gem_ids[] = {
+ { .compatible = "cdns,versal-gem" },
{ .compatible = "cdns,zynqmp-gem" },
{ .compatible = "cdns,zynq-gem" },
{ .compatible = "cdns,gem" },
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index bdfc0c1..19e7b50 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -151,4 +151,12 @@
help
Say Y here if you want to enable PCI controller support on AM654 SoC.
+config PCIE_MEDIATEK
+ bool "MediaTek PCIe Gen2 controller"
+ depends on DM_PCI
+ depends on ARCH_MEDIATEK
+ help
+ Say Y here if you want to enable Gen2 PCIe controller,
+ which could be found on MT7623 SoC family.
+
endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index e54a98b..b1d3dc8 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -39,3 +39,4 @@
obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o
obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o
+obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o
diff --git a/drivers/pci/pcie_mediatek.c b/drivers/pci/pcie_mediatek.c
new file mode 100644
index 0000000..a0dcb25
--- /dev/null
+++ b/drivers/pci/pcie_mediatek.c
@@ -0,0 +1,279 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek PCIe host controller driver.
+ *
+ * Copyright (c) 2017-2019 MediaTek Inc.
+ * Author: Ryder Lee <ryder.lee@mediatek.com>
+ * Honghui Zhang <honghui.zhang@mediatek.com>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <generic-phy.h>
+#include <pci.h>
+#include <reset.h>
+#include <asm/io.h>
+#include <linux/iopoll.h>
+#include <linux/list.h>
+
+/* PCIe shared registers */
+#define PCIE_SYS_CFG 0x00
+#define PCIE_INT_ENABLE 0x0c
+#define PCIE_CFG_ADDR 0x20
+#define PCIE_CFG_DATA 0x24
+
+/* PCIe per port registers */
+#define PCIE_BAR0_SETUP 0x10
+#define PCIE_CLASS 0x34
+#define PCIE_LINK_STATUS 0x50
+
+#define PCIE_PORT_INT_EN(x) BIT(20 + (x))
+#define PCIE_PORT_PERST(x) BIT(1 + (x))
+#define PCIE_PORT_LINKUP BIT(0)
+#define PCIE_BAR_MAP_MAX GENMASK(31, 16)
+
+#define PCIE_BAR_ENABLE BIT(0)
+#define PCIE_REVISION_ID BIT(0)
+#define PCIE_CLASS_CODE (0x60400 << 8)
+#define PCIE_CONF_REG(regn) (((regn) & GENMASK(7, 2)) | \
+ ((((regn) >> 8) & GENMASK(3, 0)) << 24))
+#define PCIE_CONF_ADDR(regn, bdf) \
+ (PCIE_CONF_REG(regn) | (bdf))
+
+/* MediaTek specific configuration registers */
+#define PCIE_FTS_NUM 0x70c
+#define PCIE_FTS_NUM_MASK GENMASK(15, 8)
+#define PCIE_FTS_NUM_L0(x) ((x) & 0xff << 8)
+
+#define PCIE_FC_CREDIT 0x73c
+#define PCIE_FC_CREDIT_MASK (GENMASK(31, 31) | GENMASK(28, 16))
+#define PCIE_FC_CREDIT_VAL(x) ((x) << 16)
+
+struct mtk_pcie_port {
+ void __iomem *base;
+ struct list_head list;
+ struct mtk_pcie *pcie;
+ struct reset_ctl reset;
+ struct clk sys_ck;
+ struct phy phy;
+ u32 slot;
+};
+
+struct mtk_pcie {
+ void __iomem *base;
+ struct clk free_ck;
+ struct list_head ports;
+};
+
+static int mtk_pcie_config_address(struct udevice *udev, pci_dev_t bdf,
+ uint offset, void **paddress)
+{
+ struct mtk_pcie *pcie = dev_get_priv(udev);
+
+ writel(PCIE_CONF_ADDR(offset, bdf), pcie->base + PCIE_CFG_ADDR);
+ *paddress = pcie->base + PCIE_CFG_DATA + (offset & 3);
+
+ return 0;
+}
+
+static int mtk_pcie_read_config(struct udevice *bus, pci_dev_t bdf,
+ uint offset, ulong *valuep,
+ enum pci_size_t size)
+{
+ return pci_generic_mmap_read_config(bus, mtk_pcie_config_address,
+ bdf, offset, valuep, size);
+}
+
+static int mtk_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
+ uint offset, ulong value,
+ enum pci_size_t size)
+{
+ return pci_generic_mmap_write_config(bus, mtk_pcie_config_address,
+ bdf, offset, value, size);
+}
+
+static const struct dm_pci_ops mtk_pcie_ops = {
+ .read_config = mtk_pcie_read_config,
+ .write_config = mtk_pcie_write_config,
+};
+
+static void mtk_pcie_port_free(struct mtk_pcie_port *port)
+{
+ list_del(&port->list);
+ free(port);
+}
+
+static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
+{
+ struct mtk_pcie *pcie = port->pcie;
+ u32 slot = PCI_DEV(port->slot << 11);
+ u32 val;
+ int err;
+
+ /* assert port PERST_N */
+ setbits_le32(pcie->base + PCIE_SYS_CFG, PCIE_PORT_PERST(port->slot));
+ /* de-assert port PERST_N */
+ clrbits_le32(pcie->base + PCIE_SYS_CFG, PCIE_PORT_PERST(port->slot));
+
+ /* 100ms timeout value should be enough for Gen1/2 training */
+ err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val,
+ !!(val & PCIE_PORT_LINKUP), 100000);
+ if (err)
+ return -ETIMEDOUT;
+
+ /* disable interrupt */
+ clrbits_le32(pcie->base + PCIE_INT_ENABLE,
+ PCIE_PORT_INT_EN(port->slot));
+
+ /* map to all DDR region. We need to set it before cfg operation. */
+ writel(PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
+ port->base + PCIE_BAR0_SETUP);
+
+ /* configure class code and revision ID */
+ writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS);
+
+ /* configure FC credit */
+ writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, slot),
+ pcie->base + PCIE_CFG_ADDR);
+ clrsetbits_le32(pcie->base + PCIE_CFG_DATA, PCIE_FC_CREDIT_MASK,
+ PCIE_FC_CREDIT_VAL(0x806c));
+
+ /* configure RC FTS number to 250 when it leaves L0s */
+ writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, slot), pcie->base + PCIE_CFG_ADDR);
+ clrsetbits_le32(pcie->base + PCIE_CFG_DATA, PCIE_FTS_NUM_MASK,
+ PCIE_FTS_NUM_L0(0x50));
+
+ return 0;
+}
+
+static void mtk_pcie_enable_port(struct mtk_pcie_port *port)
+{
+ int err;
+
+ err = clk_enable(&port->sys_ck);
+ if (err)
+ goto exit;
+
+ err = reset_assert(&port->reset);
+ if (err)
+ goto exit;
+
+ err = reset_deassert(&port->reset);
+ if (err)
+ goto exit;
+
+ err = generic_phy_init(&port->phy);
+ if (err)
+ goto exit;
+
+ err = generic_phy_power_on(&port->phy);
+ if (err)
+ goto exit;
+
+ if (!mtk_pcie_startup_port(port))
+ return;
+
+ pr_err("Port%d link down\n", port->slot);
+exit:
+ mtk_pcie_port_free(port);
+}
+
+static int mtk_pcie_parse_port(struct udevice *dev, u32 slot)
+{
+ struct mtk_pcie *pcie = dev_get_priv(dev);
+ struct mtk_pcie_port *port;
+ char name[10];
+ int err;
+
+ port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
+ if (!port)
+ return -ENOMEM;
+
+ snprintf(name, sizeof(name), "port%d", slot);
+ port->base = dev_remap_addr_name(dev, name);
+ if (!port->base)
+ return -ENOENT;
+
+ snprintf(name, sizeof(name), "sys_ck%d", slot);
+ err = clk_get_by_name(dev, name, &port->sys_ck);
+ if (err)
+ return err;
+
+ err = reset_get_by_index(dev, slot, &port->reset);
+ if (err)
+ return err;
+
+ err = generic_phy_get_by_index(dev, slot, &port->phy);
+ if (err)
+ return err;
+
+ port->slot = slot;
+ port->pcie = pcie;
+
+ INIT_LIST_HEAD(&port->list);
+ list_add_tail(&port->list, &pcie->ports);
+
+ return 0;
+}
+
+static int mtk_pcie_probe(struct udevice *dev)
+{
+ struct mtk_pcie *pcie = dev_get_priv(dev);
+ struct mtk_pcie_port *port, *tmp;
+ ofnode subnode;
+ int err;
+
+ INIT_LIST_HEAD(&pcie->ports);
+
+ pcie->base = dev_remap_addr_name(dev, "subsys");
+ if (!pcie->base)
+ return -ENOENT;
+
+ err = clk_get_by_name(dev, "free_ck", &pcie->free_ck);
+ if (err)
+ return err;
+
+ /* enable top level clock */
+ err = clk_enable(&pcie->free_ck);
+ if (err)
+ return err;
+
+ dev_for_each_subnode(subnode, dev) {
+ struct fdt_pci_addr addr;
+ u32 slot = 0;
+
+ if (!ofnode_is_available(subnode))
+ continue;
+
+ err = ofnode_read_pci_addr(subnode, 0, "reg", &addr);
+ if (err)
+ return err;
+
+ slot = PCI_DEV(addr.phys_hi);
+
+ err = mtk_pcie_parse_port(dev, slot);
+ if (err)
+ return err;
+ }
+
+ /* enable each port, and then check link status */
+ list_for_each_entry_safe(port, tmp, &pcie->ports, list)
+ mtk_pcie_enable_port(port);
+
+ return 0;
+}
+
+static const struct udevice_id mtk_pcie_ids[] = {
+ { .compatible = "mediatek,mt7623-pcie", },
+ { }
+};
+
+U_BOOT_DRIVER(pcie_mediatek) = {
+ .name = "pcie_mediatek",
+ .id = UCLASS_PCI,
+ .of_match = mtk_pcie_ids,
+ .ops = &mtk_pcie_ops,
+ .probe = mtk_pcie_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_pcie),
+};
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 0231227..e317373 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -205,4 +205,15 @@
This PHY is found on MT76x8 devices supporting USB.
+config PHY_MTK_TPHY
+ bool "MediaTek T-PHY Driver"
+ depends on PHY
+ depends on ARCH_MEDIATEK
+ help
+ MediaTek T-PHY driver supports usb2.0, usb3.0 ports, PCIe and
+ SATA, and meanwhile supports two version T-PHY which have
+ different banks layout, the T-PHY with shared banks between
+ multi-ports is first version, otherwise is second veriosn,
+ so you can easily distinguish them by banks layout.
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 3157f1b..43ce62e 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -23,3 +23,4 @@
obj-$(CONFIG_KEYSTONE_USB_PHY) += keystone-usb-phy.o
obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o
obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o
+obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
diff --git a/drivers/phy/phy-mtk-tphy.c b/drivers/phy/phy-mtk-tphy.c
new file mode 100644
index 0000000..3701481
--- /dev/null
+++ b/drivers/phy/phy-mtk-tphy.c
@@ -0,0 +1,362 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2015 - 2019 MediaTek Inc.
+ * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
+ * Ryder Lee <ryder.lee@mediatek.com>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <generic-phy.h>
+#include <mapmem.h>
+#include <asm/io.h>
+
+#include <dt-bindings/phy/phy.h>
+
+/* version V1 sub-banks offset base address */
+/* banks shared by multiple phys */
+#define SSUSB_SIFSLV_V1_SPLLC 0x000 /* shared by u3 phys */
+#define SSUSB_SIFSLV_V1_CHIP 0x300 /* shared by u3 phys */
+/* u3/pcie/sata phy banks */
+#define SSUSB_SIFSLV_V1_U3PHYD 0x000
+#define SSUSB_SIFSLV_V1_U3PHYA 0x200
+
+#define U3P_U3_CHIP_GPIO_CTLD 0x0c
+#define P3C_REG_IP_SW_RST BIT(31)
+#define P3C_MCU_BUS_CK_GATE_EN BIT(30)
+#define P3C_FORCE_IP_SW_RST BIT(29)
+
+#define U3P_U3_CHIP_GPIO_CTLE 0x10
+#define P3C_RG_SWRST_U3_PHYD BIT(25)
+#define P3C_RG_SWRST_U3_PHYD_FORCE_EN BIT(24)
+
+#define U3P_U3_PHYA_REG0 0x000
+#define P3A_RG_CLKDRV_OFF GENMASK(3, 2)
+#define P3A_RG_CLKDRV_OFF_VAL(x) ((0x3 & (x)) << 2)
+
+#define U3P_U3_PHYA_REG1 0x004
+#define P3A_RG_CLKDRV_AMP GENMASK(31, 29)
+#define P3A_RG_CLKDRV_AMP_VAL(x) ((0x7 & (x)) << 29)
+
+#define U3P_U3_PHYA_DA_REG0 0x100
+#define P3A_RG_XTAL_EXT_PE2H GENMASK(17, 16)
+#define P3A_RG_XTAL_EXT_PE2H_VAL(x) ((0x3 & (x)) << 16)
+#define P3A_RG_XTAL_EXT_PE1H GENMASK(13, 12)
+#define P3A_RG_XTAL_EXT_PE1H_VAL(x) ((0x3 & (x)) << 12)
+#define P3A_RG_XTAL_EXT_EN_U3 GENMASK(11, 10)
+#define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10)
+
+#define U3P_U3_PHYA_DA_REG4 0x108
+#define P3A_RG_PLL_DIVEN_PE2H GENMASK(21, 19)
+#define P3A_RG_PLL_BC_PE2H GENMASK(7, 6)
+#define P3A_RG_PLL_BC_PE2H_VAL(x) ((0x3 & (x)) << 6)
+
+#define U3P_U3_PHYA_DA_REG5 0x10c
+#define P3A_RG_PLL_BR_PE2H GENMASK(29, 28)
+#define P3A_RG_PLL_BR_PE2H_VAL(x) ((0x3 & (x)) << 28)
+#define P3A_RG_PLL_IC_PE2H GENMASK(15, 12)
+#define P3A_RG_PLL_IC_PE2H_VAL(x) ((0xf & (x)) << 12)
+
+#define U3P_U3_PHYA_DA_REG6 0x110
+#define P3A_RG_PLL_IR_PE2H GENMASK(19, 16)
+#define P3A_RG_PLL_IR_PE2H_VAL(x) ((0xf & (x)) << 16)
+
+#define U3P_U3_PHYA_DA_REG7 0x114
+#define P3A_RG_PLL_BP_PE2H GENMASK(19, 16)
+#define P3A_RG_PLL_BP_PE2H_VAL(x) ((0xf & (x)) << 16)
+
+#define U3P_U3_PHYA_DA_REG20 0x13c
+#define P3A_RG_PLL_DELTA1_PE2H GENMASK(31, 16)
+#define P3A_RG_PLL_DELTA1_PE2H_VAL(x) ((0xffff & (x)) << 16)
+
+#define U3P_U3_PHYA_DA_REG25 0x148
+#define P3A_RG_PLL_DELTA_PE2H GENMASK(15, 0)
+#define P3A_RG_PLL_DELTA_PE2H_VAL(x) (0xffff & (x))
+
+#define U3P_U3_PHYD_RXDET1 0x128
+#define P3D_RG_RXDET_STB2_SET GENMASK(17, 9)
+#define P3D_RG_RXDET_STB2_SET_VAL(x) ((0x1ff & (x)) << 9)
+
+#define U3P_U3_PHYD_RXDET2 0x12c
+#define P3D_RG_RXDET_STB2_SET_P3 GENMASK(8, 0)
+#define P3D_RG_RXDET_STB2_SET_P3_VAL(x) (0x1ff & (x))
+
+struct u3phy_banks {
+ void __iomem *spllc;
+ void __iomem *chip;
+ void __iomem *phyd; /* include u3phyd_bank2 */
+ void __iomem *phya; /* include u3phya_da */
+};
+
+struct mtk_phy_instance {
+ void __iomem *port_base;
+ const struct device_node *np;
+
+ struct u3phy_banks u3_banks;
+
+ /* reference clock of anolog phy */
+ struct clk ref_clk;
+ u32 index;
+ u8 type;
+};
+
+struct mtk_tphy {
+ void __iomem *sif_base;
+ struct mtk_phy_instance **phys;
+ int nphys;
+};
+
+static void pcie_phy_instance_init(struct mtk_tphy *tphy,
+ struct mtk_phy_instance *instance)
+{
+ struct u3phy_banks *u3_banks = &instance->u3_banks;
+
+ clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG0,
+ P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H,
+ P3A_RG_XTAL_EXT_PE1H_VAL(0x2) |
+ P3A_RG_XTAL_EXT_PE2H_VAL(0x2));
+
+ /* ref clk drive */
+ clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG1, P3A_RG_CLKDRV_AMP,
+ P3A_RG_CLKDRV_AMP_VAL(0x4));
+ clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_CLKDRV_OFF,
+ P3A_RG_CLKDRV_OFF_VAL(0x1));
+
+ /* SSC delta -5000ppm */
+ clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG20,
+ P3A_RG_PLL_DELTA1_PE2H,
+ P3A_RG_PLL_DELTA1_PE2H_VAL(0x3c));
+
+ clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG25,
+ P3A_RG_PLL_DELTA_PE2H,
+ P3A_RG_PLL_DELTA_PE2H_VAL(0x36));
+
+ /* change pll BW 0.6M */
+ clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG5,
+ P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H,
+ P3A_RG_PLL_BR_PE2H_VAL(0x1) |
+ P3A_RG_PLL_IC_PE2H_VAL(0x1));
+ clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG4,
+ P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H,
+ P3A_RG_PLL_BC_PE2H_VAL(0x3));
+
+ clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG6,
+ P3A_RG_PLL_IR_PE2H, P3A_RG_PLL_IR_PE2H_VAL(0x2));
+ clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG7,
+ P3A_RG_PLL_BP_PE2H, P3A_RG_PLL_BP_PE2H_VAL(0xa));
+
+ /* Tx Detect Rx Timing: 10us -> 5us */
+ clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET1,
+ P3D_RG_RXDET_STB2_SET,
+ P3D_RG_RXDET_STB2_SET_VAL(0x10));
+ clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET2,
+ P3D_RG_RXDET_STB2_SET_P3,
+ P3D_RG_RXDET_STB2_SET_P3_VAL(0x10));
+
+ /* wait for PCIe subsys register to active */
+ udelay(3000);
+}
+
+static void pcie_phy_instance_power_on(struct mtk_tphy *tphy,
+ struct mtk_phy_instance *instance)
+{
+ struct u3phy_banks *bank = &instance->u3_banks;
+
+ clrbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLD,
+ P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
+ clrbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLE,
+ P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD);
+}
+
+static void pcie_phy_instance_power_off(struct mtk_tphy *tphy,
+ struct mtk_phy_instance *instance)
+
+{
+ struct u3phy_banks *bank = &instance->u3_banks;
+
+ setbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLD,
+ P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
+ setbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLE,
+ P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD);
+}
+
+static void phy_v1_banks_init(struct mtk_tphy *tphy,
+ struct mtk_phy_instance *instance)
+{
+ struct u3phy_banks *u3_banks = &instance->u3_banks;
+
+ switch (instance->type) {
+ case PHY_TYPE_PCIE:
+ u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC;
+ u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP;
+ u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
+ u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;
+ break;
+ default:
+ return;
+ }
+}
+
+static int mtk_phy_init(struct phy *phy)
+{
+ struct mtk_tphy *tphy = dev_get_priv(phy->dev);
+ struct mtk_phy_instance *instance = tphy->phys[phy->id];
+ int ret;
+
+ /* we may use a fixed-clock here */
+ ret = clk_enable(&instance->ref_clk);
+ if (ret && ret != -ENOSYS)
+ return ret;
+
+ switch (instance->type) {
+ case PHY_TYPE_PCIE:
+ pcie_phy_instance_init(tphy, instance);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int mtk_phy_power_on(struct phy *phy)
+{
+ struct mtk_tphy *tphy = dev_get_priv(phy->dev);
+ struct mtk_phy_instance *instance = tphy->phys[phy->id];
+
+ pcie_phy_instance_power_on(tphy, instance);
+
+ return 0;
+}
+
+static int mtk_phy_power_off(struct phy *phy)
+{
+ struct mtk_tphy *tphy = dev_get_priv(phy->dev);
+ struct mtk_phy_instance *instance = tphy->phys[phy->id];
+
+ pcie_phy_instance_power_off(tphy, instance);
+
+ return 0;
+}
+
+static int mtk_phy_exit(struct phy *phy)
+{
+ struct mtk_tphy *tphy = dev_get_priv(phy->dev);
+ struct mtk_phy_instance *instance = tphy->phys[phy->id];
+
+ clk_disable(&instance->ref_clk);
+
+ return 0;
+}
+
+static int mtk_phy_xlate(struct phy *phy,
+ struct ofnode_phandle_args *args)
+{
+ struct mtk_tphy *tphy = dev_get_priv(phy->dev);
+ struct mtk_phy_instance *instance = NULL;
+ const struct device_node *phy_np = ofnode_to_np(args->node);
+ u32 index;
+
+ if (!phy_np) {
+ dev_err(phy->dev, "null pointer phy node\n");
+ return -EINVAL;
+ }
+
+ if (args->args_count < 1) {
+ dev_err(phy->dev, "invalid number of cells in 'phy' property\n");
+ return -EINVAL;
+ }
+
+ for (index = 0; index < tphy->nphys; index++)
+ if (phy_np == tphy->phys[index]->np) {
+ instance = tphy->phys[index];
+ break;
+ }
+
+ if (!instance) {
+ dev_err(phy->dev, "failed to find appropriate phy\n");
+ return -EINVAL;
+ }
+
+ phy->id = index;
+ instance->type = args->args[1];
+ if (!(instance->type == PHY_TYPE_USB2 ||
+ instance->type == PHY_TYPE_USB3 ||
+ instance->type == PHY_TYPE_PCIE ||
+ instance->type == PHY_TYPE_SATA)) {
+ dev_err(phy->dev, "unsupported device type\n");
+ return -EINVAL;
+ }
+
+ phy_v1_banks_init(tphy, instance);
+
+ return 0;
+}
+
+static const struct phy_ops mtk_tphy_ops = {
+ .init = mtk_phy_init,
+ .exit = mtk_phy_exit,
+ .power_on = mtk_phy_power_on,
+ .power_off = mtk_phy_power_off,
+ .of_xlate = mtk_phy_xlate,
+};
+
+static int mtk_tphy_probe(struct udevice *dev)
+{
+ struct mtk_tphy *tphy = dev_get_priv(dev);
+ ofnode subnode;
+ int index = 0;
+
+ dev_for_each_subnode(subnode, dev)
+ tphy->nphys++;
+
+ tphy->phys = devm_kcalloc(dev, tphy->nphys, sizeof(*tphy->phys),
+ GFP_KERNEL);
+ if (!tphy->phys)
+ return -ENOMEM;
+
+ tphy->sif_base = dev_read_addr_ptr(dev);
+ if (!tphy->sif_base)
+ return -ENOENT;
+
+ dev_for_each_subnode(subnode, dev) {
+ struct mtk_phy_instance *instance;
+ fdt_addr_t addr;
+ int err;
+
+ instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL);
+ if (!instance)
+ return -ENOMEM;
+
+ addr = ofnode_get_addr(subnode);
+ if (addr == FDT_ADDR_T_NONE)
+ return -ENOMEM;
+
+ instance->port_base = map_sysmem(addr, 0);
+ instance->index = index;
+ instance->np = ofnode_to_np(subnode);
+ tphy->phys[index] = instance;
+ index++;
+
+ err = clk_get_by_index_nodev(subnode, 0, &instance->ref_clk);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id mtk_tphy_id_table[] = {
+ { .compatible = "mediatek,generic-tphy-v1", },
+ { }
+};
+
+U_BOOT_DRIVER(mtk_tphy) = {
+ .name = "mtk-tphy",
+ .id = UCLASS_PHY,
+ .of_match = mtk_tphy_id_table,
+ .ops = &mtk_tphy_ops,
+ .probe = mtk_tphy_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_tphy),
+};
diff --git a/drivers/power/regulator/regulator_common.c b/drivers/power/regulator/regulator_common.c
index 3dabbe2..2041086 100644
--- a/drivers/power/regulator/regulator_common.c
+++ b/drivers/power/regulator/regulator_common.c
@@ -12,10 +12,15 @@
struct regulator_common_platdata *dev_pdata, const char *enable_gpio_name)
{
struct gpio_desc *gpio;
+ struct dm_regulator_uclass_platdata *uc_pdata;
int flags = GPIOD_IS_OUT;
int ret;
- if (dev_read_bool(dev, "enable-active-high"))
+ uc_pdata = dev_get_uclass_platdata(dev);
+
+ if (!dev_read_bool(dev, "enable-active-high"))
+ flags |= GPIOD_ACTIVE_LOW;
+ if (uc_pdata->boot_on)
flags |= GPIOD_IS_OUT_ACTIVE;
/* Get optional enable GPIO desc */
diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig
index f54a245..7c2e480 100644
--- a/drivers/remoteproc/Kconfig
+++ b/drivers/remoteproc/Kconfig
@@ -52,6 +52,26 @@
on various TI K3 family of SoCs through the remote processor
framework.
+config REMOTEPROC_TI_K3_DSP
+ bool "TI K3 C66 and C71 remoteproc support"
+ select REMOTEPROC
+ depends on ARCH_K3
+ depends on TI_SCI_PROTOCOL
+ help
+ Say y here to support TI's C66/C71 remote processor subsystems
+ on various TI K3 family of SoCs through the remote processor
+ framework.
+
+config REMOTEPROC_TI_K3_R5F
+ bool "TI K3 R5F remoteproc support"
+ select REMOTEPROC
+ depends on ARCH_K3
+ depends on TI_SCI_PROTOCOL
+ help
+ Say y here to support TI's R5F remote processor subsystems
+ on various TI K3 family of SoCs through the remote processor
+ framework.
+
config REMOTEPROC_TI_POWER
bool "Support for TI Power processor"
select REMOTEPROC
diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile
index 271ba55..69ae7bd 100644
--- a/drivers/remoteproc/Makefile
+++ b/drivers/remoteproc/Makefile
@@ -11,4 +11,6 @@
obj-$(CONFIG_REMOTEPROC_SANDBOX) += sandbox_testproc.o
obj-$(CONFIG_REMOTEPROC_STM32_COPRO) += stm32_copro.o
obj-$(CONFIG_REMOTEPROC_TI_K3_ARM64) += ti_k3_arm64_rproc.o
+obj-$(CONFIG_REMOTEPROC_TI_K3_DSP) += ti_k3_dsp_rproc.o
+obj-$(CONFIG_REMOTEPROC_TI_K3_R5F) += ti_k3_r5f_rproc.o
obj-$(CONFIG_REMOTEPROC_TI_POWER) += ti_power_proc.o
diff --git a/drivers/remoteproc/rproc-elf-loader.c b/drivers/remoteproc/rproc-elf-loader.c
index 67937a7..b38a226 100644
--- a/drivers/remoteproc/rproc-elf-loader.c
+++ b/drivers/remoteproc/rproc-elf-loader.c
@@ -64,13 +64,90 @@
return 0;
}
-/* A very simple elf loader, assumes the image is valid */
-int rproc_elf32_load_image(struct udevice *dev, unsigned long addr)
+/* Basic function to verify ELF64 image format */
+int rproc_elf64_sanity_check(ulong addr, ulong size)
+{
+ Elf64_Ehdr *ehdr = (Elf64_Ehdr *)addr;
+ char class;
+
+ if (!addr) {
+ pr_debug("Invalid fw address?\n");
+ return -EFAULT;
+ }
+
+ if (size < sizeof(Elf64_Ehdr)) {
+ pr_debug("Image is too small\n");
+ return -ENOSPC;
+ }
+
+ class = ehdr->e_ident[EI_CLASS];
+
+ if (!IS_ELF(*ehdr) || ehdr->e_type != ET_EXEC || class != ELFCLASS64) {
+ pr_debug("Not an executable ELF64 image\n");
+ return -EPROTONOSUPPORT;
+ }
+
+ /* We assume the firmware has the same endianness as the host */
+# ifdef __LITTLE_ENDIAN
+ if (ehdr->e_ident[EI_DATA] != ELFDATA2LSB) {
+# else /* BIG ENDIAN */
+ if (ehdr->e_ident[EI_DATA] != ELFDATA2MSB) {
+# endif
+ pr_debug("Unsupported firmware endianness\n");
+ return -EILSEQ;
+ }
+
+ if (size < ehdr->e_shoff + sizeof(Elf64_Shdr)) {
+ pr_debug("Image is too small\n");
+ return -ENOSPC;
+ }
+
+ if (memcmp(ehdr->e_ident, ELFMAG, SELFMAG)) {
+ pr_debug("Image is corrupted (bad magic)\n");
+ return -EBADF;
+ }
+
+ if (ehdr->e_phnum == 0) {
+ pr_debug("No loadable segments\n");
+ return -ENOEXEC;
+ }
+
+ if (ehdr->e_phoff > size) {
+ pr_debug("Firmware size is too small\n");
+ return -ENOSPC;
+ }
+
+ return 0;
+}
+
+/* Basic function to verify ELF image format */
+int rproc_elf_sanity_check(ulong addr, ulong size)
+{
+ Elf32_Ehdr *ehdr = (Elf32_Ehdr *)addr;
+
+ if (!addr) {
+ dev_err(dev, "Invalid firmware address\n");
+ return -EFAULT;
+ }
+
+ if (ehdr->e_ident[EI_CLASS] == ELFCLASS64)
+ return rproc_elf64_sanity_check(addr, size);
+ else
+ return rproc_elf32_sanity_check(addr, size);
+}
+
+int rproc_elf32_load_image(struct udevice *dev, unsigned long addr, ulong size)
{
Elf32_Ehdr *ehdr; /* Elf header structure pointer */
Elf32_Phdr *phdr; /* Program header structure pointer */
const struct dm_rproc_ops *ops;
- unsigned int i;
+ unsigned int i, ret;
+
+ ret = rproc_elf32_sanity_check(addr, size);
+ if (ret) {
+ dev_err(dev, "Invalid ELF32 Image %d\n", ret);
+ return ret;
+ }
ehdr = (Elf32_Ehdr *)addr;
phdr = (Elf32_Phdr *)(addr + ehdr->e_phoff);
@@ -86,7 +163,8 @@
continue;
if (ops->device_to_virt)
- dst = ops->device_to_virt(dev, (ulong)dst);
+ dst = ops->device_to_virt(dev, (ulong)dst,
+ phdr->p_memsz);
dev_dbg(dev, "Loading phdr %i to 0x%p (%i bytes)\n",
i, dst, phdr->p_filesz);
@@ -104,3 +182,96 @@
return 0;
}
+
+int rproc_elf64_load_image(struct udevice *dev, ulong addr, ulong size)
+{
+ const struct dm_rproc_ops *ops = rproc_get_ops(dev);
+ u64 da, memsz, filesz, offset;
+ Elf64_Ehdr *ehdr;
+ Elf64_Phdr *phdr;
+ int i, ret = 0;
+ void *ptr;
+
+ dev_dbg(dev, "%s: addr = 0x%lx size = 0x%lx\n", __func__, addr, size);
+
+ if (rproc_elf64_sanity_check(addr, size))
+ return -EINVAL;
+
+ ehdr = (Elf64_Ehdr *)addr;
+ phdr = (Elf64_Phdr *)(addr + (ulong)ehdr->e_phoff);
+
+ /* go through the available ELF segments */
+ for (i = 0; i < ehdr->e_phnum; i++, phdr++) {
+ da = phdr->p_paddr;
+ memsz = phdr->p_memsz;
+ filesz = phdr->p_filesz;
+ offset = phdr->p_offset;
+
+ if (phdr->p_type != PT_LOAD)
+ continue;
+
+ dev_dbg(dev, "%s:phdr: type %d da 0x%llx memsz 0x%llx filesz 0x%llx\n",
+ __func__, phdr->p_type, da, memsz, filesz);
+
+ ptr = (void *)(uintptr_t)da;
+ if (ops->device_to_virt) {
+ ptr = ops->device_to_virt(dev, da, phdr->p_memsz);
+ if (!ptr) {
+ dev_err(dev, "bad da 0x%llx mem 0x%llx\n", da,
+ memsz);
+ ret = -EINVAL;
+ break;
+ }
+ }
+
+ if (filesz)
+ memcpy(ptr, (void *)addr + offset, filesz);
+ if (filesz != memsz)
+ memset(ptr + filesz, 0x00, memsz - filesz);
+
+ flush_cache(rounddown((ulong)ptr, ARCH_DMA_MINALIGN),
+ roundup((ulong)ptr + filesz, ARCH_DMA_MINALIGN) -
+ rounddown((ulong)ptr, ARCH_DMA_MINALIGN));
+ }
+
+ return ret;
+}
+
+int rproc_elf_load_image(struct udevice *dev, ulong addr, ulong size)
+{
+ Elf32_Ehdr *ehdr = (Elf32_Ehdr *)addr;
+
+ if (!addr) {
+ dev_err(dev, "Invalid firmware address\n");
+ return -EFAULT;
+ }
+
+ if (ehdr->e_ident[EI_CLASS] == ELFCLASS64)
+ return rproc_elf64_load_image(dev, addr, size);
+ else
+ return rproc_elf32_load_image(dev, addr, size);
+}
+
+static ulong rproc_elf32_get_boot_addr(ulong addr)
+{
+ Elf32_Ehdr *ehdr = (Elf32_Ehdr *)addr;
+
+ return ehdr->e_entry;
+}
+
+static ulong rproc_elf64_get_boot_addr(ulong addr)
+{
+ Elf64_Ehdr *ehdr = (Elf64_Ehdr *)addr;
+
+ return ehdr->e_entry;
+}
+
+ulong rproc_elf_get_boot_addr(struct udevice *dev, ulong addr)
+{
+ Elf32_Ehdr *ehdr = (Elf32_Ehdr *)addr;
+
+ if (ehdr->e_ident[EI_CLASS] == ELFCLASS64)
+ return rproc_elf64_get_boot_addr(addr);
+ else
+ return rproc_elf32_get_boot_addr(addr);
+}
diff --git a/drivers/remoteproc/sandbox_testproc.c b/drivers/remoteproc/sandbox_testproc.c
index 5f35119..eeee49c 100644
--- a/drivers/remoteproc/sandbox_testproc.c
+++ b/drivers/remoteproc/sandbox_testproc.c
@@ -306,9 +306,11 @@
* sandbox_testproc_device_to_virt() - Convert device address to virtual address
* @dev: device to operate upon
* @da: device address
+ * @size: Size of the memory region @da is pointing to
* @return converted virtual address
*/
-static void *sandbox_testproc_device_to_virt(struct udevice *dev, ulong da)
+static void *sandbox_testproc_device_to_virt(struct udevice *dev, ulong da,
+ ulong size)
{
u64 paddr;
diff --git a/drivers/remoteproc/stm32_copro.c b/drivers/remoteproc/stm32_copro.c
index ad941f6..40bba37 100644
--- a/drivers/remoteproc/stm32_copro.c
+++ b/drivers/remoteproc/stm32_copro.c
@@ -107,11 +107,13 @@
* stm32_copro_device_to_virt() - Convert device address to virtual address
* @dev: corresponding STM32 remote processor device
* @da: device address
+ * @size: Size of the memory region @da is pointing to
* @return converted virtual address
*/
-static void *stm32_copro_device_to_virt(struct udevice *dev, ulong da)
+static void *stm32_copro_device_to_virt(struct udevice *dev, ulong da,
+ ulong size)
{
- fdt32_t in_addr = cpu_to_be32(da);
+ fdt32_t in_addr = cpu_to_be32(da), end_addr;
u64 paddr;
paddr = dev_translate_dma_address(dev, &in_addr);
@@ -120,6 +122,12 @@
return NULL;
}
+ end_addr = cpu_to_be32(da + size - 1);
+ if (dev_translate_dma_address(dev, &end_addr) == OF_BAD_ADDR) {
+ dev_err(dev, "Unable to convert address %ld\n", da + size - 1);
+ return NULL;
+ }
+
return phys_to_virt(paddr);
}
@@ -147,14 +155,7 @@
return ret;
}
- /* Support only ELF32 image */
- ret = rproc_elf32_sanity_check(addr, size);
- if (ret) {
- dev_err(dev, "Invalid ELF32 image (%d)\n", ret);
- return ret;
- }
-
- return rproc_elf32_load_image(dev, addr);
+ return rproc_elf32_load_image(dev, addr, size);
}
/**
diff --git a/drivers/remoteproc/ti_k3_dsp_rproc.c b/drivers/remoteproc/ti_k3_dsp_rproc.c
new file mode 100644
index 0000000..c5dc6b2
--- /dev/null
+++ b/drivers/remoteproc/ti_k3_dsp_rproc.c
@@ -0,0 +1,354 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments' K3 DSP Remoteproc driver
+ *
+ * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Lokesh Vutla <lokeshvutla@ti.com>
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <remoteproc.h>
+#include <errno.h>
+#include <clk.h>
+#include <reset.h>
+#include <asm/io.h>
+#include <power-domain.h>
+#include <linux/soc/ti/ti_sci_protocol.h>
+#include "ti_sci_proc.h"
+
+#define KEYSTONE_RPROC_LOCAL_ADDRESS_MASK (SZ_16M - 1)
+
+/**
+ * struct k3_dsp_mem - internal memory structure
+ * @cpu_addr: MPU virtual address of the memory region
+ * @bus_addr: Bus address used to access the memory region
+ * @dev_addr: Device address from remoteproc view
+ * @size: Size of the memory region
+ */
+struct k3_dsp_mem {
+ void __iomem *cpu_addr;
+ phys_addr_t bus_addr;
+ phys_addr_t dev_addr;
+ size_t size;
+};
+
+/**
+ * struct k3_dsp_privdata - Structure representing Remote processor data.
+ * @rproc_rst: rproc reset control data
+ * @tsp: Pointer to TISCI proc contrl handle
+ * @mem: Array of available memories
+ * @num_mem: Number of available memories
+ */
+struct k3_dsp_privdata {
+ struct reset_ctl dsp_rst;
+ struct ti_sci_proc tsp;
+ struct k3_dsp_mem *mem;
+ int num_mems;
+};
+
+/**
+ * k3_dsp_load() - Load up the Remote processor image
+ * @dev: rproc device pointer
+ * @addr: Address at which image is available
+ * @size: size of the image
+ *
+ * Return: 0 if all goes good, else appropriate error message.
+ */
+static int k3_dsp_load(struct udevice *dev, ulong addr, ulong size)
+{
+ struct k3_dsp_privdata *dsp = dev_get_priv(dev);
+ u32 boot_vector;
+ int ret;
+
+ dev_dbg(dev, "%s addr = 0x%lx, size = 0x%lx\n", __func__, addr, size);
+ ret = ti_sci_proc_request(&dsp->tsp);
+ if (ret)
+ return ret;
+
+ ret = rproc_elf_load_image(dev, addr, size);
+ if (ret < 0) {
+ dev_err(dev, "Loading elf failed %d\n", ret);
+ goto proc_release;
+ }
+
+ boot_vector = rproc_elf_get_boot_addr(dev, addr);
+
+ dev_dbg(dev, "%s: Boot vector = 0x%x\n", __func__, boot_vector);
+
+ ret = ti_sci_proc_set_config(&dsp->tsp, boot_vector, 0, 0);
+proc_release:
+ ti_sci_proc_release(&dsp->tsp);
+ return ret;
+}
+
+/**
+ * k3_dsp_start() - Start the remote processor
+ * @dev: rproc device pointer
+ *
+ * Return: 0 if all went ok, else return appropriate error
+ */
+static int k3_dsp_start(struct udevice *dev)
+{
+ struct k3_dsp_privdata *dsp = dev_get_priv(dev);
+ int ret;
+
+ dev_dbg(dev, "%s\n", __func__);
+
+ ret = ti_sci_proc_request(&dsp->tsp);
+ if (ret)
+ return ret;
+ /*
+ * Setting the right clock frequency would have taken care by
+ * assigned-clock-rates during the device probe. So no need to
+ * set the frequency again here.
+ */
+ ret = ti_sci_proc_power_domain_on(&dsp->tsp);
+ if (ret)
+ goto proc_release;
+
+ ret = reset_deassert(&dsp->dsp_rst);
+
+proc_release:
+ ti_sci_proc_release(&dsp->tsp);
+
+ return ret;
+}
+
+static int k3_dsp_stop(struct udevice *dev)
+{
+ struct k3_dsp_privdata *dsp = dev_get_priv(dev);
+
+ dev_dbg(dev, "%s\n", __func__);
+
+ ti_sci_proc_request(&dsp->tsp);
+ reset_assert(&dsp->dsp_rst);
+ ti_sci_proc_power_domain_off(&dsp->tsp);
+ ti_sci_proc_release(&dsp->tsp);
+
+ return 0;
+}
+
+/**
+ * k3_dsp_init() - Initialize the remote processor
+ * @dev: rproc device pointer
+ *
+ * Return: 0 if all went ok, else return appropriate error
+ */
+static int k3_dsp_init(struct udevice *dev)
+{
+ dev_dbg(dev, "%s\n", __func__);
+
+ return 0;
+}
+
+static int k3_dsp_reset(struct udevice *dev)
+{
+ dev_dbg(dev, "%s\n", __func__);
+
+ return 0;
+}
+
+static void *k3_dsp_da_to_va(struct udevice *dev, ulong da, ulong len)
+{
+ struct k3_dsp_privdata *dsp = dev_get_priv(dev);
+ phys_addr_t bus_addr, dev_addr;
+ void __iomem *va = NULL;
+ size_t size;
+ u32 offset;
+ int i;
+
+ dev_dbg(dev, "%s\n", __func__);
+
+ if (len <= 0)
+ return NULL;
+
+ for (i = 0; i < dsp->num_mems; i++) {
+ bus_addr = dsp->mem[i].bus_addr;
+ dev_addr = dsp->mem[i].dev_addr;
+ size = dsp->mem[i].size;
+
+ if (da >= dev_addr && ((da + len) <= (dev_addr + size))) {
+ offset = da - dev_addr;
+ va = dsp->mem[i].cpu_addr + offset;
+ return (__force void *)va;
+ }
+
+ if (da >= bus_addr && (da + len) <= (bus_addr + size)) {
+ offset = da - bus_addr;
+ va = dsp->mem[i].cpu_addr + offset;
+ return (__force void *)va;
+ }
+ }
+
+ /* Assume it is DDR region and return da */
+ return map_physmem(da, len, MAP_NOCACHE);
+}
+
+static const struct dm_rproc_ops k3_dsp_ops = {
+ .init = k3_dsp_init,
+ .load = k3_dsp_load,
+ .start = k3_dsp_start,
+ .stop = k3_dsp_stop,
+ .reset = k3_dsp_reset,
+ .device_to_virt = k3_dsp_da_to_va,
+};
+
+static int ti_sci_proc_of_to_priv(struct udevice *dev, struct ti_sci_proc *tsp)
+{
+ u32 ids[2];
+ int ret;
+
+ dev_dbg(dev, "%s\n", __func__);
+
+ tsp->sci = ti_sci_get_by_phandle(dev, "ti,sci");
+ if (IS_ERR(tsp->sci)) {
+ dev_err(dev, "ti_sci get failed: %ld\n", PTR_ERR(tsp->sci));
+ return PTR_ERR(tsp->sci);
+ }
+
+ ret = dev_read_u32_array(dev, "ti,sci-proc-ids", ids, 2);
+ if (ret) {
+ dev_err(dev, "Proc IDs not populated %d\n", ret);
+ return ret;
+ }
+
+ tsp->ops = &tsp->sci->ops.proc_ops;
+ tsp->proc_id = ids[0];
+ tsp->host_id = ids[1];
+ tsp->dev_id = dev_read_u32_default(dev, "ti,sci-dev-id",
+ TI_SCI_RESOURCE_NULL);
+ if (tsp->dev_id == TI_SCI_RESOURCE_NULL) {
+ dev_err(dev, "Device ID not populated %d\n", ret);
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static int k3_dsp_of_get_memories(struct udevice *dev)
+{
+ static const char * const mem_names[] = {"l2sram", "l1pram", "l1dram"};
+ struct k3_dsp_privdata *dsp = dev_get_priv(dev);
+ int i;
+
+ dev_dbg(dev, "%s\n", __func__);
+
+ dsp->num_mems = ARRAY_SIZE(mem_names);
+ dsp->mem = calloc(dsp->num_mems, sizeof(*dsp->mem));
+ if (!dsp->mem)
+ return -ENOMEM;
+
+ for (i = 0; i < dsp->num_mems; i++) {
+ /* C71 cores only have a L1P Cache, there are no L1P SRAMs */
+ if (device_is_compatible(dev, "ti,j721e-c71-dsp") &&
+ !strcmp(mem_names[i], "l1pram")) {
+ dsp->mem[i].bus_addr = FDT_ADDR_T_NONE;
+ dsp->mem[i].dev_addr = FDT_ADDR_T_NONE;
+ dsp->mem[i].cpu_addr = NULL;
+ dsp->mem[i].size = 0;
+ continue;
+ }
+
+ dsp->mem[i].bus_addr = dev_read_addr_size_name(dev, mem_names[i],
+ (fdt_addr_t *)&dsp->mem[i].size);
+ if (dsp->mem[i].bus_addr == FDT_ADDR_T_NONE) {
+ dev_err(dev, "%s bus address not found\n", mem_names[i]);
+ return -EINVAL;
+ }
+ dsp->mem[i].cpu_addr = map_physmem(dsp->mem[i].bus_addr,
+ dsp->mem[i].size,
+ MAP_NOCACHE);
+ dsp->mem[i].dev_addr = dsp->mem[i].bus_addr &
+ KEYSTONE_RPROC_LOCAL_ADDRESS_MASK;
+
+ dev_dbg(dev, "memory %8s: bus addr %pa size 0x%zx va %p da %pa\n",
+ mem_names[i], &dsp->mem[i].bus_addr,
+ dsp->mem[i].size, dsp->mem[i].cpu_addr,
+ &dsp->mem[i].dev_addr);
+ }
+
+ return 0;
+}
+
+/**
+ * k3_of_to_priv() - generate private data from device tree
+ * @dev: corresponding k3 dsp processor device
+ * @dsp: pointer to driver specific private data
+ *
+ * Return: 0 if all goes good, else appropriate error message.
+ */
+static int k3_dsp_of_to_priv(struct udevice *dev, struct k3_dsp_privdata *dsp)
+{
+ int ret;
+
+ dev_dbg(dev, "%s\n", __func__);
+
+ ret = reset_get_by_index(dev, 0, &dsp->dsp_rst);
+ if (ret) {
+ dev_err(dev, "reset_get() failed: %d\n", ret);
+ return ret;
+ }
+
+ ret = ti_sci_proc_of_to_priv(dev, &dsp->tsp);
+ if (ret)
+ return ret;
+
+ ret = k3_dsp_of_get_memories(dev);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+/**
+ * k3_dsp_probe() - Basic probe
+ * @dev: corresponding k3 remote processor device
+ *
+ * Return: 0 if all goes good, else appropriate error message.
+ */
+static int k3_dsp_probe(struct udevice *dev)
+{
+ struct k3_dsp_privdata *dsp;
+ int ret;
+
+ dev_dbg(dev, "%s\n", __func__);
+
+ dsp = dev_get_priv(dev);
+
+ ret = k3_dsp_of_to_priv(dev, dsp);
+ if (ret) {
+ dev_dbg(dev, "%s: Probe failed with error %d\n", __func__, ret);
+ return ret;
+ }
+
+ dev_dbg(dev, "Remoteproc successfully probed\n");
+
+ return 0;
+}
+
+static int k3_dsp_remove(struct udevice *dev)
+{
+ struct k3_dsp_privdata *dsp = dev_get_priv(dev);
+
+ free(dsp->mem);
+
+ return 0;
+}
+
+static const struct udevice_id k3_dsp_ids[] = {
+ { .compatible = "ti,j721e-c66-dsp"},
+ { .compatible = "ti,j721e-c71-dsp"},
+ {}
+};
+
+U_BOOT_DRIVER(k3_dsp) = {
+ .name = "k3_dsp",
+ .of_match = k3_dsp_ids,
+ .id = UCLASS_REMOTEPROC,
+ .ops = &k3_dsp_ops,
+ .probe = k3_dsp_probe,
+ .remove = k3_dsp_remove,
+ .priv_auto_alloc_size = sizeof(struct k3_dsp_privdata),
+};
diff --git a/drivers/remoteproc/ti_k3_r5f_rproc.c b/drivers/remoteproc/ti_k3_r5f_rproc.c
new file mode 100644
index 0000000..ae1e4b9
--- /dev/null
+++ b/drivers/remoteproc/ti_k3_r5f_rproc.c
@@ -0,0 +1,816 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments' K3 R5 Remoteproc driver
+ *
+ * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Lokesh Vutla <lokeshvutla@ti.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <remoteproc.h>
+#include <errno.h>
+#include <clk.h>
+#include <reset.h>
+#include <asm/io.h>
+#include <linux/kernel.h>
+#include <linux/soc/ti/ti_sci_protocol.h>
+#include "ti_sci_proc.h"
+
+/*
+ * R5F's view of this address can either be for ATCM or BTCM with the other
+ * at address 0x0 based on loczrama signal.
+ */
+#define K3_R5_TCM_DEV_ADDR 0x41010000
+
+/* R5 TI-SCI Processor Configuration Flags */
+#define PROC_BOOT_CFG_FLAG_R5_DBG_EN 0x00000001
+#define PROC_BOOT_CFG_FLAG_R5_DBG_NIDEN 0x00000002
+#define PROC_BOOT_CFG_FLAG_R5_LOCKSTEP 0x00000100
+#define PROC_BOOT_CFG_FLAG_R5_TEINIT 0x00000200
+#define PROC_BOOT_CFG_FLAG_R5_NMFI_EN 0x00000400
+#define PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE 0x00000800
+#define PROC_BOOT_CFG_FLAG_R5_BTCM_EN 0x00001000
+#define PROC_BOOT_CFG_FLAG_R5_ATCM_EN 0x00002000
+#define PROC_BOOT_CFG_FLAG_GEN_IGN_BOOTVECTOR 0x10000000
+
+/* R5 TI-SCI Processor Control Flags */
+#define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001
+
+/* R5 TI-SCI Processor Status Flags */
+#define PROC_BOOT_STATUS_FLAG_R5_WFE 0x00000001
+#define PROC_BOOT_STATUS_FLAG_R5_WFI 0x00000002
+#define PROC_BOOT_STATUS_FLAG_R5_CLK_GATED 0x00000004
+#define PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED 0x00000100
+
+#define NR_CORES 2
+
+enum cluster_mode {
+ CLUSTER_MODE_SPLIT = 0,
+ CLUSTER_MODE_LOCKSTEP,
+};
+
+/**
+ * struct k3_r5_mem - internal memory structure
+ * @cpu_addr: MPU virtual address of the memory region
+ * @bus_addr: Bus address used to access the memory region
+ * @dev_addr: Device address from remoteproc view
+ * @size: Size of the memory region
+ */
+struct k3_r5f_mem {
+ void __iomem *cpu_addr;
+ phys_addr_t bus_addr;
+ u32 dev_addr;
+ size_t size;
+};
+
+/**
+ * struct k3_r5f_core - K3 R5 core structure
+ * @dev: cached device pointer
+ * @cluster: pointer to the parent cluster.
+ * @reset: reset control handle
+ * @tsp: TI-SCI processor control handle
+ * @mem: Array of available internal memories
+ * @num_mem: Number of available memories
+ * @atcm_enable: flag to control ATCM enablement
+ * @btcm_enable: flag to control BTCM enablement
+ * @loczrama: flag to dictate which TCM is at device address 0x0
+ * @in_use: flag to tell if the core is already in use.
+ */
+struct k3_r5f_core {
+ struct udevice *dev;
+ struct k3_r5f_cluster *cluster;
+ struct reset_ctl reset;
+ struct ti_sci_proc tsp;
+ struct k3_r5f_mem *mem;
+ int num_mems;
+ u32 atcm_enable;
+ u32 btcm_enable;
+ u32 loczrama;
+ bool in_use;
+};
+
+/**
+ * struct k3_r5f_cluster - K3 R5F Cluster structure
+ * @mode: Mode to configure the Cluster - Split or LockStep
+ * @cores: Array of pointers to R5 cores within the cluster
+ */
+struct k3_r5f_cluster {
+ enum cluster_mode mode;
+ struct k3_r5f_core *cores[NR_CORES];
+};
+
+static bool is_primary_core(struct k3_r5f_core *core)
+{
+ return core == core->cluster->cores[0];
+}
+
+static int k3_r5f_proc_request(struct k3_r5f_core *core)
+{
+ struct k3_r5f_cluster *cluster = core->cluster;
+ int i, ret;
+
+ if (cluster->mode == CLUSTER_MODE_LOCKSTEP) {
+ for (i = 0; i < NR_CORES; i++) {
+ ret = ti_sci_proc_request(&cluster->cores[i]->tsp);
+ if (ret)
+ goto proc_release;
+ }
+ } else {
+ ret = ti_sci_proc_request(&core->tsp);
+ }
+
+ return 0;
+
+proc_release:
+ while (i >= 0) {
+ ti_sci_proc_release(&cluster->cores[i]->tsp);
+ i--;
+ }
+ return ret;
+}
+
+static void k3_r5f_proc_release(struct k3_r5f_core *core)
+{
+ struct k3_r5f_cluster *cluster = core->cluster;
+ int i;
+
+ if (cluster->mode == CLUSTER_MODE_LOCKSTEP)
+ for (i = 0; i < NR_CORES; i++)
+ ti_sci_proc_release(&cluster->cores[i]->tsp);
+ else
+ ti_sci_proc_release(&core->tsp);
+}
+
+static int k3_r5f_lockstep_release(struct k3_r5f_cluster *cluster)
+{
+ int ret, c;
+
+ dev_dbg(dev, "%s\n", __func__);
+
+ for (c = NR_CORES - 1; c >= 0; c--) {
+ ret = ti_sci_proc_power_domain_on(&cluster->cores[c]->tsp);
+ if (ret)
+ goto unroll_module_reset;
+ }
+
+ /* deassert local reset on all applicable cores */
+ for (c = NR_CORES - 1; c >= 0; c--) {
+ ret = reset_deassert(&cluster->cores[c]->reset);
+ if (ret)
+ goto unroll_local_reset;
+ }
+
+ return 0;
+
+unroll_local_reset:
+ while (c < NR_CORES) {
+ reset_assert(&cluster->cores[c]->reset);
+ c++;
+ }
+ c = 0;
+unroll_module_reset:
+ while (c < NR_CORES) {
+ ti_sci_proc_power_domain_off(&cluster->cores[c]->tsp);
+ c++;
+ }
+
+ return ret;
+}
+
+static int k3_r5f_split_release(struct k3_r5f_core *core)
+{
+ int ret;
+
+ dev_dbg(dev, "%s\n", __func__);
+
+ ret = ti_sci_proc_power_domain_on(&core->tsp);
+ if (ret) {
+ dev_err(core->dev, "module-reset deassert failed, ret = %d\n",
+ ret);
+ return ret;
+ }
+
+ ret = reset_deassert(&core->reset);
+ if (ret) {
+ dev_err(core->dev, "local-reset deassert failed, ret = %d\n",
+ ret);
+ if (ti_sci_proc_power_domain_off(&core->tsp))
+ dev_warn(core->dev, "module-reset assert back failed\n");
+ }
+
+ return ret;
+}
+
+static int k3_r5f_prepare(struct udevice *dev)
+{
+ struct k3_r5f_core *core = dev_get_priv(dev);
+ struct k3_r5f_cluster *cluster = core->cluster;
+ int ret = 0;
+
+ dev_dbg(dev, "%s\n", __func__);
+
+ if (cluster->mode == CLUSTER_MODE_LOCKSTEP)
+ ret = k3_r5f_lockstep_release(cluster);
+ else
+ ret = k3_r5f_split_release(core);
+
+ if (ret)
+ dev_err(dev, "Unable to enable cores for TCM loading %d\n",
+ ret);
+
+ return ret;
+}
+
+static int k3_r5f_core_sanity_check(struct k3_r5f_core *core)
+{
+ struct k3_r5f_cluster *cluster = core->cluster;
+
+ if (core->in_use) {
+ dev_err(dev, "Invalid op: Trying to load/start on already running core %d\n",
+ core->tsp.proc_id);
+ return -EINVAL;
+ }
+
+ if (cluster->mode == CLUSTER_MODE_LOCKSTEP && !cluster->cores[1]) {
+ printf("Secondary core is not probed in this cluster\n");
+ return -EAGAIN;
+ }
+
+ if (cluster->mode == CLUSTER_MODE_LOCKSTEP && !is_primary_core(core)) {
+ dev_err(dev, "Invalid op: Trying to start secondary core %d in lockstep mode\n",
+ core->tsp.proc_id);
+ return -EINVAL;
+ }
+
+ if (cluster->mode == CLUSTER_MODE_SPLIT && !is_primary_core(core)) {
+ if (!core->cluster->cores[0]->in_use) {
+ dev_err(dev, "Invalid seq: Enable primary core before loading secondary core\n");
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * k3_r5f_load() - Load up the Remote processor image
+ * @dev: rproc device pointer
+ * @addr: Address at which image is available
+ * @size: size of the image
+ *
+ * Return: 0 if all goes good, else appropriate error message.
+ */
+static int k3_r5f_load(struct udevice *dev, ulong addr, ulong size)
+{
+ struct k3_r5f_core *core = dev_get_priv(dev);
+ u32 boot_vector;
+ int ret;
+
+ dev_dbg(dev, "%s addr = 0x%lx, size = 0x%lx\n", __func__, addr, size);
+
+ ret = k3_r5f_core_sanity_check(core);
+ if (ret)
+ return ret;
+
+ ret = k3_r5f_proc_request(core);
+ if (ret)
+ return ret;
+
+ ret = k3_r5f_prepare(dev);
+ if (ret) {
+ dev_err(dev, "R5f prepare failed for core %d\n",
+ core->tsp.proc_id);
+ goto proc_release;
+ }
+
+ /* Zero out TCMs so that ECC can be effective on all TCM addresses */
+ if (core->atcm_enable)
+ memset(core->mem[0].cpu_addr, 0x00, core->mem[0].size);
+ if (core->btcm_enable)
+ memset(core->mem[1].cpu_addr, 0x00, core->mem[1].size);
+
+ ret = rproc_elf_load_image(dev, addr, size);
+ if (ret < 0) {
+ dev_err(dev, "Loading elf failedi %d\n", ret);
+ goto proc_release;
+ }
+
+ boot_vector = rproc_elf_get_boot_addr(dev, addr);
+
+ dev_dbg(dev, "%s: Boot vector = 0x%x\n", __func__, boot_vector);
+
+ ret = ti_sci_proc_set_config(&core->tsp, boot_vector, 0, 0);
+
+proc_release:
+ k3_r5f_proc_release(core);
+
+ return ret;
+}
+
+static int k3_r5f_core_halt(struct k3_r5f_core *core)
+{
+ int ret;
+
+ ret = ti_sci_proc_set_control(&core->tsp,
+ PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0);
+ if (ret)
+ dev_err(core->dev, "Core %d failed to stop\n",
+ core->tsp.proc_id);
+
+ return ret;
+}
+
+static int k3_r5f_core_run(struct k3_r5f_core *core)
+{
+ int ret;
+
+ ret = ti_sci_proc_set_control(&core->tsp,
+ 0, PROC_BOOT_CTRL_FLAG_R5_CORE_HALT);
+ if (ret) {
+ dev_err(core->dev, "Core %d failed to start\n",
+ core->tsp.proc_id);
+ return ret;
+ }
+
+ return 0;
+}
+
+/**
+ * k3_r5f_start() - Start the remote processor
+ * @dev: rproc device pointer
+ *
+ * Return: 0 if all went ok, else return appropriate error
+ */
+static int k3_r5f_start(struct udevice *dev)
+{
+ struct k3_r5f_core *core = dev_get_priv(dev);
+ struct k3_r5f_cluster *cluster = core->cluster;
+ int ret, c;
+
+ dev_dbg(dev, "%s\n", __func__);
+
+ ret = k3_r5f_core_sanity_check(core);
+ if (ret)
+ return ret;
+
+ ret = k3_r5f_proc_request(core);
+ if (ret)
+ return ret;
+
+ if (cluster->mode == CLUSTER_MODE_LOCKSTEP) {
+ if (is_primary_core(core)) {
+ for (c = NR_CORES - 1; c >= 0; c--) {
+ ret = k3_r5f_core_run(cluster->cores[c]);
+ if (ret)
+ goto unroll_core_run;
+ }
+ } else {
+ dev_err(dev, "Invalid op: Trying to start secondary core %d in lockstep mode\n",
+ core->tsp.proc_id);
+ ret = -EINVAL;
+ goto proc_release;
+ }
+ } else {
+ ret = k3_r5f_core_run(core);
+ if (ret)
+ goto proc_release;
+ }
+
+ core->in_use = true;
+
+ k3_r5f_proc_release(core);
+ return 0;
+
+unroll_core_run:
+ while (c < NR_CORES) {
+ k3_r5f_core_halt(cluster->cores[c]);
+ c++;
+ }
+proc_release:
+ k3_r5f_proc_release(core);
+
+ return ret;
+}
+
+static int k3_r5f_split_reset(struct k3_r5f_core *core)
+{
+ int ret;
+
+ dev_dbg(dev, "%s\n", __func__);
+
+ if (reset_assert(&core->reset))
+ ret = -EINVAL;
+
+ if (ti_sci_proc_power_domain_off(&core->tsp))
+ ret = -EINVAL;
+
+ return ret;
+}
+
+static int k3_r5f_lockstep_reset(struct k3_r5f_cluster *cluster)
+{
+ int ret = 0, c;
+
+ dev_dbg(dev, "%s\n", __func__);
+
+ for (c = 0; c < NR_CORES; c++)
+ if (reset_assert(&cluster->cores[c]->reset))
+ ret = -EINVAL;
+
+ /* disable PSC modules on all applicable cores */
+ for (c = 0; c < NR_CORES; c++)
+ if (ti_sci_proc_power_domain_off(&cluster->cores[c]->tsp))
+ ret = -EINVAL;
+
+ return ret;
+}
+
+static int k3_r5f_unprepare(struct udevice *dev)
+{
+ struct k3_r5f_core *core = dev_get_priv(dev);
+ struct k3_r5f_cluster *cluster = core->cluster;
+ int ret;
+
+ dev_dbg(dev, "%s\n", __func__);
+
+ if (cluster->mode == CLUSTER_MODE_LOCKSTEP) {
+ if (is_primary_core(core))
+ ret = k3_r5f_lockstep_reset(cluster);
+ } else {
+ ret = k3_r5f_split_reset(core);
+ }
+
+ if (ret)
+ dev_warn(dev, "Unable to enable cores for TCM loading %d\n",
+ ret);
+
+ return 0;
+}
+
+static int k3_r5f_stop(struct udevice *dev)
+{
+ struct k3_r5f_core *core = dev_get_priv(dev);
+ struct k3_r5f_cluster *cluster = core->cluster;
+ int c, ret;
+
+ dev_dbg(dev, "%s\n", __func__);
+
+ ret = k3_r5f_proc_request(core);
+ if (ret)
+ return ret;
+
+ core->in_use = false;
+
+ if (cluster->mode == CLUSTER_MODE_LOCKSTEP) {
+ if (is_primary_core(core)) {
+ for (c = 0; c < NR_CORES; c++)
+ k3_r5f_core_halt(cluster->cores[c]);
+ } else {
+ dev_err(dev, "Invalid op: Trying to stop secondary core in lockstep mode\n");
+ ret = -EINVAL;
+ goto proc_release;
+ }
+ } else {
+ k3_r5f_core_halt(core);
+ }
+
+ ret = k3_r5f_unprepare(dev);
+proc_release:
+ k3_r5f_proc_release(core);
+ return ret;
+}
+
+static void *k3_r5f_da_to_va(struct udevice *dev, ulong da, ulong size)
+{
+ struct k3_r5f_core *core = dev_get_priv(dev);
+ void __iomem *va = NULL;
+ phys_addr_t bus_addr;
+ u32 dev_addr, offset;
+ ulong mem_size;
+ int i;
+
+ dev_dbg(dev, "%s\n", __func__);
+
+ if (size <= 0)
+ return NULL;
+
+ for (i = 0; i < core->num_mems; i++) {
+ bus_addr = core->mem[i].bus_addr;
+ dev_addr = core->mem[i].dev_addr;
+ mem_size = core->mem[i].size;
+
+ if (da >= bus_addr && (da + size) <= (bus_addr + mem_size)) {
+ offset = da - bus_addr;
+ va = core->mem[i].cpu_addr + offset;
+ return (__force void *)va;
+ }
+
+ if (da >= dev_addr && (da + size) <= (dev_addr + mem_size)) {
+ offset = da - dev_addr;
+ va = core->mem[i].cpu_addr + offset;
+ return (__force void *)va;
+ }
+ }
+
+ /* Assume it is DDR region and return da */
+ return map_physmem(da, size, MAP_NOCACHE);
+}
+
+static int k3_r5f_init(struct udevice *dev)
+{
+ return 0;
+}
+
+static int k3_r5f_reset(struct udevice *dev)
+{
+ return 0;
+}
+
+static const struct dm_rproc_ops k3_r5f_rproc_ops = {
+ .init = k3_r5f_init,
+ .reset = k3_r5f_reset,
+ .start = k3_r5f_start,
+ .stop = k3_r5f_stop,
+ .load = k3_r5f_load,
+ .device_to_virt = k3_r5f_da_to_va,
+};
+
+static int k3_r5f_rproc_configure(struct k3_r5f_core *core)
+{
+ struct k3_r5f_cluster *cluster = core->cluster;
+ u32 set_cfg = 0, clr_cfg = 0, cfg, ctrl, sts;
+ u64 boot_vec = 0;
+ int ret;
+
+ dev_dbg(dev, "%s\n", __func__);
+
+ ret = ti_sci_proc_request(&core->tsp);
+ if (ret < 0)
+ return ret;
+
+ /* Do not touch boot vector now. Load will take care of it. */
+ clr_cfg |= PROC_BOOT_CFG_FLAG_GEN_IGN_BOOTVECTOR;
+
+ ret = ti_sci_proc_get_status(&core->tsp, &boot_vec, &cfg, &ctrl, &sts);
+ if (ret)
+ goto out;
+
+ /* Sanity check for Lockstep mode */
+ if (cluster->mode && is_primary_core(core) &&
+ !(sts & PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED)) {
+ dev_err(core->dev, "LockStep mode not permitted on this device\n");
+ ret = -EINVAL;
+ goto out;
+ }
+
+ /* Primary core only configuration */
+ if (is_primary_core(core)) {
+ /* always enable ARM mode */
+ clr_cfg |= PROC_BOOT_CFG_FLAG_R5_TEINIT;
+ if (cluster->mode == CLUSTER_MODE_LOCKSTEP)
+ set_cfg |= PROC_BOOT_CFG_FLAG_R5_LOCKSTEP;
+ else
+ clr_cfg |= PROC_BOOT_CFG_FLAG_R5_LOCKSTEP;
+ }
+
+ if (core->atcm_enable)
+ set_cfg |= PROC_BOOT_CFG_FLAG_R5_ATCM_EN;
+ else
+ clr_cfg |= PROC_BOOT_CFG_FLAG_R5_ATCM_EN;
+
+ if (core->btcm_enable)
+ set_cfg |= PROC_BOOT_CFG_FLAG_R5_BTCM_EN;
+ else
+ clr_cfg |= PROC_BOOT_CFG_FLAG_R5_BTCM_EN;
+
+ if (core->loczrama)
+ set_cfg |= PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE;
+ else
+ clr_cfg |= PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE;
+
+ ret = k3_r5f_core_halt(core);
+ if (ret)
+ goto out;
+
+ ret = ti_sci_proc_set_config(&core->tsp, boot_vec, set_cfg, clr_cfg);
+out:
+ ti_sci_proc_release(&core->tsp);
+ return ret;
+}
+
+static int ti_sci_proc_of_to_priv(struct udevice *dev, struct ti_sci_proc *tsp)
+{
+ u32 ids[2];
+ int ret;
+
+ dev_dbg(dev, "%s\n", __func__);
+
+ tsp->sci = ti_sci_get_by_phandle(dev, "ti,sci");
+ if (IS_ERR(tsp->sci)) {
+ dev_err(dev, "ti_sci get failed: %ld\n", PTR_ERR(tsp->sci));
+ return PTR_ERR(tsp->sci);
+ }
+
+ ret = dev_read_u32_array(dev, "ti,sci-proc-ids", ids, 2);
+ if (ret) {
+ dev_err(dev, "Proc IDs not populated %d\n", ret);
+ return ret;
+ }
+
+ tsp->ops = &tsp->sci->ops.proc_ops;
+ tsp->proc_id = ids[0];
+ tsp->host_id = ids[1];
+ tsp->dev_id = dev_read_u32_default(dev, "ti,sci-dev-id",
+ TI_SCI_RESOURCE_NULL);
+ if (tsp->dev_id == TI_SCI_RESOURCE_NULL) {
+ dev_err(dev, "Device ID not populated %d\n", ret);
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static int k3_r5f_of_to_priv(struct k3_r5f_core *core)
+{
+ int ret;
+
+ dev_dbg(dev, "%s\n", __func__);
+
+ core->atcm_enable = dev_read_u32_default(core->dev, "atcm-enable", 0);
+ core->btcm_enable = dev_read_u32_default(core->dev, "btcm-enable", 1);
+ core->loczrama = dev_read_u32_default(core->dev, "loczrama", 1);
+
+ ret = ti_sci_proc_of_to_priv(core->dev, &core->tsp);
+ if (ret)
+ return ret;
+
+ ret = reset_get_by_index(core->dev, 0, &core->reset);
+ if (ret) {
+ dev_err(core->dev, "Reset lines not available: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int k3_r5f_core_of_get_memories(struct k3_r5f_core *core)
+{
+ static const char * const mem_names[] = {"atcm", "btcm"};
+ struct udevice *dev = core->dev;
+ int i;
+
+ dev_dbg(dev, "%s\n", __func__);
+
+ core->num_mems = ARRAY_SIZE(mem_names);
+ core->mem = calloc(core->num_mems, sizeof(*core->mem));
+ if (!core->mem)
+ return -ENOMEM;
+
+ for (i = 0; i < core->num_mems; i++) {
+ core->mem[i].bus_addr = dev_read_addr_size_name(dev,
+ mem_names[i],
+ (fdt_addr_t *)&core->mem[i].size);
+ if (core->mem[i].bus_addr == FDT_ADDR_T_NONE) {
+ dev_err(dev, "%s bus address not found\n",
+ mem_names[i]);
+ return -EINVAL;
+ }
+ core->mem[i].cpu_addr = map_physmem(core->mem[i].bus_addr,
+ core->mem[i].size,
+ MAP_NOCACHE);
+ if (!strcmp(mem_names[i], "atcm")) {
+ core->mem[i].dev_addr = core->loczrama ?
+ 0 : K3_R5_TCM_DEV_ADDR;
+ } else {
+ core->mem[i].dev_addr = core->loczrama ?
+ K3_R5_TCM_DEV_ADDR : 0;
+ }
+
+ dev_dbg(dev, "memory %8s: bus addr %pa size 0x%zx va %p da 0x%x\n",
+ mem_names[i], &core->mem[i].bus_addr,
+ core->mem[i].size, core->mem[i].cpu_addr,
+ core->mem[i].dev_addr);
+ }
+
+ return 0;
+}
+
+/**
+ * k3_r5f_probe() - Basic probe
+ * @dev: corresponding k3 remote processor device
+ *
+ * Return: 0 if all goes good, else appropriate error message.
+ */
+static int k3_r5f_probe(struct udevice *dev)
+{
+ struct k3_r5f_cluster *cluster = dev_get_priv(dev->parent);
+ struct k3_r5f_core *core = dev_get_priv(dev);
+ bool r_state;
+ int ret;
+
+ dev_dbg(dev, "%s\n", __func__);
+
+ core->dev = dev;
+ ret = k3_r5f_of_to_priv(core);
+ if (ret)
+ return ret;
+
+ core->cluster = cluster;
+ /* Assume Primary core gets probed first */
+ if (!cluster->cores[0])
+ cluster->cores[0] = core;
+ else
+ cluster->cores[1] = core;
+
+ ret = k3_r5f_core_of_get_memories(core);
+ if (ret) {
+ dev_err(dev, "Rproc getting internal memories failed\n");
+ return ret;
+ }
+
+ ret = core->tsp.sci->ops.dev_ops.is_on(core->tsp.sci, core->tsp.dev_id,
+ &r_state, &core->in_use);
+ if (ret)
+ return ret;
+
+ if (core->in_use) {
+ dev_info(dev, "Core %d is already in use. No rproc commands work\n",
+ core->tsp.proc_id);
+ return 0;
+ }
+
+ /* Make sure Local reset is asserted. Redundant? */
+ reset_assert(&core->reset);
+
+ ret = k3_r5f_rproc_configure(core);
+ if (ret) {
+ dev_err(dev, "rproc configure failed %d\n", ret);
+ return ret;
+ }
+
+ dev_dbg(dev, "Remoteproc successfully probed\n");
+
+ return 0;
+}
+
+static int k3_r5f_remove(struct udevice *dev)
+{
+ struct k3_r5f_core *core = dev_get_priv(dev);
+
+ free(core->mem);
+
+ ti_sci_proc_release(&core->tsp);
+
+ return 0;
+}
+
+static const struct udevice_id k3_r5f_rproc_ids[] = {
+ { .compatible = "ti,am654-r5f"},
+ { .compatible = "ti,j721e-r5f"},
+ {}
+};
+
+U_BOOT_DRIVER(k3_r5f_rproc) = {
+ .name = "k3_r5f_rproc",
+ .of_match = k3_r5f_rproc_ids,
+ .id = UCLASS_REMOTEPROC,
+ .ops = &k3_r5f_rproc_ops,
+ .probe = k3_r5f_probe,
+ .remove = k3_r5f_remove,
+ .priv_auto_alloc_size = sizeof(struct k3_r5f_core),
+};
+
+static int k3_r5f_cluster_probe(struct udevice *dev)
+{
+ struct k3_r5f_cluster *cluster = dev_get_priv(dev);
+
+ dev_dbg(dev, "%s\n", __func__);
+
+ cluster->mode = dev_read_u32_default(dev, "lockstep-mode",
+ CLUSTER_MODE_LOCKSTEP);
+
+ if (device_get_child_count(dev) != 2) {
+ dev_err(dev, "Invalid number of R5 cores");
+ return -EINVAL;
+ }
+
+ dev_dbg(dev, "%s: Cluster successfully probed in %s mode\n",
+ __func__, cluster->mode ? "lockstep" : "split");
+
+ return 0;
+}
+
+static const struct udevice_id k3_r5fss_ids[] = {
+ { .compatible = "ti,am654-r5fss"},
+ { .compatible = "ti,j721e-r5fss"},
+ {}
+};
+
+U_BOOT_DRIVER(k3_r5fss) = {
+ .name = "k3_r5fss",
+ .of_match = k3_r5fss_ids,
+ .id = UCLASS_MISC,
+ .probe = k3_r5f_cluster_probe,
+ .priv_auto_alloc_size = sizeof(struct k3_r5f_cluster),
+};
diff --git a/drivers/remoteproc/ti_sci_proc.h b/drivers/remoteproc/ti_sci_proc.h
index ccfc39e..f8299d1 100644
--- a/drivers/remoteproc/ti_sci_proc.h
+++ b/drivers/remoteproc/ti_sci_proc.h
@@ -19,12 +19,14 @@
* @proc_id: processor id for the consumer remoteproc device
* @host_id: host id to pass the control over for this consumer remoteproc
* device
+ * @dev_id: Device ID as identified by system controller.
*/
struct ti_sci_proc {
const struct ti_sci_handle *sci;
const struct ti_sci_proc_ops *ops;
u8 proc_id;
u8 host_id;
+ u16 dev_id;
};
static inline int ti_sci_proc_request(struct ti_sci_proc *tsp)
@@ -118,4 +120,29 @@
return ret;
}
+static inline int ti_sci_proc_power_domain_on(struct ti_sci_proc *tsp)
+{
+ int ret;
+
+ debug("%s: dev_id = %d\n", __func__, tsp->dev_id);
+
+ ret = tsp->sci->ops.dev_ops.get_device_exclusive(tsp->sci, tsp->dev_id);
+ if (ret)
+ pr_err("Power-domain on failed for dev = %d\n", tsp->dev_id);
+
+ return ret;
+}
+
+static inline int ti_sci_proc_power_domain_off(struct ti_sci_proc *tsp)
+{
+ int ret;
+
+ debug("%s: dev_id = %d\n", __func__, tsp->dev_id);
+
+ ret = tsp->sci->ops.dev_ops.put_device(tsp->sci, tsp->dev_id);
+ if (ret)
+ pr_err("Power-domain off failed for dev = %d\n", tsp->dev_id);
+
+ return ret;
+}
#endif /* REMOTEPROC_TI_SCI_PROC_H */
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 8dd3213..b8ca2bd 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -67,7 +67,7 @@
config BCM63XX_HSSPI
bool "BCM63XX HSSPI driver"
- depends on ARCH_BMIPS
+ depends on (ARCH_BMIPS || ARCH_BCM6858 || ARCH_BCM63158)
help
Enable the BCM6328 HSSPI driver. This driver can be used to
access the SPI NOR flash on platforms embedding this Broadcom
diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c
index 4f527fa7..e82b80c 100644
--- a/drivers/spi/bcm63xx_hsspi.c
+++ b/drivers/spi/bcm63xx_hsspi.c
@@ -120,9 +120,9 @@
/* clock polarity */
if (mode & SPI_CPOL)
- setbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK);
+ setbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK);
else
- clrbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK);
+ clrbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK);
return 0;
}
@@ -146,7 +146,7 @@
set = DIV_ROUND_UP(2048, set);
set &= SPI_PFL_CLK_FREQ_MASK;
set |= SPI_PFL_CLK_RSTLOOP_MASK;
- writel_be(set, priv->regs + SPI_PFL_CLK_REG(plat->cs));
+ writel(set, priv->regs + SPI_PFL_CLK_REG(plat->cs));
/* profile signal */
set = 0;
@@ -164,7 +164,7 @@
if (priv->speed > SPI_MAX_SYNC_CLOCK)
set |= SPI_PFL_SIG_ASYNCIN_MASK;
- clrsetbits_be32(priv->regs + SPI_PFL_SIG_REG(plat->cs), clr, set);
+ clrsetbits_32(priv->regs + SPI_PFL_SIG_REG(plat->cs), clr, set);
/* global control */
set = 0;
@@ -182,13 +182,13 @@
else
set |= BIT(!plat->cs);
- clrsetbits_be32(priv->regs + SPI_CTL_REG, clr, set);
+ clrsetbits_32(priv->regs + SPI_CTL_REG, clr, set);
}
static void bcm63xx_hsspi_deactivate_cs(struct bcm63xx_hsspi_priv *priv)
{
/* restore cs polarities */
- clrsetbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CS_POL_MASK,
+ clrsetbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CS_POL_MASK,
priv->cs_pols);
}
@@ -247,7 +247,7 @@
SPI_PFL_MODE_MDWRSZ_MASK;
if (plat->mode & SPI_3WIRE)
val |= SPI_PFL_MODE_3WIRE_MASK;
- writel_be(val, priv->regs + SPI_PFL_MODE_REG(plat->cs));
+ writel(val, priv->regs + SPI_PFL_MODE_REG(plat->cs));
/* transfer loop */
while (data_bytes > 0) {
@@ -262,7 +262,7 @@
}
/* set fifo operation */
- writew_be(opcode | (curr_step & HSSPI_FIFO_OP_BYTES_MASK),
+ writew(cpu_to_be16(opcode | (curr_step & HSSPI_FIFO_OP_BYTES_MASK)),
priv->regs + HSSPI_FIFO_OP_REG);
/* issue the transfer */
@@ -271,10 +271,10 @@
SPI_CMD_PFL_MASK;
val |= (!plat->cs << SPI_CMD_SLAVE_SHIFT) &
SPI_CMD_SLAVE_MASK;
- writel_be(val, priv->regs + SPI_CMD_REG);
+ writel(val, priv->regs + SPI_CMD_REG);
/* wait for completion */
- ret = wait_for_bit_be32(priv->regs + SPI_STAT_REG,
+ ret = wait_for_bit_32(priv->regs + SPI_STAT_REG,
SPI_STAT_SRCBUSY_MASK, false,
1000, false);
if (ret) {
@@ -349,48 +349,47 @@
return ret;
ret = clk_enable(&clk);
- if (ret < 0)
+ if (ret < 0 && ret != -ENOSYS)
return ret;
ret = clk_free(&clk);
- if (ret < 0)
+ if (ret < 0 && ret != -ENOSYS)
return ret;
/* get clock rate */
ret = clk_get_by_name(dev, "pll", &clk);
- if (ret < 0)
+ if (ret < 0 && ret != -ENOSYS)
return ret;
priv->clk_rate = clk_get_rate(&clk);
ret = clk_free(&clk);
- if (ret < 0)
+ if (ret < 0 && ret != -ENOSYS)
return ret;
/* perform reset */
ret = reset_get_by_index(dev, 0, &rst_ctl);
- if (ret < 0)
- return ret;
-
- ret = reset_deassert(&rst_ctl);
- if (ret < 0)
- return ret;
+ if (ret >= 0) {
+ ret = reset_deassert(&rst_ctl);
+ if (ret < 0)
+ return ret;
+ }
ret = reset_free(&rst_ctl);
if (ret < 0)
return ret;
/* initialize hardware */
- writel_be(0, priv->regs + SPI_IR_MASK_REG);
+ writel(0, priv->regs + SPI_IR_MASK_REG);
/* clear pending interrupts */
- writel_be(SPI_IR_CLEAR_ALL, priv->regs + SPI_IR_STAT_REG);
+ writel(SPI_IR_CLEAR_ALL, priv->regs + SPI_IR_STAT_REG);
/* enable clk gate */
- setbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_GATE_MASK);
+ setbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_GATE_MASK);
/* read default cs polarities */
- priv->cs_pols = readl_be(priv->regs + SPI_CTL_REG) &
+ priv->cs_pols = readl(priv->regs + SPI_CTL_REG) &
SPI_CTL_CS_POL_MASK;
return 0;
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 56e2a04..2498f0e 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -440,6 +440,8 @@
goto err0;
}
+ dwc3_phy_setup(dwc);
+
ret = dwc3_core_soft_reset(dwc);
if (ret)
goto err0;
@@ -514,8 +516,6 @@
dwc3_writel(dwc->regs, DWC3_GCTL, reg);
- dwc3_phy_setup(dwc);
-
ret = dwc3_alloc_scratch_buffers(dwc);
if (ret)
goto err0;
diff --git a/env/Kconfig b/env/Kconfig
index 74db2f3..e4ba12e 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -473,6 +473,7 @@
default 0x88000 if ARCH_SUNXI
default 0xE0000 if ARCH_ZYNQ
default 0x1E00000 if ARCH_ZYNQMP
+ default 0x7F40000 if ARCH_VERSAL
default 0 if ARC
default 0x140000 if ARCH_AT91
default 0x260000 if ARCH_OMAP2PLUS
@@ -491,8 +492,8 @@
config ENV_SECT_SIZE
hex "Environment Sector-Size"
- depends on (!ENV_IS_NOWHERE && (ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_OMAP2PLUS || ARCH_AT91) )|| ARCH_STM32MP
- default 0x40000 if ARCH_ZYNQMP
+ depends on (!ENV_IS_NOWHERE && (ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARCH_OMAP2PLUS || ARCH_AT91) )|| ARCH_STM32MP
+ default 0x40000 if ARCH_ZYNQMP || ARCH_VERSAL
default 0x20000 if ARCH_ZYNQ || ARCH_OMAP2PLUS || ARCH_AT91
help
Size of the sector containing the environment.
diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index 29cae8d..9e1b842 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -301,10 +301,20 @@
return 0;
}
-/*
+/**
+ * get_contents() - read from file
+ *
* Read at most 'maxsize' bytes from 'pos' in the file associated with 'dentptr'
- * into 'buffer'.
- * Update the number of bytes read in *gotsize or return -1 on fatal errors.
+ * into 'buffer'. Update the number of bytes read in *gotsize or return -1 on
+ * fatal errors.
+ *
+ * @mydata: file system description
+ * @dentprt: directory entry pointer
+ * @pos: position from where to read
+ * @buffer: buffer into which to read
+ * @maxsize: maximum number of bytes to read
+ * @gotsize: number of bytes actually read
+ * Return: -1 on error, otherwise 0
*/
static int get_contents(fsdata *mydata, dir_entry *dentptr, loff_t pos,
__u8 *buffer, loff_t maxsize, loff_t *gotsize)
@@ -335,8 +345,8 @@
curclust = get_fatent(mydata, curclust);
if (CHECK_CLUST(curclust, mydata->fatsize)) {
debug("curclust: 0x%x\n", curclust);
- debug("Invalid FAT entry\n");
- return 0;
+ printf("Invalid FAT entry\n");
+ return -1;
}
actsize += bytesperclust;
}
@@ -354,7 +364,7 @@
tmp_buffer = malloc_cache_aligned(actsize);
if (!tmp_buffer) {
debug("Error: allocating buffer\n");
- return -ENOMEM;
+ return -1;
}
if (get_cluster(mydata, curclust, tmp_buffer, actsize) != 0) {
@@ -374,8 +384,8 @@
curclust = get_fatent(mydata, curclust);
if (CHECK_CLUST(curclust, mydata->fatsize)) {
debug("curclust: 0x%x\n", curclust);
- debug("Invalid FAT entry\n");
- return 0;
+ printf("Invalid FAT entry\n");
+ return -1;
}
}
@@ -390,8 +400,8 @@
goto getit;
if (CHECK_CLUST(newclust, mydata->fatsize)) {
debug("curclust: 0x%x\n", newclust);
- debug("Invalid FAT entry\n");
- return 0;
+ printf("Invalid FAT entry\n");
+ return -1;
}
endclust = newclust;
actsize += bytesperclust;
@@ -418,7 +428,7 @@
if (CHECK_CLUST(curclust, mydata->fatsize)) {
debug("curclust: 0x%x\n", curclust);
printf("Invalid FAT entry\n");
- return 0;
+ return -1;
}
actsize = bytesperclust;
endclust = curclust;
diff --git a/include/configs/am335x_guardian.h b/include/configs/am335x_guardian.h
index 8bde198..b45b8d2 100644
--- a/include/configs/am335x_guardian.h
+++ b/include/configs/am335x_guardian.h
@@ -16,10 +16,14 @@
#define CONFIG_TIMESTAMP
#endif
+#define CONFIG_SYS_BOOTM_LEN (16 << 20)
+
/* Clock Defines */
#define V_OSCK 24000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
#ifndef CONFIG_SPL_BUILD
#define MEM_LAYOUT_ENV_SETTINGS \
@@ -30,7 +34,6 @@
"ramdisk_addr_r=0x88080000\0" \
#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 0) \
func(UBIFS, ubifs, 0) \
func(PXE, pxe, na) \
func(DHCP, dhcp, na)
@@ -44,11 +47,12 @@
MEM_LAYOUT_ENV_SETTINGS \
BOOTENV \
"bootlimit=3\0" \
+ "bootubivol=rootfs\0" \
"altbootcmd=" \
"setenv boot_config \"extlinux-rollback.conf\"; " \
"run distro_bootcmd\0"
-#endif /* CONFIG_SPL_BUILD */
+#endif /* ! CONFIG_SPL_BUILD */
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
@@ -65,9 +69,6 @@
#define CONFIG_SYS_BOOTCOUNT_LE
#ifdef CONFIG_NAND
-#define CONFIG_ENV_OFFSET 0x300000
-#define CONFIG_ENV_OFFSET_REDUND 0x340000
-#define CONFIG_ENV_SIZE 0x040000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h
index 0249a20..1149d55 100644
--- a/include/configs/am65x_evm.h
+++ b/include/configs/am65x_evm.h
@@ -12,6 +12,7 @@
#include <linux/sizes.h>
#include <config_distro_bootcmd.h>
#include <environment/ti/mmc.h>
+#include <environment/ti/k3_rproc.h>
#define CONFIG_ENV_SIZE (128 << 10)
@@ -98,12 +99,20 @@
"${bootdir}/${name_fit}\0" \
"partitions=" PARTS_DEFAULT
+#ifdef DEFAULT_RPROCS
+#undef DEFAULT_RPROCS
+#endif
+#define DEFAULT_RPROCS "" \
+ "0 /lib/firmware/am65x-mcu-r5f0_0-fw " \
+ "1 /lib/firmware/am65x-mcu-r5f0_1-fw "
+
/* Incorporate settings into the U-Boot environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_MMC_TI_ARGS \
DEFAULT_FIT_TI_ARGS \
EXTRA_ENV_AM65X_BOARD_SETTINGS \
- EXTRA_ENV_AM65X_BOARD_SETTINGS_MMC
+ EXTRA_ENV_AM65X_BOARD_SETTINGS_MMC \
+ EXTRA_ENV_RPROC_SETTINGS
/* MMC ENV related defines */
#ifdef CONFIG_ENV_IS_IN_MMC
diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h
index dacf36b..fe45917 100644
--- a/include/configs/apalis-tk1.h
+++ b/include/configs/apalis-tk1.h
@@ -138,8 +138,6 @@
#define CONFIG_CMD_TIME
-#define CONFIG_SYS_BOOT_RAMDISK_HIGH
-
#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
index 5fe77ef..dbe226b 100644
--- a/include/configs/j721e_evm.h
+++ b/include/configs/j721e_evm.h
@@ -12,6 +12,7 @@
#include <linux/sizes.h>
#include <config_distro_bootcmd.h>
#include <environment/ti/mmc.h>
+#include <environment/ti/k3_rproc.h>
#define CONFIG_ENV_SIZE (128 << 10)
@@ -87,11 +88,22 @@
"get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \
"${bootdir}/${name_kern}\0"
+#ifdef DEFAULT_RPROCS
+#undef DEFAULT_RPROCS
+#endif
+#define DEFAULT_RPROCS "" \
+ "3 /lib/firmware/j7-main-r5f0_1-fw " \
+ "4 /lib/firmware/j7-main-r5f1_0-fw " \
+ "6 /lib/firmware/j7-c66_0-fw " \
+ "7 /lib/firmware/j7-c66_1-fw " \
+ "8 /lib/firmware/j7-c71_0-fw "
+
/* Incorporate settings into the U-Boot environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_MMC_TI_ARGS \
EXTRA_ENV_J721E_BOARD_SETTINGS \
- EXTRA_ENV_J721E_BOARD_SETTINGS_MMC
+ EXTRA_ENV_J721E_BOARD_SETTINGS_MMC \
+ EXTRA_ENV_RPROC_SETTINGS
/* Now for the remaining common defines */
#include <configs/ti_armv7_common.h>
diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index 814fec5..f1d0def 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -13,6 +13,8 @@
/* MicroBlaze CPU */
#define MICROBLAZE_V5 1
+#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024)
+
/* linear and spi flash memory */
#ifdef XILINX_FLASH_START
#define FLASH
@@ -100,6 +102,9 @@
#endif /* !SPIFLASH */
#endif /* !FLASH */
+#define XILINX_USE_ICACHE 1
+#define XILINX_USE_DCACHE 1
+
#if defined(XILINX_USE_ICACHE)
# define CONFIG_ICACHE
#else
@@ -152,9 +157,6 @@
"setenv stdin serial\0"
#endif
-/* Enable flat device tree support */
-#define CONFIG_LMB 1
-
#if defined(CONFIG_XILINX_AXIEMAC)
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1
#endif
diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h
index c34e785..7a54fe3 100644
--- a/include/configs/tao3530.h
+++ b/include/configs/tao3530.h
@@ -114,7 +114,7 @@
"bootm ${loadaddr}\0" \
#define CONFIG_BOOTCOMMAND \
- "if mmc rescan ${mmcdev}; then " \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index 2de6bc2..6d15304 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -60,7 +60,7 @@
"do;" \
"setenv overlaystring ${overlaystring}'#'${overlay};" \
"done;\0" \
- "run_fit=bootm ${loadaddr}#${fdtfile}${overlaystring}\0" \
+ "run_fit=bootm ${addr_fit}#${fdtfile}${overlaystring}\0" \
"loadfit=run args_mmc; run run_fit;\0" \
/*
diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h
index 296f450..f426127 100644
--- a/include/configs/xilinx_versal.h
+++ b/include/configs/xilinx_versal.h
@@ -52,6 +52,26 @@
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_MAXARGS 64
+#if defined(CONFIG_CMD_DFU)
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x1800000
+#define DFU_DEFAULT_POLL_TIMEOUT 300
+#define CONFIG_THOR_RESET_OFF
+#define DFU_ALT_INFO_RAM \
+ "dfu_ram_info=" \
+ "setenv dfu_alt_info " \
+ "Image ram $kernel_addr_r $kernel_size_r\\\\;" \
+ "system.dtb ram $fdt_addr_r $fdt_size_r\0" \
+ "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
+ "thor_ram=run dfu_ram_info && thordown 0 ram 0\0"
+
+#define DFU_ALT_INFO \
+ DFU_ALT_INFO_RAM
+#endif
+
+#if !defined(DFU_ALT_INFO)
+# define DFU_ALT_INFO
+#endif
+
/* Ethernet driver */
#if defined(CONFIG_ZYNQ_GEM)
# define CONFIG_NET_MULTI
@@ -65,13 +85,14 @@
#define ENV_MEM_LAYOUT_SETTINGS \
"fdt_high=10000000\0" \
- "initrd_high=10000000\0" \
"fdt_addr_r=0x40000000\0" \
+ "fdt_size_r=0x400000\0" \
"pxefile_addr_r=0x10000000\0" \
"kernel_addr_r=0x18000000\0" \
- "scriptaddr=0x02000000\0" \
+ "kernel_size_r=0x10000000\0" \
+ "scriptaddr=0x20000000\0" \
"ramdisk_addr_r=0x02100000\0" \
- "script_offset_f=0x3f80000\0" \
+ "script_offset_f=0x7F80000\0" \
"script_size_f=0x80000\0"
#if defined(CONFIG_MMC_SDHCI_ZYNQ)
@@ -94,9 +115,29 @@
#define BOOTENV_DEV_NAME_XSPI(devtypeu, devtypel, instance) \
"xspi "
+#define BOOT_TARGET_DEVICES_JTAG(func) func(JTAG, jtag, na)
+
+#define BOOTENV_DEV_JTAG(devtypeu, devtypel, instance) \
+ "bootcmd_jtag=source $scriptaddr; echo SCRIPT FAILED: continuing...;\0"
+
+#define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \
+ "jtag "
+
+#define BOOT_TARGET_DEVICES_DFU_USB(func) func(DFU_USB, dfu_usb, 0)
+
+#define BOOTENV_DEV_DFU_USB(devtypeu, devtypel, instance) \
+ "bootcmd_dfu_usb=setenv dfu_alt_info boot.scr ram $scriptaddr " \
+ "$script_size_f; dfu 0 ram 0 && source $scriptaddr; " \
+ "echo SCRIPT FAILED: continuing...;\0"
+
+#define BOOTENV_DEV_NAME_DFU_USB(devtypeu, devtypel, instance) \
+ "dfu_usb "
+
#define BOOT_TARGET_DEVICES(func) \
+ BOOT_TARGET_DEVICES_JTAG(func) \
BOOT_TARGET_DEVICES_MMC(func) \
BOOT_TARGET_DEVICES_XSPI(func) \
+ BOOT_TARGET_DEVICES_DFU_USB(func) \
func(PXE, pxe, na) \
func(DHCP, dhcp, na)
@@ -106,7 +147,8 @@
#ifndef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
ENV_MEM_LAYOUT_SETTINGS \
- BOOTENV
+ BOOTENV \
+ DFU_ALT_INFO
#endif
#endif /* __XILINX_VERSAL_H */
diff --git a/include/configs/xilinx_versal_mini.h b/include/configs/xilinx_versal_mini.h
index d30a697..ee305e0 100644
--- a/include/configs/xilinx_versal_mini.h
+++ b/include/configs/xilinx_versal_mini.h
@@ -26,4 +26,7 @@
#undef CONFIG_BOOTP_BOOTFILESIZE
#undef CONFIG_BOOTP_MAY_FAIL
+#undef CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_CBSIZE 1024
+
#endif /* __CONFIG_VERSAL_MINI_H */
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index a1c55a8..ee1ceeb 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -109,11 +109,10 @@
#define ENV_MEM_LAYOUT_SETTINGS \
"fdt_high=10000000\0" \
- "initrd_high=10000000\0" \
"fdt_addr_r=0x40000000\0" \
"pxefile_addr_r=0x10000000\0" \
"kernel_addr_r=0x18000000\0" \
- "scriptaddr=0x02000000\0" \
+ "scriptaddr=0x20000000\0" \
"ramdisk_addr_r=0x02100000\0" \
"script_offset_f=0x3e80000\0" \
"script_size_f=0x80000\0" \
@@ -176,7 +175,16 @@
#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
#devtypel #instance " "
+#define BOOT_TARGET_DEVICES_JTAG(func) func(JTAG, jtag, na)
+
+#define BOOTENV_DEV_JTAG(devtypeu, devtypel, instance) \
+ "bootcmd_jtag=source $scriptaddr; echo SCRIPT FAILED: continuing...;\0"
+
+#define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \
+ "jtag "
+
#define BOOT_TARGET_DEVICES(func) \
+ BOOT_TARGET_DEVICES_JTAG(func) \
BOOT_TARGET_DEVICES_MMC(func) \
BOOT_TARGET_DEVICES_QSPI(func) \
BOOT_TARGET_DEVICES_NAND(func) \
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index ae08ebf..b6c9f2c 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -111,13 +111,13 @@
#else
#ifdef CONFIG_CMD_MMC
-#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
+#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1)
#else
#define BOOT_TARGET_DEVICES_MMC(func)
#endif
#ifdef CONFIG_CMD_USB
-#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
+#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) func(USB, usb, 1)
#else
#define BOOT_TARGET_DEVICES_USB(func)
#endif
@@ -152,15 +152,9 @@
# define BOOT_TARGET_DEVICES_NOR(func)
#endif
-#define BOOTENV_DEV_XILINX(devtypeu, devtypel, instance) \
- "bootcmd_xilinx=run $modeboot\0"
-
-#define BOOTENV_DEV_NAME_XILINX(devtypeu, devtypel, instance) \
- "xilinx "
-
#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \
"bootcmd_qspi=sf probe 0 0 0 && " \
- "sf read $scriptaddr $script_offset_f $script_size_f && " \
+ "sf read ${scriptaddr} ${script_offset_f} ${script_size_f} && " \
"source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0"
#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \
@@ -168,14 +162,15 @@
#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
"bootcmd_nand=nand info && " \
- "nand read $scriptaddr $script_offset_f $script_size_f && " \
+ "nand read ${scriptaddr} ${script_offset_f} ${script_size_f} && " \
"source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0"
#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
"nand "
#define BOOTENV_DEV_NOR(devtypeu, devtypel, instance) \
- "bootcmd_nor=cp.b $scropt_offset_nor $scriptaddr $script_size_f && " \
+ "script_offset_nor=0xE2FC0000\0" \
+ "bootcmd_nor=cp.b ${script_offset_nor} ${scriptaddr} ${script_size_f} && " \
"source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0"
#define BOOTENV_DEV_NAME_NOR(devtypeu, devtypel, instance) \
@@ -188,8 +183,7 @@
BOOT_TARGET_DEVICES_NOR(func) \
BOOT_TARGET_DEVICES_USB(func) \
BOOT_TARGET_DEVICES_PXE(func) \
- BOOT_TARGET_DEVICES_DHCP(func) \
- func(XILINX, xilinx, na)
+ BOOT_TARGET_DEVICES_DHCP(func)
#include <config_distro_bootcmd.h>
#endif /* CONFIG_SPL_BUILD */
@@ -197,72 +191,31 @@
/* Default environment */
#ifndef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
- "fit_image=fit.itb\0" \
- "load_addr=0x2000000\0" \
- "fit_size=0x800000\0" \
- "flash_off=0x100000\0" \
- "nor_flash_off=0xE2100000\0" \
"fdt_high=0x20000000\0" \
"initrd_high=0x20000000\0" \
"scriptaddr=0x20000\0" \
- "script_offser_nor=0xE2FC0000\0" \
"script_offset_f=0xFC0000\0" \
"script_size_f=0x40000\0" \
- "loadbootenv_addr=0x2000000\0" \
"fdt_addr_r=0x1f00000\0" \
"pxefile_addr_r=0x2000000\0" \
"kernel_addr_r=0x2000000\0" \
"scriptaddr=0x3000000\0" \
"ramdisk_addr_r=0x3100000\0" \
- "bootenv=uEnv.txt\0" \
- "bootenv_dev=mmc\0" \
- "loadbootenv=load ${bootenv_dev} 0 ${loadbootenv_addr} ${bootenv}\0" \
- "importbootenv=echo Importing environment from ${bootenv_dev} ...; " \
- "env import -t ${loadbootenv_addr} $filesize\0" \
- "bootenv_existence_test=test -e ${bootenv_dev} 0 /${bootenv}\0" \
- "setbootenv=if env run bootenv_existence_test; then " \
- "if env run loadbootenv; then " \
- "env run importbootenv; " \
- "fi; " \
- "fi; \0" \
- "sd_loadbootenv=setenv bootenv_dev mmc && " \
- "run setbootenv \0" \
- "usb_loadbootenv=setenv bootenv_dev usb && usb start && run setbootenv \0" \
- "preboot=if test $modeboot = sdboot; then " \
- "run sd_loadbootenv; " \
- "echo Checking if uenvcmd is set ...; " \
- "if test -n $uenvcmd; then " \
- "echo Running uenvcmd ...; " \
- "run uenvcmd; " \
- "fi; " \
- "fi; \0" \
- "norboot=echo Copying FIT from NOR flash to RAM... && " \
- "cp.b ${nor_flash_off} ${load_addr} ${fit_size} && " \
- "bootm ${load_addr}\0" \
- "sdboot=echo Copying FIT from SD to RAM... && " \
- "load mmc 0 ${load_addr} ${fit_image} && " \
- "bootm ${load_addr}\0" \
- "jtagboot=echo TFTPing FIT to RAM... && " \
- "tftpboot ${load_addr} ${fit_image} && " \
- "bootm ${load_addr}\0" \
- "usbboot=if usb start; then " \
- "echo Copying FIT from USB to RAM... && " \
- "load usb 0 ${load_addr} ${fit_image} && " \
- "bootm ${load_addr}; fi\0" \
- DFU_ALT_INFO \
- BOOTENV
+ DFU_ALT_INFO \
+ BOOTENV
#endif
/* Miscellaneous configurable options */
#define CONFIG_CLOCKS
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
+#define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0
#define CONFIG_SYS_MEMTEST_END 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
@@ -274,6 +227,8 @@
/* Boot FreeBSD/vxWorks from an ELF image */
#define CONFIG_SYS_MMC_MAX_DEVICE 1
+#undef CONFIG_BOOTM_NETBSD
+
/* MMC support */
#ifdef CONFIG_MMC_SDHCI_ZYNQ
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
diff --git a/include/dm/device.h b/include/dm/device.h
index d121042..defda0a 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -405,6 +405,15 @@
int device_get_child(struct udevice *parent, int index, struct udevice **devp);
/**
+ * device_get_child_count() - Get the available child count of a device
+ *
+ * Returns the number of children to a device.
+ *
+ * @parent: Parent device to check
+ */
+int device_get_child_count(struct udevice *parent);
+
+/**
* device_find_child_by_seq() - Find a child device based on a sequence
*
* This searches for a device with the given seq or req_seq.
diff --git a/include/dt-bindings/reset/mtk-reset.h b/include/dt-bindings/reset/mt7623-reset.h
similarity index 88%
rename from include/dt-bindings/reset/mtk-reset.h
rename to include/dt-bindings/reset/mt7623-reset.h
index 78fcdab..a859a5b 100644
--- a/include/dt-bindings/reset/mtk-reset.h
+++ b/include/dt-bindings/reset/mt7623-reset.h
@@ -6,11 +6,9 @@
#ifndef _DT_BINDINGS_MTK_RESET_H_
#define _DT_BINDINGS_MTK_RESET_H_
-/* ETHSYS */
+/* ETHSYS resets */
#define ETHSYS_PPE_RST 31
-#define ETHSYS_EPHY_RST 24
#define ETHSYS_GMAC_RST 23
-#define ETHSYS_ESW_RST 16
#define ETHSYS_FE_RST 6
#define ETHSYS_MCM_RST 2
#define ETHSYS_SYS_RST 0
diff --git a/include/dt-bindings/reset/mt7629-reset.h b/include/dt-bindings/reset/mt7629-reset.h
new file mode 100644
index 0000000..8f1634f
--- /dev/null
+++ b/include/dt-bindings/reset/mt7629-reset.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ */
+
+#ifndef _DT_BINDINGS_MTK_RESET_H_
+#define _DT_BINDINGS_MTK_RESET_H_
+
+/* PCIe Subsystem resets */
+#define PCIE1_CORE_RST 19
+#define PCIE1_MMIO_RST 20
+#define PCIE1_HRST 21
+#define PCIE1_USER_RST 22
+#define PCIE1_PIPE_RST 23
+#define PCIE0_CORE_RST 27
+#define PCIE0_MMIO_RST 28
+#define PCIE0_HRST 29
+#define PCIE0_USER_RST 30
+#define PCIE0_PIPE_RST 31
+
+/* SSUSB Subsystem resets */
+#define SSUSB_PHY_PWR_RST 3
+#define SSUSB_MAC_PWR_RST 4
+
+/* ETH Subsystem resets */
+#define ETHSYS_SYS_RST 0
+#define ETHSYS_MCM_RST 2
+#define ETHSYS_HSDMA_RST 5
+#define ETHSYS_FE_RST 6
+#define ETHSYS_ESW_RST 16
+#define ETHSYS_GMAC_RST 23
+#define ETHSYS_EPHY_RST 24
+#define ETHSYS_CRYPTO_RST 29
+#define ETHSYS_PPE_RST 31
+
+#endif /* _DT_BINDINGS_MTK_RESET_H_ */
diff --git a/include/environment/ti/k3_rproc.h b/include/environment/ti/k3_rproc.h
new file mode 100644
index 0000000..3418cb4
--- /dev/null
+++ b/include/environment/ti/k3_rproc.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * rproc environment variable definitions for various TI K3 SoCs.
+ */
+
+#ifndef __TI_RPROC_H
+#define __TI_RPROC_H
+
+/*
+ * should contain a list of <rproc_id fw_name> tuplies,
+ * override in board config files with the actual list
+ */
+#define DEFAULT_RPROCS ""
+
+#ifdef CONFIG_CMD_REMOTEPROC
+#define EXTRA_ENV_RPROC_SETTINGS \
+ "dorprocboot=0\0" \
+ "boot_rprocs=" \
+ "if test ${dorprocboot} -eq 1 && test ${boot} = mmc; then "\
+ "rproc init;" \
+ "run boot_rprocs_mmc;" \
+ "fi;\0" \
+ "rproc_load_and_boot_one=" \
+ "if load mmc ${bootpart} $loadaddr ${rproc_fw}; then " \
+ "if rproc load ${rproc_id} ${loadaddr} ${filesize}; then "\
+ "rproc start ${rproc_id};" \
+ "fi;" \
+ "fi\0" \
+ "boot_rprocs_mmc=" \
+ "env set rproc_id;" \
+ "env set rproc_fw;" \
+ "for i in ${rproc_fw_binaries} ; do " \
+ "if test -z \"${rproc_id}\" ; then " \
+ "env set rproc_id $i;" \
+ "else " \
+ "env set rproc_fw $i;" \
+ "run rproc_load_and_boot_one;" \
+ "env set rproc_id;" \
+ "env set rproc_fw;" \
+ "fi;" \
+ "done\0" \
+ "rproc_fw_binaries=" \
+ DEFAULT_RPROCS \
+ "\0"
+#else
+#define EXTRA_ENV_RPROC_SETTINGS \
+ "boot_rprocs= \0"
+#endif /* CONFIG_CMD_REMOTEPROC */
+
+#endif /* __TI_RPROC_H */
diff --git a/include/phy.h b/include/phy.h
index f4530fa..e50f56b 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -17,6 +17,11 @@
#include <phy_interface.h>
#define PHY_FIXED_ID 0xa5a55a5a
+/*
+ * There is no actual id for this.
+ * This is just a dummy id for gmii2rgmmi converter.
+ */
+#define PHY_GMII2RGMII_ID 0x5a5a5a5a
#define PHY_MAX_ADDR 32
@@ -391,6 +396,7 @@
int phy_xilinx_init(void);
int phy_mscc_init(void);
int phy_fixed_init(void);
+int phy_xilinx_gmii2rgmii_init(void);
int board_phy_config(struct phy_device *phydev);
int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id);
diff --git a/include/remoteproc.h b/include/remoteproc.h
index 4987194..046cd9e 100644
--- a/include/remoteproc.h
+++ b/include/remoteproc.h
@@ -122,9 +122,10 @@
*
* @dev: Remote proc device
* @da: Device address
+ * @size: Size of the memory region @da is pointing to
* @return virtual address.
*/
- void * (*device_to_virt)(struct udevice *dev, ulong da);
+ void * (*device_to_virt)(struct udevice *dev, ulong da, ulong size);
};
/* Accessor */
@@ -214,12 +215,68 @@
int rproc_elf32_sanity_check(ulong addr, ulong size);
/**
+ * rproc_elf64_sanity_check() - Verify if an image is a valid ELF32 one
+ *
+ * Check if a valid ELF64 image exists at the given memory location. Verify
+ * basic ELF64 format requirements like magic number and sections size.
+ *
+ * @addr: address of the image to verify
+ * @size: size of the image
+ * @return 0 if the image looks good, else appropriate error value.
+ */
+int rproc_elf64_sanity_check(ulong addr, ulong size);
+
+/**
+ * rproc_elf_sanity_check() - Verify if an image is a valid ELF one
+ *
+ * Check if a valid ELF image exists at the given memory location. Auto
+ * detects ELF32/ELF64 and verifies basic ELF64/ELF32 format requirements
+ * like magic number and sections size.
+ *
+ * @addr: address of the image to verify
+ * @size: size of the image
+ * @return 0 if the image looks good, else appropriate error value.
+ */
+int rproc_elf_sanity_check(ulong addr, ulong size);
+
+/**
* rproc_elf32_load_image() - load an ELF32 image
* @dev: device loading the ELF32 image
* @addr: valid ELF32 image address
+ * @size: size of the image
* @return 0 if the image is successfully loaded, else appropriate error value.
*/
-int rproc_elf32_load_image(struct udevice *dev, unsigned long addr);
+int rproc_elf32_load_image(struct udevice *dev, unsigned long addr, ulong size);
+
+/**
+ * rproc_elf64_load_image() - load an ELF64 image
+ * @dev: device loading the ELF64 image
+ * @addr: valid ELF64 image address
+ * @size: size of the image
+ * @return 0 if the image is successfully loaded, else appropriate error value.
+ */
+int rproc_elf64_load_image(struct udevice *dev, ulong addr, ulong size);
+
+/**
+ * rproc_elf_load_image() - load an ELF image
+ * @dev: device loading the ELF image
+ * @addr: valid ELF image address
+ * @size: size of the image
+ *
+ * Auto detects if the image is ELF32 or ELF64 image and load accordingly.
+ * @return 0 if the image is successfully loaded, else appropriate error value.
+ */
+int rproc_elf_load_image(struct udevice *dev, unsigned long addr, ulong size);
+
+/**
+ * rproc_elf_get_boot_addr() - Get rproc's boot address.
+ * @dev: device loading the ELF image
+ * @addr: valid ELF image address
+ *
+ * This function returns the entry point address of the ELF
+ * image.
+ */
+ulong rproc_elf_get_boot_addr(struct udevice *dev, ulong addr);
#else
static inline int rproc_init(void) { return -ENOSYS; }
static inline int rproc_dev_init(int id) { return -ENOSYS; }
@@ -232,8 +289,21 @@
static inline int rproc_is_running(int id) { return -ENOSYS; }
static inline int rproc_elf32_sanity_check(ulong addr,
ulong size) { return -ENOSYS; }
+static inline int rproc_elf64_sanity_check(ulong addr,
+ ulong size) { return -ENOSYS; }
+static inline int rproc_elf_sanity_check(ulong addr,
+ ulong size) { return -ENOSYS; }
static inline int rproc_elf32_load_image(struct udevice *dev,
- unsigned long addr) { return -ENOSYS; }
+ unsigned long addr, ulong size)
+{ return -ENOSYS; }
+static inline int rproc_elf64_load_image(struct udevice *dev, ulong addr,
+ ulong size)
+{ return -ENOSYS; }
+static inline int rproc_elf_load_image(struct udevice *dev, ulong addr,
+ ulong size)
+{ return -ENOSYS; }
+static inline ulong rproc_elf_get_boot_addr(struct udevice *dev, ulong addr)
+{ return 0; }
#endif
#endif /* _RPROC_H_ */
diff --git a/include/spl.h b/include/spl.h
index 4359636..b5387ef 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -434,6 +434,9 @@
int raw_part,
unsigned long raw_sect);
+int spl_ymodem_load_image(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev);
+
/**
* spl_invoke_atf - boot using an ARM trusted firmware image
*/
diff --git a/include/versalpl.h b/include/versalpl.h
new file mode 100644
index 0000000..b94c82e
--- /dev/null
+++ b/include/versalpl.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2019 Xilinx, Inc,
+ * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
+ */
+
+#ifndef _VERSALPL_H_
+#define _VERSALPL_H_
+
+#include <xilinx.h>
+
+#define VERSAL_PM_LOAD_PDI 0x701
+#define VERSAL_PM_PDI_TYPE 0xF
+
+extern struct xilinx_fpga_op versal_op;
+
+#define XILINX_VERSAL_DESC \
+{ xilinx_versal, csu_dma, 1, &versal_op, 0, &versal_op }
+
+#endif /* _VERSALPL_H_ */
diff --git a/include/wait_bit.h b/include/wait_bit.h
index 82e09da..79da081 100644
--- a/include/wait_bit.h
+++ b/include/wait_bit.h
@@ -72,10 +72,12 @@
BUILD_WAIT_FOR_BIT(8, u8, readb)
BUILD_WAIT_FOR_BIT(le16, u16, readw)
+BUILD_WAIT_FOR_BIT(16, u16, readw)
#ifdef readw_be
BUILD_WAIT_FOR_BIT(be16, u16, readw_be)
#endif
BUILD_WAIT_FOR_BIT(le32, u32, readl)
+BUILD_WAIT_FOR_BIT(32, u32, readl)
#ifdef readl_be
BUILD_WAIT_FOR_BIT(be32, u32, readl_be)
#endif
diff --git a/include/xilinx.h b/include/xilinx.h
index af40bef..ab4537b 100644
--- a/include/xilinx.h
+++ b/include/xilinx.h
@@ -21,6 +21,7 @@
slave_selectmap, /* slave SelectMap (virtex2) */
devcfg, /* devcfg interface (zynq) */
csu_dma, /* csu_dma interface (zynqmp) */
+ cfi, /* CFI interface(versal) */
max_xilinx_iface_type /* insert all new types before this */
} xilinx_iface; /* end, typedef xilinx_iface */
@@ -32,6 +33,7 @@
xilinx_spartan3, /* Spartan-III Family */
xilinx_zynq, /* Zynq Family */
xilinx_zynqmp, /* ZynqMP Family */
+ xilinx_versal, /* Versal Family */
max_xilinx_type /* insert all new types before this */
} xilinx_family; /* end, typedef xilinx_family */
diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h
new file mode 100644
index 0000000..a20cbcd
--- /dev/null
+++ b/include/zynqmp_firmware.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Xilinx Zynq MPSoC Firmware driver
+ *
+ * Copyright (C) 2018-2019 Xilinx, Inc.
+ */
+
+#ifndef _ZYNQMP_FIRMWARE_H_
+#define _ZYNQMP_FIRMWARE_H_
+
+enum pm_api_id {
+ PM_GET_API_VERSION = 1,
+ PM_SET_CONFIGURATION,
+ PM_SECURE_IMAGE = 45,
+};
+
+#define PM_SIP_SVC 0xc2000000
+#define ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD \
+ (PM_SIP_SVC + PM_SECURE_IMAGE)
+
+#define ZYNQMP_PM_VERSION_MAJOR 1
+#define ZYNQMP_PM_VERSION_MINOR 0
+#define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16
+#define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF
+
+#define ZYNQMP_PM_VERSION \
+ ((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \
+ ZYNQMP_PM_VERSION_MINOR)
+
+#define ZYNQMP_PM_VERSION_INVALID ~0
+
+#define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0)
+
+unsigned int zynqmp_firmware_version(void);
+void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size);
+
+#endif /* _ZYNQMP_FIRMWARE_H_ */
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 1920954..5402bc2 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -4361,5 +4361,4 @@
CONFIG_YELLOW_LED
CONFIG_ZLT
CONFIG_ZM7300
-CONFIG_ZYNQ_HISPD_BROKEN
CONFIG_eTSEC_MDIO_BUS
diff --git a/test/dm/bus.c b/test/dm/bus.c
index 93f3acd..1ad45ad 100644
--- a/test/dm/bus.c
+++ b/test/dm/bus.c
@@ -8,6 +8,7 @@
#include <os.h>
#endif
#include <dm.h>
+#include <dm/device.h>
#include <dm/device-internal.h>
#include <dm/test.h>
#include <dm/uclass-internal.h>
@@ -371,7 +372,6 @@
{
struct dm_test_parent_platdata *plat;
struct udevice *bus, *dev;
- int child_count;
/* Check that the bus has no children */
ut_assertok(uclass_find_device(UCLASS_TEST_BUS, 0, &bus));
@@ -380,7 +380,7 @@
ut_assertok(uclass_get_device(UCLASS_TEST_BUS, 0, &bus));
- for (device_find_first_child(bus, &dev), child_count = 0;
+ for (device_find_first_child(bus, &dev);
dev;
device_find_next_child(&dev)) {
/* Check that platform data is allocated */
@@ -399,22 +399,20 @@
ut_asserteq_ptr(plat, dev_get_parent_platdata(dev));
ut_asserteq(1, plat->count);
ut_assertok(device_probe(dev));
- child_count++;
}
- ut_asserteq(3, child_count);
+ ut_asserteq(3, device_get_child_count(bus));
/* Removing the bus should also have no effect (it is still bound) */
device_remove(bus, DM_REMOVE_NORMAL);
- for (device_find_first_child(bus, &dev), child_count = 0;
+ for (device_find_first_child(bus, &dev);
dev;
device_find_next_child(&dev)) {
/* Check that platform data is allocated */
plat = dev_get_parent_platdata(dev);
ut_assert(plat != NULL);
ut_asserteq(1, plat->count);
- child_count++;
}
- ut_asserteq(3, child_count);
+ ut_asserteq(3, device_get_child_count(bus));
/* Unbind all the children */
do {
@@ -425,16 +423,15 @@
/* Now the child platdata should be removed and re-added */
device_probe(bus);
- for (device_find_first_child(bus, &dev), child_count = 0;
+ for (device_find_first_child(bus, &dev);
dev;
device_find_next_child(&dev)) {
/* Check that platform data is allocated */
plat = dev_get_parent_platdata(dev);
ut_assert(plat != NULL);
ut_asserteq(0, plat->count);
- child_count++;
}
- ut_asserteq(3, child_count);
+ ut_asserteq(3, device_get_child_count(bus));
return 0;
}
@@ -480,19 +477,17 @@
{
struct dm_test_parent_platdata *plat;
struct udevice *bus, *dev;
- int child_count;
ut_assertok(uclass_get_device(UCLASS_TEST_BUS, 0, &bus));
- for (device_find_first_child(bus, &dev), child_count = 0;
+ for (device_find_first_child(bus, &dev);
dev;
device_find_next_child(&dev)) {
/* Check that platform data is allocated */
plat = dev_get_parent_platdata(dev);
ut_assert(plat != NULL);
ut_asserteq(1, plat->bind_flag);
- child_count++;
}
- ut_asserteq(3, child_count);
+ ut_asserteq(3, device_get_child_count(bus));
return 0;
}
@@ -503,19 +498,17 @@
{
struct dm_test_parent_platdata *plat;
struct udevice *bus, *dev;
- int child_count;
ut_assertok(uclass_get_device(UCLASS_TEST_BUS, 0, &bus));
- for (device_find_first_child(bus, &dev), child_count = 0;
+ for (device_find_first_child(bus, &dev);
dev;
device_find_next_child(&dev)) {
/* Check that platform data is allocated */
plat = dev_get_parent_platdata(dev);
ut_assert(plat != NULL);
ut_asserteq(2, plat->uclass_bind_flag);
- child_count++;
}
- ut_asserteq(3, child_count);
+ ut_asserteq(3, device_get_child_count(bus));
return 0;
}
@@ -529,14 +522,13 @@
static int dm_test_bus_child_pre_probe_uclass(struct unit_test_state *uts)
{
struct udevice *bus, *dev;
- int child_count;
/*
* See testfdt_drv_probe() which effectively checks that the uclass
* flag is set before that method is called
*/
ut_assertok(uclass_get_device(UCLASS_TEST_BUS, 0, &bus));
- for (device_find_first_child(bus, &dev), child_count = 0;
+ for (device_find_first_child(bus, &dev);
dev;
device_find_next_child(&dev)) {
struct dm_test_priv *priv = dev_get_priv(dev);
@@ -549,9 +541,8 @@
ut_assert(priv != NULL);
ut_asserteq(1, priv->uclass_flag);
ut_asserteq(1, priv->uclass_total);
- child_count++;
}
- ut_asserteq(3, child_count);
+ ut_asserteq(3, device_get_child_count(bus));
return 0;
}
@@ -565,14 +556,13 @@
static int dm_test_bus_child_post_probe_uclass(struct unit_test_state *uts)
{
struct udevice *bus, *dev;
- int child_count;
/*
* See testfdt_drv_probe() which effectively initializes that
* the uclass postp flag is set to a value
*/
ut_assertok(uclass_get_device(UCLASS_TEST_BUS, 0, &bus));
- for (device_find_first_child(bus, &dev), child_count = 0;
+ for (device_find_first_child(bus, &dev);
dev;
device_find_next_child(&dev)) {
struct dm_test_priv *priv = dev_get_priv(dev);
@@ -584,9 +574,8 @@
priv = dev_get_priv(dev);
ut_assert(priv != NULL);
ut_asserteq(0, priv->uclass_postp);
- child_count++;
}
- ut_asserteq(3, child_count);
+ ut_asserteq(3, device_get_child_count(bus));
return 0;
}
diff --git a/test/dm/remoteproc.c b/test/dm/remoteproc.c
index a2c4be7..1d9a9b3 100644
--- a/test/dm/remoteproc.c
+++ b/test/dm/remoteproc.c
@@ -171,12 +171,11 @@
ut_assertnonnull(loaded_firmware);
memset(loaded_firmware, 0, loaded_firmware_size);
- /* Verify valid ELF format */
- ut_assertok(rproc_elf32_sanity_check((ulong)valid_elf32, size));
-
/* Load firmware in loaded_firmware, and verify it */
- ut_assertok(rproc_elf32_load_image(dev, (unsigned long)valid_elf32));
+ ut_assertok(rproc_elf32_load_image(dev, (ulong)valid_elf32, size));
ut_assertok(memcmp(loaded_firmware, valid_elf32, loaded_firmware_size));
+ ut_asserteq(rproc_elf_get_boot_addr(dev, (unsigned long)valid_elf32),
+ 0x08000000);
unmap_physmem(loaded_firmware, MAP_NOCACHE);
/* Invalid ELF Magic */