commit 935e3625ceedbcf11e66947f1bc8791ececbf083
author T Karthik Reddy <t.karthik.reddy@xilinx.com> Tue May 10 13:26:09 2022 +0200
committer Michal Simek <michal.simek@amd.com> Fri Jun 24 14:11:05 2022 +0200
tree 65f213e1d98138edfa85dd5b847ee08cf2517dcd
parent c18e5fb055ab789f58434e3cb432582adee0134c

net: xilinx: axi_emac: Use shared MDIO bus support for axi emac driver

CONFIG_DM_ETH_PHY enables support to utilize generic ethernet phy
framework. Though if ethernet PHY node is in other ethernet node, it
will use shared MDIO to access the PHY of other ethernet. Move ethernet
print info statement from plat function to probe function, as phyaddr is
not enumerated when CONFIG_DM_ETH_PHY is enabled.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/ecfec78234233fefdc172c141c207b2d78ef70c5.1652181968.git.michal.simek@amd.com

drivers/net/xilinx_axi_emac.c

diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index a471573..04277b1 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -19,6 +19,7 @@
 #include <miiphy.h>
 #include <wait_bit.h>
 #include <linux/delay.h>
+#include <eth_phy.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -295,6 +296,9 @@
 	/* Set default MDIO divisor */
 	writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, &regs->mdio_mc);
 
+	if (IS_ENABLED(CONFIG_DM_ETH_PHY))
+		priv->phyaddr = eth_phy_get_addr(dev);
+
 	if (priv->phyaddr == -1) {
 		/* Detect the PHY address */
 		for (i = 31; i >= 0; i--) {
@@ -778,18 +782,29 @@
 		priv->phy_of_handle = plat->phy_of_handle;
 		priv->interface = pdata->phy_interface;
 
-		priv->bus = mdio_alloc();
-		priv->bus->read = axiemac_miiphy_read;
-		priv->bus->write = axiemac_miiphy_write;
-		priv->bus->priv = priv;
+		if (IS_ENABLED(CONFIG_DM_ETH_PHY))
+			priv->bus = eth_phy_get_mdio_bus(dev);
 
-		ret = mdio_register_seq(priv->bus, dev_seq(dev));
-		if (ret)
-			return ret;
+		if (!priv->bus) {
+			priv->bus = mdio_alloc();
+			priv->bus->read = axiemac_miiphy_read;
+			priv->bus->write = axiemac_miiphy_write;
+			priv->bus->priv = priv;
+
+			ret = mdio_register_seq(priv->bus, dev_seq(dev));
+			if (ret)
+				return ret;
+		}
+
+		if (IS_ENABLED(CONFIG_DM_ETH_PHY))
+			eth_phy_set_mdio_bus(dev, priv->bus);
 
 		axiemac_phy_init(dev);
 	}
 
+	printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)pdata->iobase,
+	       priv->phyaddr, phy_string_for_interface(pdata->phy_interface));
+
 	return 0;
 }
 
@@ -844,8 +859,10 @@
 		offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
 					       "phy-handle");
 		if (offset > 0) {
-			plat->phyaddr = fdtdec_get_int(gd->fdt_blob, offset,
-						       "reg", -1);
+			if (!(IS_ENABLED(CONFIG_DM_ETH_PHY)))
+				plat->phyaddr = fdtdec_get_int(gd->fdt_blob,
+							       offset,
+							       "reg", -1);
 			plat->phy_of_handle = offset;
 		}
 
@@ -857,9 +874,6 @@
 						     "xlnx,eth-hasnobuf");
 	}
 
-	printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)pdata->iobase,
-	       plat->phyaddr, phy_string_for_interface(pdata->phy_interface));
-
 	return 0;
 }