| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| # Copyright 2022 Unisoc Inc. |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/mfd/sprd,ums512-glbreg.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: Unisoc System Global Register |
| |
| maintainers: |
| - Orson Zhai <orsonzhai@gmail.com> |
| - Baolin Wang <baolin.wang7@gmail.com> |
| - Chunyan Zhang <zhang.lyra@gmail.com> |
| |
| description: |
| Unisoc system global registers provide register map |
| for clocks and some multimedia modules of the SoC. |
| |
| properties: |
| compatible: |
| items: |
| - enum: |
| - sprd,ums512-glbregs |
| - sprd,ums9620-glbregs |
| - const: syscon |
| - const: simple-mfd |
| |
| "#address-cells": |
| const: 1 |
| |
| "#size-cells": |
| const: 1 |
| |
| ranges: |
| maxItems: 1 |
| |
| reg: |
| maxItems: 1 |
| |
| patternProperties: |
| "^clock-controller@[0-9a-f]+$": |
| type: object |
| $ref: /schemas/clock/sprd,ums512-clk.yaml# |
| description: |
| Clock controller for the SoC clocks. |
| |
| required: |
| - compatible |
| - reg |
| |
| additionalProperties: false |
| |
| examples: |
| - | |
| ap_apb_regs: syscon@71000000 { |
| compatible = "sprd,ums512-glbregs", "syscon", "simple-mfd"; |
| reg = <0x71000000 0x3000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0x71000000 0x3000>; |
| |
| clock-controller@0 { |
| compatible = "sprd,ums512-apahb-gate"; |
| reg = <0x0 0x2000>; |
| #clock-cells = <1>; |
| }; |
| }; |
| |
| - | |
| ap_intc5_regs: syscon@32360000 { |
| compatible = "sprd,ums512-glbregs", "syscon", "simple-mfd"; |
| reg = <0x32360000 0x1000>; |
| }; |