| commit | 93c811b7331b16c1ecb1e7ad00f1864b5d4b359a | [log] [tgz] |
|---|---|---|
| author | Paul Barker <paul.barker.ct@bp.renesas.com> | Mon Oct 16 10:25:38 2023 +0100 |
| committer | Marek Vasut <marek.vasut+renesas@mailbox.org> | Tue Oct 17 03:27:42 2023 +0200 |
| tree | 6594d222bbf77843bb453f10289c5a3925efae74 | |
| parent | e84dddf10a7d1b3e9a65113fb0387d789ecf1dbf [diff] |
mmc: renesas-sdhi: Initialize module on RZ/G2L On the Renesas RZ/G2L SoC family, we must ensure that the required clock signals are enabled and the reset signal is de-asserted before we try to communicate with the SDHI module. Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>