ARM: IGEP0033: Update timing to run DDR at 400MHz.
We can run the DDR at 400MHz, so update the timings for that purpose.
Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org>
diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c
index 9e91f68..a9c34c6 100644
--- a/board/isee/igep0033/board.c
+++ b/board/isee/igep0033/board.c
@@ -64,7 +64,7 @@
#define OSC (V_OSCK/1000000)
const struct dpll_params dpll_ddr = {
- 303, OSC-1, 1, -1, -1, -1, -1};
+ 400, OSC-1, 1, -1, -1, -1, -1};
const struct dpll_params *get_dpll_ddr_params(void)
{
@@ -83,7 +83,7 @@
void sdram_init(void)
{
- config_ddr(303, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
+ config_ddr(400, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
}
#endif