Patches Part 1 by Jon Loeliger, 11 May 2004:
Dynamically handle REV1 and REV2 MPC85xx parts.
(Jon Loeliger, 10-May-2004).
New consistent memory map and Local Access Window across MPC85xx line.
New CCSRBAR at 0xE000_0000 now.
Add RAPID I/O memory map.
New memory map in README.MPC85xxads
(Kumar Gala, 10-May-2004)
Better board and CPU identification on MPC85xx boards at boot.
(Jon Loeliger, 10-May-2004)
SDRAM clock control fixes on MPC8540ADS & MPC8560 boards.
Some configuration options for MPC8540ADS & MPC8560ADS cleaned up.
(Jim Robertson, 10-May-2004)
Rewrite of the MPC85xx Three Speed Ethernet Controller (TSEC) driver.
Supports multiple PHYs.
(Andy Fleming, 10-May-2004)
Some README.MPC85xxads updates.
(Kumar Gala, 10-May-2004)
Copyright updates for "Freescale"
(Andy Fleming, 10-May-2004)
diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c
index ccd06e9..02b29ad 100644
--- a/cpu/mpc85xx/spd_sdram.c
+++ b/cpu/mpc85xx/spd_sdram.c
@@ -1,4 +1,5 @@
/*
+ * Copyright 2004 Freescale Semiconductor.
* (C) Copyright 2003 Motorola Inc.
* Xianghua Xiao (X.Xiao@motorola.com)
*
@@ -29,15 +30,7 @@
#ifdef CONFIG_SPD_EEPROM
-#undef DEBUG
-
-#if defined(DEBUG)
-#define DEB(x) x
-#else
-#define DEB(x)
-#endif
-
-#define ns2clk(ns) ((ns) / (2000000000 /get_bus_freq(0) + 1))
+#define ns2clk(ns) ((ns) / (2000000000 /get_bus_freq(0) + 1) + 1)
long int spd_sdram(void) {
volatile immap_t *immap = (immap_t *)CFG_IMMR;
@@ -61,64 +54,62 @@
ddr->cs0_bnds = ((spd.row_dens>>2) - 1);
ddr->cs0_config = ( 1<<31 | (spd.nrow_addr-12)<<8 | (spd.ncol_addr-8) );
- DEB(printf("\n"));
- DEB(printf("cs0_bnds = 0x%08x\n",ddr->cs0_bnds));
- DEB(printf("cs0_config = 0x%08x\n",ddr->cs0_config));
+ debug ("\n");
+ debug ("cs0_bnds = 0x%08x\n",ddr->cs0_bnds);
+ debug ("cs0_config = 0x%08x\n",ddr->cs0_config);
if ( spd.nrows == 2 ) {
ddr->cs1_bnds = ((spd.row_dens<<14) | ((spd.row_dens>>1) - 1));
ddr->cs1_config = ( 1<<31 | (spd.nrow_addr-12)<<8 | (spd.ncol_addr-8) );
- DEB(printf("cs1_bnds = 0x%08x\n",ddr->cs1_bnds));
- DEB(printf("cs1_config = 0x%08x\n",ddr->cs1_config));
+ debug ("cs1_bnds = 0x%08x\n",ddr->cs1_bnds);
+ debug ("cs1_config = 0x%08x\n",ddr->cs1_config);
}
memsize = spd.nrows * (4 * spd.row_dens);
- if( spd.mem_type == 0x07 ) {
- printf("DDR module detected, total size:%dMB.\n",memsize);
- } else {
+ if( spd.mem_type != 0x07 ) {
printf("No DDR module found!\n");
return 0;
}
- switch(memsize) {
- case 16:
- tmp = 7; /* TLB size */
- tmp1 = 1; /* TLB entry number */
- tmp2 = 23; /* Local Access Window size */
- break;
- case 32:
- tmp = 7;
- tmp1 = 2;
- tmp2 = 24;
- break;
- case 64:
- tmp = 8;
- tmp1 = 1;
- tmp2 = 25;
- break;
- case 128:
- tmp = 8;
- tmp1 = 2;
- tmp2 = 26;
- break;
- case 256:
- tmp = 9;
- tmp1 = 1;
- tmp2 = 27;
- break;
- case 512:
- tmp = 9;
- tmp1 = 2;
- tmp2 = 28;
- break;
- case 1024:
- tmp = 10;
- tmp1 = 1;
- tmp2 = 29;
- break;
- default:
- printf("DDR:we only added support 16M,32M,64M,128M,256M,512M and 1G DDR I.\n");
- return 0;
- break;
+ switch (memsize) {
+ case 16:
+ tmp = 7; /* TLB size */
+ tmp1 = 1; /* TLB entry number */
+ tmp2 = 23; /* Local Access Window size */
+ break;
+ case 32:
+ tmp = 7;
+ tmp1 = 2;
+ tmp2 = 24;
+ break;
+ case 64:
+ tmp = 8;
+ tmp1 = 1;
+ tmp2 = 25;
+ break;
+ case 128:
+ tmp = 8;
+ tmp1 = 2;
+ tmp2 = 26;
+ break;
+ case 256:
+ tmp = 9;
+ tmp1 = 1;
+ tmp2 = 27;
+ break;
+ case 512:
+ tmp = 9;
+ tmp1 = 2;
+ tmp2 = 28;
+ break;
+ case 1024:
+ tmp = 10;
+ tmp1 = 1;
+ tmp2 = 29;
+ break;
+ default:
+ printf ("DDR:we only added support 16M,32M,64M,128M,256M,512M and 1G DDR I.\n");
+ return 0;
+ break;
}
/* configure DDR TLB to TLB1 Entry 4,5 */
@@ -127,12 +118,12 @@
mtspr(MAS2, TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0));
mtspr(MAS3, TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1));
asm volatile("isync;msync;tlbwe;isync");
- DEB(printf("DDR:MAS0=0x%08x\n",TLB1_MAS0(1,4,0)));
- DEB(printf("DDR:MAS1=0x%08x\n",TLB1_MAS1(1,1,0,0,tmp)));
- DEB(printf("DDR:MAS2=0x%08x\n",TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) \
- & 0xfffff),0,0,0,0,0,0,0,0)));
- DEB(printf("DDR:MAS3=0x%08x\n",TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) \
- & 0xfffff),0,0,0,0,0,1,0,1,0,1)));
+ debug ("DDR:MAS0=0x%08x\n",TLB1_MAS0(1,4,0));
+ debug ("DDR:MAS1=0x%08x\n",TLB1_MAS1(1,1,0,0,tmp));
+ debug ("DDR:MAS2=0x%08x\n",TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) \
+ & 0xfffff),0,0,0,0,0,0,0,0));
+ debug ("DDR:MAS3=0x%08x\n",TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) \
+ & 0xfffff),0,0,0,0,0,1,0,1,0,1));
if(tmp1 == 2) {
mtspr(MAS0, TLB1_MAS0(1,5,0));
@@ -142,28 +133,28 @@
mtspr(MAS3, TLB1_MAS3((((CFG_DDR_SDRAM_BASE+(memsize*1024*1024)/2)>>12) \
& 0xfffff),0,0,0,0,0,1,0,1,0,1));
asm volatile("isync;msync;tlbwe;isync");
- DEB(printf("DDR:MAS0=0x%08x\n",TLB1_MAS0(1,5,0)));
- DEB(printf("DDR:MAS1=0x%08x\n",TLB1_MAS1(1,1,0,0,tmp)));
- DEB(printf("DDR:MAS2=0x%08x\n",TLB1_MAS2((((CFG_DDR_SDRAM_BASE \
- +(memsize*1024*1024)/2)>>12) & 0xfffff),0,0,0,0,0,0,0,0)));
- DEB(printf("DDR:MAS3=0x%08x\n",TLB1_MAS3((((CFG_DDR_SDRAM_BASE \
- +(memsize*1024*1024)/2)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)));
+ debug ("DDR:MAS0=0x%08x\n",TLB1_MAS0(1,5,0));
+ debug ("DDR:MAS1=0x%08x\n",TLB1_MAS1(1,1,0,0,tmp));
+ debug ("DDR:MAS2=0x%08x\n",TLB1_MAS2((((CFG_DDR_SDRAM_BASE \
+ +(memsize*1024*1024)/2)>>12) & 0xfffff),0,0,0,0,0,0,0,0));
+ debug ("DDR:MAS3=0x%08x\n",TLB1_MAS3((((CFG_DDR_SDRAM_BASE \
+ +(memsize*1024*1024)/2)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1));
}
#if defined(CONFIG_RAM_AS_FLASH)
ecm->lawbar2 = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
ecm->lawar2 = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & tmp2));
- DEB(printf("DDR:LAWBAR2=0x%08x\n",ecm->lawbar2));
- DEB(printf("DDR:LARAR2=0x%08x\n",ecm->lawar2));
+ debug ("DDR:LAWBAR2=0x%08x\n",ecm->lawbar2);
+ debug ("DDR:LARAR2=0x%08x\n",ecm->lawar2);
#else
ecm->lawbar1 = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
ecm->lawar1 = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & tmp2));
- DEB(printf("DDR:LAWBAR1=0x%08x\n",ecm->lawbar1));
- DEB(printf("DDR:LARAR1=0x%08x\n",ecm->lawar1));
+ debug ("DDR:LAWBAR1=0x%08x\n",ecm->lawbar1);
+ debug ("DDR:LARAR1=0x%08x\n",ecm->lawar1);
#endif
tmp = 20000/(((spd.clk_cycle & 0xF0) >> 4) * 10 + (spd.clk_cycle & 0x0f));
- DEB(printf("DDR:Module maximum data rate is: %dMhz\n",tmp));
+ debug ("DDR:Module maximum data rate is: %dMhz\n",tmp);
/* find the largest CAS */
if(spd.cas_lat & 0x40) {
@@ -186,13 +177,16 @@
}
tmp1 = get_bus_freq(0)/1000000;
- if(tmp1<230 && tmp1>=90 && tmp>=230) { /* 90~230 range, treated as DDR 200 */
+ if(tmp1<230 && tmp1>=90 && tmp>=230) {
+ /* 90~230 range, treated as DDR 200 */
if(spd.clk_cycle3 == 0xa0) caslat -= 2;
else if(spd.clk_cycle2 == 0xa0) caslat--;
- } else if(tmp1<280 && tmp1>=230 && tmp>=280) { /* 230-280 range, treated as DDR 266 */
+ } else if(tmp1<280 && tmp1>=230 && tmp>=280) {
+ /* 230-280 range, treated as DDR 266 */
if(spd.clk_cycle3 == 0x75) caslat -= 2;
else if(spd.clk_cycle2 == 0x75) caslat--;
- } else if(tmp1<350 && tmp1>=280 && tmp>=350) { /* 280~350 range, treated as DDR 333 */
+ } else if(tmp1<350 && tmp1>=280 && tmp>=350) {
+ /* 280~350 range, treated as DDR 333 */
if(spd.clk_cycle3 == 0x60) caslat -= 2;
else if(spd.clk_cycle2 == 0x60) caslat--;
} else if(tmp1<90 || tmp1 >=350) { /* DDR rate out-of-range */
@@ -200,9 +194,10 @@
return 0;
}
- /* note: caslat must also be programmed into ddr->sdram_mode register */
- /* note: WRREC(Twr) and WRTORD(Twtr) are not in SPD,use conservative value here */
-#if 1
+ /* note: caslat must also be programmed into ddr->sdram_mode
+ register */
+ /* note: WRREC(Twr) and WRTORD(Twtr) are not in SPD,use
+ conservative value here */
ddr->timing_cfg_1 = (((ns2clk(spd.trp/4) & 0x07) << 28 ) | \
((ns2clk(spd.tras) & 0x0f ) << 24 ) | \
((ns2clk(spd.trcd/4) & 0x07) << 20 ) | \
@@ -210,72 +205,66 @@
(((ns2clk(spd.sset[6]) - 8) & 0x0f) << 12 ) | \
( 0x300 ) | \
((ns2clk(spd.trrd/4) & 0x07) << 4) | 1);
-#else
- ddr->timing_cfg_1 = 0x37344321;
- caslat = 4;
-#endif
- DEB(printf("DDR:timing_cfg_1=0x%08x\n",ddr->timing_cfg_1));
- /* note: hand-coded value for timing_cfg_2, see Errata DDR1*/
-#if defined(CONFIG_MPC85xx_REV1)
+ debug ("DDR:timing_cfg_1=0x%08x\n",ddr->timing_cfg_1);
+
ddr->timing_cfg_2 = 0x00000800;
-#endif
- DEB(printf("DDR:timing_cfg_2=0x%08x\n",ddr->timing_cfg_2));
+ debug ("DDR:timing_cfg_2=0x%08x\n",ddr->timing_cfg_2);
/* only DDR I is supported, DDR I and II have different mode-register-set definition */
/* burst length is always 4 */
switch(caslat) {
- case 2:
- ddr->sdram_mode = 0x52; /* 1.5 */
- break;
- case 3:
- ddr->sdram_mode = 0x22; /* 2.0 */
- break;
- case 4:
- ddr->sdram_mode = 0x62; /* 2.5 */
- break;
- case 5:
- ddr->sdram_mode = 0x32; /* 3.0 */
- break;
- default:
- printf("DDR:only CAS Latency 1.5,2.0,2.5,3.0 is supported.\n");
- return 0;
+ case 2:
+ ddr->sdram_mode = 0x52; /* 1.5 */
+ break;
+ case 3:
+ ddr->sdram_mode = 0x22; /* 2.0 */
+ break;
+ case 4:
+ ddr->sdram_mode = 0x62; /* 2.5 */
+ break;
+ case 5:
+ ddr->sdram_mode = 0x32; /* 3.0 */
+ break;
+ default:
+ printf("DDR:only CAS Latency 1.5,2.0,2.5,3.0 is supported.\n");
+ return 0;
}
- DEB(printf("DDR:sdram_mode=0x%08x\n",ddr->sdram_mode));
+ debug ("DDR:sdram_mode=0x%08x\n",ddr->sdram_mode);
switch(spd.refresh) {
- case 0x00:
- case 0x80:
- tmp = ns2clk(15625);
- break;
- case 0x01:
- case 0x81:
- tmp = ns2clk(3900);
- break;
- case 0x02:
- case 0x82:
- tmp = ns2clk(7800);
- break;
- case 0x03:
- case 0x83:
- tmp = ns2clk(31300);
- break;
- case 0x04:
- case 0x84:
- tmp = ns2clk(62500);
- break;
- case 0x05:
- case 0x85:
- tmp = ns2clk(125000);
- break;
- default:
- tmp = 0x512;
- break;
+ case 0x00:
+ case 0x80:
+ tmp = ns2clk(15625);
+ break;
+ case 0x01:
+ case 0x81:
+ tmp = ns2clk(3900);
+ break;
+ case 0x02:
+ case 0x82:
+ tmp = ns2clk(7800);
+ break;
+ case 0x03:
+ case 0x83:
+ tmp = ns2clk(31300);
+ break;
+ case 0x04:
+ case 0x84:
+ tmp = ns2clk(62500);
+ break;
+ case 0x05:
+ case 0x85:
+ tmp = ns2clk(125000);
+ break;
+ default:
+ tmp = 0x512;
+ break;
}
/* set BSTOPRE to 0x100 for page mode, if auto-charge is used, set BSTOPRE = 0 */
ddr->sdram_interval = ((tmp & 0x3fff) << 16) | 0x100;
- DEB(printf("DDR:sdram_interval=0x%08x\n",ddr->sdram_interval));
+ debug ("DDR:sdram_interval=0x%08x\n",ddr->sdram_interval);
/* is this an ECC DDR chip? */
#if defined(CONFIG_DDR_ECC)
@@ -283,24 +272,71 @@
ddr->err_disable = 0x0000000d;
ddr->err_sbe = 0x00ff0000;
}
- DEB(printf("DDR:err_disable=0x%08x\n",ddr->err_disable));
- DEB(printf("DDR:err_sbe=0x%08x\n",ddr->err_sbe));
+ debug ("DDR:err_disable=0x%08x\n",ddr->err_disable);
+ debug ("DDR:err_sbe=0x%08x\n",ddr->err_sbe);
#endif
asm("sync;isync;msync");
udelay(500);
- /* registered or unbuffered? */
+#ifdef MPC85xx_DDR_SDRAM_CLK_CNTL
+ /* Setup the clock control (8555 and later)
+ * SDRAM_CLK_CNTL[0] = Source synchronous enable == 1
+ * SDRAM_CLK_CNTL[5-7] = Clock Adjust == 3 (3/4 cycle late)
+ */
+ ddr->sdram_clk_cntl = 0x83000000;
+#endif
+
+ /* Figure out the settings for the sdram_cfg register. Build up
+ * the entire register in 'tmp' before writing since the write into
+ * the register will actually enable the memory controller, and all
+ * settings must be done before enabling.
+ *
+ * sdram_cfg[0] = 1 (ddr sdram logic enable)
+ * sdram_cfg[1] = 1 (self-refresh-enable)
+ * sdram_cfg[6:7] = 2 (SDRAM type = DDR SDRAM)
+ */
+ tmp = 0xc2000000;
+
+ /* sdram_cfg[3] = RD_EN - registered DIMM enable
+ * A value of 0x26 indicates micron registered DIMMS (micron.com)
+ */
+ if (spd.mod_attr == 0x26) {
+ tmp |= 0x10000000;
+ }
+
#if defined(CONFIG_DDR_ECC)
- ddr->sdram_cfg = (spd.config == 0x02)?0x20000000:0x0;
+ /* If the user wanted ECC (enabled via sdram_cfg[2]) */
+ if (spd.config == 0x02) {
+ tmp |= 0x20000000;
+ }
#endif
- ddr->sdram_cfg = 0xc2000000|((spd.mod_attr == 0x20) ? 0x0 : \
- ((spd.mod_attr == 0x26) ? 0x10000000:0x0));
+
+
+ /*
+ * REV1 uses 1T timing.
+ * REV2 may use 1T or 2T as configured by the user.
+ */
+ {
+ uint pvr = get_pvr();
+
+ if (pvr != PVR_85xx_REV1) {
+#if defined(CONFIG_DDR_2T_TIMING)
+ /*
+ * Enable 2T timing by setting sdram_cfg[16].
+ */
+ tmp |= 0x8000;
+#endif
+ }
+ }
+
+ ddr->sdram_cfg = tmp;
+
asm("sync;isync;msync");
udelay(500);
- DEB(printf("DDR:sdram_cfg=0x%08x\n",ddr->sdram_cfg));
+ debug ("DDR:sdram_cfg=0x%08x\n",ddr->sdram_cfg);
return (memsize*1024*1024);
}