Port AT91CAP9 to the new headers
Adapt the existing AT91CAP9 code to the new headers and APIs.
Signed-off-by: Stelian Pop <stelian@popies.net>
diff --git a/cpu/arm926ejs/at91sam9/ether.c b/cpu/arm926ejs/at91sam9/ether.c
index 8de1bb7..e4f5601 100644
--- a/cpu/arm926ejs/at91sam9/ether.c
+++ b/cpu/arm926ejs/at91sam9/ether.c
@@ -30,6 +30,6 @@
#if defined(CONFIG_MACB) && defined(CONFIG_CMD_NET)
void at91sam9_eth_initialize(bd_t *bi)
{
- macb_eth_initialize(0, (void *)AT91C_BASE_MACB, 0x00);
+ macb_eth_initialize(0, (void *)AT91_BASE_EMAC, 0x00);
}
#endif
diff --git a/cpu/arm926ejs/at91sam9/spi.c b/cpu/arm926ejs/at91sam9/spi.c
index 0953820..c819608 100644
--- a/cpu/arm926ejs/at91sam9/spi.c
+++ b/cpu/arm926ejs/at91sam9/spi.c
@@ -19,94 +19,135 @@
*
*/
-#include <config.h>
#include <common.h>
-#include <asm/hardware.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/at91_spi.h>
#ifdef CONFIG_HAS_DATAFLASH
#include <dataflash.h>
-/* Max Value = 10MHz to be compliant to the Continuous Array Read function */
-#define AT91C_SPI_CLK 10000000
-
-/* AC Characteristics: DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
-#define DATAFLASH_TCSS (0xFA << 16)
-#define DATAFLASH_TCHS (0x8 << 24)
-
-#define AT91C_TIMEOUT_WRDY 200000
-#define AT91C_SPI_PCS0_DATAFLASH_CARD 0xE /* Chip Select 0: NPCS0%1110 */
-#define AT91C_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3: NPCS3%0111 */
+#define AT91_SPI_PCS0_DATAFLASH_CARD 0xE /* Chip Select 0: NPCS0%1110 */
+#define AT91_SPI_PCS1_DATAFLASH_CARD 0xD /* Chip Select 0: NPCS0%1101 */
+#define AT91_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3: NPCS3%0111 */
void AT91F_SpiInit(void)
{
/* Reset the SPI */
- AT91C_BASE_SPI0->SPI_CR = AT91C_SPI_SWRST;
+ writel(AT91_SPI_SWRST, AT91_BASE_SPI + AT91_SPI_CR);
/* Configure SPI in Master Mode with No CS selected !!! */
- AT91C_BASE_SPI0->SPI_MR =
- AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS;
+ writel(AT91_SPI_MSTR | AT91_SPI_MODFDIS | AT91_SPI_PCS,
+ AT91_BASE_SPI + AT91_SPI_MR);
/* Configure CS0 */
- AT91C_BASE_SPI0->SPI_CSR[0] =
- AT91C_SPI_CPOL |
- (AT91C_SPI_DLYBS & DATAFLASH_TCSS) |
- (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) |
- ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
+ writel(AT91_SPI_NCPHA |
+ (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
+ (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
+ ((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8),
+ AT91_BASE_SPI + AT91_SPI_CSR(0));
+
+#ifdef CFG_DATAFLASH_LOGIC_ADDR_CS1
+ /* Configure CS1 */
+ writel(AT91_SPI_NCPHA |
+ (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
+ (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
+ ((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8),
+ AT91_BASE_SPI + AT91_SPI_CSR(1));
+#endif
+
+#ifdef CFG_DATAFLASH_LOGIC_ADDR_CS3
+ /* Configure CS3 */
+ writel(AT91_SPI_NCPHA |
+ (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
+ (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
+ ((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8),
+ AT91_BASE_SPI + AT91_SPI_CSR(3));
+#endif
+
+ /* SPI_Enable */
+ writel(AT91_SPI_SPIEN, AT91_BASE_SPI + AT91_SPI_CR);
+
+ while (!(readl(AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_SPIENS));
+
+ /*
+ * Add tempo to get SPI in a safe state.
+ * Should not be needed for new silicon (Rev B)
+ */
+ udelay(500000);
+ readl(AT91_BASE_SPI + AT91_SPI_SR);
+ readl(AT91_BASE_SPI + AT91_SPI_RDR);
+
}
void AT91F_SpiEnable(int cs)
{
+ unsigned long mode;
switch (cs) {
case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */
- AT91C_BASE_SPI0->SPI_MR &= 0xFFF0FFFF;
- AT91C_BASE_SPI0->SPI_MR |=
- ((AT91C_SPI_PCS0_DATAFLASH_CARD<<16) & AT91C_SPI_PCS);
+ mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
+ mode &= 0xFFF0FFFF;
+ writel(mode | ((AT91_SPI_PCS0_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
+ AT91_BASE_SPI + AT91_SPI_MR);
+ break;
+ case 1: /* Configure SPI CS1 for Serial DataFlash AT45DBxx */
+ mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
+ mode &= 0xFFF0FFFF;
+ writel(mode | ((AT91_SPI_PCS1_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
+ AT91_BASE_SPI + AT91_SPI_MR);
break;
case 3:
- AT91C_BASE_SPI0->SPI_MR &= 0xFFF0FFFF;
- AT91C_BASE_SPI0->SPI_MR |=
- ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS);
+ mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
+ mode &= 0xFFF0FFFF;
+ writel(mode | ((AT91_SPI_PCS3_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
+ AT91_BASE_SPI + AT91_SPI_MR);
break;
}
/* SPI_Enable */
- AT91C_BASE_SPI0->SPI_CR = AT91C_SPI_SPIEN;
+ writel(AT91_SPI_SPIEN, AT91_BASE_SPI + AT91_SPI_CR);
}
+unsigned int AT91F_SpiWrite1(AT91PS_DataflashDesc pDesc);
+
unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc)
{
unsigned int timeout;
+
pDesc->state = BUSY;
- AT91C_BASE_SPI0->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
+ writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, AT91_BASE_SPI + AT91_SPI_PTCR);
+
/* Initialize the Transmit and Receive Pointer */
- AT91C_BASE_SPI0->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt;
- AT91C_BASE_SPI0->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt;
+ writel((unsigned int)pDesc->rx_cmd_pt, AT91_BASE_SPI + AT91_SPI_RPR);
+ writel((unsigned int)pDesc->tx_cmd_pt, AT91_BASE_SPI + AT91_SPI_TPR);
/* Intialize the Transmit and Receive Counters */
- AT91C_BASE_SPI0->SPI_RCR = pDesc->rx_cmd_size;
- AT91C_BASE_SPI0->SPI_TCR = pDesc->tx_cmd_size;
+ writel(pDesc->rx_cmd_size, AT91_BASE_SPI + AT91_SPI_RCR);
+ writel(pDesc->tx_cmd_size, AT91_BASE_SPI + AT91_SPI_TCR);
if (pDesc->tx_data_size != 0) {
/* Initialize the Next Transmit and Next Receive Pointer */
- AT91C_BASE_SPI0->SPI_RNPR = (unsigned int)pDesc->rx_data_pt;
- AT91C_BASE_SPI0->SPI_TNPR = (unsigned int)pDesc->tx_data_pt;
+ writel((unsigned int)pDesc->rx_data_pt, AT91_BASE_SPI + AT91_SPI_RNPR);
+ writel((unsigned int)pDesc->tx_data_pt, AT91_BASE_SPI + AT91_SPI_TNPR);
/* Intialize the Next Transmit and Next Receive Counters */
- AT91C_BASE_SPI0->SPI_RNCR = pDesc->rx_data_size;
- AT91C_BASE_SPI0->SPI_TNCR = pDesc->tx_data_size;
+ writel(pDesc->rx_data_size, AT91_BASE_SPI + AT91_SPI_RNCR);
+ writel(pDesc->tx_data_size, AT91_BASE_SPI + AT91_SPI_TNCR);
}
/* arm simple, non interrupt dependent timer */
reset_timer_masked();
timeout = 0;
- AT91C_BASE_SPI0->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN;
- while (!(AT91C_BASE_SPI0->SPI_SR & AT91C_SPI_RXBUFF) &&
+ writel(AT91_SPI_TXTEN + AT91_SPI_RXTEN, AT91_BASE_SPI + AT91_SPI_PTCR);
+ while (!(readl(AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_RXBUFF) &&
((timeout = get_timer_masked()) < CFG_SPI_WRITE_TOUT));
- AT91C_BASE_SPI0->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
+ writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, AT91_BASE_SPI + AT91_SPI_PTCR);
pDesc->state = IDLE;
if (timeout >= CFG_SPI_WRITE_TOUT) {
diff --git a/cpu/arm926ejs/at91sam9/timer.c b/cpu/arm926ejs/at91sam9/timer.c
index 79c135f..4e79466 100644
--- a/cpu/arm926ejs/at91sam9/timer.c
+++ b/cpu/arm926ejs/at91sam9/timer.c
@@ -24,22 +24,24 @@
#include <common.h>
#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pit.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/io.h>
/*
* We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by
* setting the 20 bit counter period to its maximum (0xfffff).
*/
#define TIMER_LOAD_VAL 0xfffff
-#define READ_RESET_TIMER (AT91C_BASE_PITC->PITC_PIVR)
-#define READ_TIMER (AT91C_BASE_PITC->PITC_PIIR)
+#define READ_RESET_TIMER at91_sys_read(AT91_PIT_PIVR)
+#define READ_TIMER at91_sys_read(AT91_PIT_PIIR)
#define TIMER_FREQ (AT91C_MASTER_CLOCK << 4)
#define TICKS_TO_USEC(ticks) ((ticks) / 6)
ulong get_timer_masked(void);
ulong resettime;
-AT91PS_PITC p_pitc;
-
/* nothing really to do with interrupts, just starts up a counter. */
int timer_init(void)
{
@@ -47,13 +49,10 @@
* Enable PITC Clock
* The clock is already enabled for system controller in boot
*/
- AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SYS;
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
/* Enable PITC */
- AT91C_BASE_PITC->PITC_PIMR = AT91C_PITC_PITEN;
-
- /* Load PITC_PIMR with the right timer value */
- AT91C_BASE_PITC->PITC_PIMR |= TIMER_LOAD_VAL;
+ at91_sys_write(AT91_PIT_MR, TIMER_LOAD_VAL | AT91_PIT_PITEN);
reset_timer_masked();
@@ -67,6 +66,7 @@
static inline ulong get_timer_raw(void)
{
ulong now = READ_TIMER;
+
if (now >= resettime)
return now - resettime;
else
@@ -129,6 +129,7 @@
ulong get_tbclk(void)
{
ulong tbclk;
+
tbclk = CFG_HZ;
return tbclk;
}
@@ -139,9 +140,9 @@
void reset_cpu(ulong ignored)
{
/* this is the way Linux does it */
- AT91C_BASE_RSTC->RSTC_RCR = (0xA5 << 24) |
- AT91C_RSTC_PROCRST |
- AT91C_RSTC_PERRST;
+ at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY |
+ AT91_RSTC_PROCRST |
+ AT91_RSTC_PERRST);
while (1);
/* Never reached */
diff --git a/cpu/arm926ejs/at91sam9/usb.c b/cpu/arm926ejs/at91sam9/usb.c
index 09292a6..d678897 100644
--- a/cpu/arm926ejs/at91sam9/usb.c
+++ b/cpu/arm926ejs/at91sam9/usb.c
@@ -26,12 +26,14 @@
#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT)
#include <asm/arch/hardware.h>
+#include <asm/arch/io.h>
+#include <asm/arch/at91_pmc.h>
int usb_cpu_init(void)
{
/* Enable USB host clock. */
- AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_UHP;
- AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_UHP;
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_UHP);
+ at91_sys_write(AT91_PMC_SCER, AT91_PMC_UHP);
return 0;
}
@@ -39,8 +41,8 @@
int usb_cpu_stop(void)
{
/* Disable USB host clock. */
- AT91C_BASE_PMC->PMC_PCDR = 1 << AT91C_ID_UHP;
- AT91C_BASE_PMC->PMC_SCDR = AT91C_PMC_UHP;
+ at91_sys_write(AT91_PMC_PCDR, 1 << AT91_ID_UHP);
+ at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP);
return 0;
}