powerpc/mpc85xx: Add workaround for DDR erratum A004508
When the DDR controller is initialized below a junction temperature of
0°C and then operated above a junction temperature of 65°C, the DDR
controller may cause receive data errors, resulting ECC errors and/or
corrupted data. This erratum applies to the following SoCs and their
variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023,
P2020.
Signed-off-by: York Sun <yorksun@freescale.com>
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 78e82bb..dcf6287 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -2304,5 +2304,10 @@
ddr->debug[2] = 0x00000400;
ddr->debug[4] = 0xff800000;
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004508
+ if ((ip_rev >= 0x40000) && (ip_rev < 0x40400))
+ ddr->debug[2] |= 0x00000200; /* set bit 22 */
+#endif
+
return check_fsl_memctl_config_regs(ddr);
}