ppc: Remove MPC8555CDS boards
These boards have not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove them. As this is the only
ARCH_MPC8555 platform left, remove that support as well.
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index b800344..b5122d1 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -1863,25 +1863,13 @@
static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts)
{
- unsigned int clk_adjust; /* Clock adjust */
- unsigned int ss_en = 0; /* Source synchronous enable */
-
-#if defined(CONFIG_ARCH_MPC8555)
- /* Per FSL Application Note: AN2805 */
- ss_en = 1;
-#endif
- if (fsl_ddr_get_version(0) >= 0x40701) {
+ if (fsl_ddr_get_version(0) >= 0x40701)
/* clk_adjust in 5-bits on T-series and LS-series */
- clk_adjust = (popts->clk_adjust & 0x1F) << 22;
- } else {
+ ddr->ddr_sdram_clk_cntl = (popts->clk_adjust & 0x1F) << 22;
+ else
/* clk_adjust in 4-bits on earlier MPC85xx and P-series */
- clk_adjust = (popts->clk_adjust & 0xF) << 23;
- }
+ ddr->ddr_sdram_clk_cntl = (popts->clk_adjust & 0xF) << 23;
- ddr->ddr_sdram_clk_cntl = (0
- | ((ss_en & 0x1) << 31)
- | clk_adjust
- );
debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
}