commit 9b1b6d42256a4c2e59c803afdbf90d39371e61ba
author Masahiro Yamada <yamada.masahiro@socionext.com> Mon Sep 19 21:40:26 2016 +0900
committer Tom Rini <trini@konsulko.com> Mon Sep 19 15:20:09 2016 -0400
tree f23016c6f6dab180ed5901a02f3ab80c3aaf23ce
parent 00709f56975e0fb08374c03aad21ac7d7e61acd0

Revert "Increase default of CONFIG_SYS_MALLOC_F_LEN for SPL_OF_CONTROL"

This reverts commit 90c08d9e08c7a108ab904f3bbdeb558081757892.

I took a closer look at this after the commit was applied, and found
CONFIG_SYS_MALLOC_F_LEN=0x2000 was too much.  8KB memory for SPL is
actually too big for some boards.  Perhaps 0x800 is enough, but the
situation varies board by board.

Let's postpone our decision until we come up with a better idea.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

configs/socfpga_vining_fpga_defconfig

diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig
index 19f79d1..a5a9501 100644
--- a/configs/socfpga_vining_fpga_defconfig
+++ b/configs/socfpga_vining_fpga_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_SOCFPGA_SAMTEC_VINING_FPGA=y
 CONFIG_SPL_STACK_R_ADDR=0x00800000
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_vining_fpga"