ARM: vexpress: refactoring of Versatile Express CA9x4 support
The current ca9x4_ct_vxp platform contains support for a Versatile
Express motherboard with a quad core A9 core tile.
This patch separates the Versatile Express motherboard code and the
A9 specific code, to ease supporting more core tiles in the next
patches.
Andre: merged the first two of Ryan's original patches and did some
checkpatch fixes.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
diff --git a/board/armltd/vexpress/Makefile b/board/armltd/vexpress/Makefile
index 8749590..6719f3d 100644
--- a/board/armltd/vexpress/Makefile
+++ b/board/armltd/vexpress/Makefile
@@ -25,7 +25,7 @@
LIB = $(obj)lib$(BOARD).o
-COBJS := ca9x4_ct_vxp.o
+COBJS := vexpress_common.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/armltd/vexpress/ca9x4_ct_vxp.c b/board/armltd/vexpress/vexpress_common.c
similarity index 97%
rename from board/armltd/vexpress/ca9x4_ct_vxp.c
rename to board/armltd/vexpress/vexpress_common.c
index d5e109e..c4f2520 100644
--- a/board/armltd/vexpress/ca9x4_ct_vxp.c
+++ b/board/armltd/vexpress/vexpress_common.c
@@ -166,8 +166,8 @@
*/
writel(SYSTIMER_RELOAD, &systimer_base->timer0load);
writel(SYSTIMER_RELOAD, &systimer_base->timer0value);
- writel(SYSTIMER_EN | SYSTIMER_32BIT | \
- readl(&systimer_base->timer0control), \
+ writel(SYSTIMER_EN | SYSTIMER_32BIT |
+ readl(&systimer_base->timer0control),
&systimer_base->timer0control);
reset_timer_masked();
@@ -251,7 +251,7 @@
return get_timer(0);
}
-ulong get_tbclk (void)
+ulong get_tbclk(void)
{
return (ulong)CONFIG_SYS_HZ;
}