commit 9c1563e3fd24ca7161c089dfd999d031f95094de
author Ye Li <ye.li@nxp.com> Wed May 15 09:56:59 2019 +0000
committer Stefano Babic <sbabic@denx.de> Fri Jul 19 20:14:50 2019 +0200
tree 2427c80f845acaaaca1c198f46f06fa63c89a0c2
parent 285aea01d2f9398b9c127c7a7fbaa401adf6969f

mx7ulp: Select the SCG1 APLL PFD as a system clock source

Due to the APLL out glitch issue, the APLLCFG PLLS bit must
be set to select SCG1 APLL PFD for generating system clock to align
with the design.

Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>

board/freescale/mx7ulp_evk/imximage.cfg

diff --git a/board/freescale/mx7ulp_evk/imximage.cfg b/board/freescale/mx7ulp_evk/imximage.cfg
index d4f6c3c..6bc7c19 100644
--- a/board/freescale/mx7ulp_evk/imximage.cfg
+++ b/board/freescale/mx7ulp_evk/imximage.cfg
@@ -45,7 +45,7 @@
 DATA 4   0x403e0040 0x01000020
 DATA 4   0x403e0500 0x01000000
 DATA 4   0x403e050c 0x80808080
-DATA 4   0x403e0508 0x00160000
+DATA 4   0x403e0508 0x00160002
 DATA 4   0x403E0510 0x00000002
 DATA 4   0x403E0514 0x00000005
 DATA 4   0x403e0500 0x00000001