imx8ulp: Workaround LPOSC_TRIM fuse load issue
8ULP ROM should read the LPOSC trim BIAS fuse to fill the CGC0
LPOSCCTRL[7:0], but it writes a fixed value on A0.1 revision.
A0.2 will fix the issue in ROM. But A0.1 we have to workaround
it in SPL by setting LPOSCCTRL BIASCURRENT again.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
index 8e2c6ed..284ccaf 100644
--- a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
@@ -17,4 +17,5 @@
int xrdc_config_pdac_openacc(u32 bridge, u32 index);
enum boot_device get_boot_device(void);
void set_lpav_qos(void);
+void load_lposc_fuse(void);
#endif
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index d9dca21..e12e28d 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -487,6 +487,26 @@
writel(0x003fffff, SIM_SEC_BASE_ADDR + 0x58);
}
+void load_lposc_fuse(void)
+{
+ int ret;
+ u32 val = 0, val2 = 0, reg;
+
+ ret = fuse_read(25, 0, &val);
+ if (ret)
+ return; /* failed */
+
+ ret = fuse_read(25, 1, &val2);
+ if (ret)
+ return; /* failed */
+
+ /* LPOSCCTRL */
+ reg = readl(0x2802f304);
+ reg &= ~0xff;
+ reg |= (val & 0xff);
+ writel(reg, 0x2802f304);
+}
+
void set_lpav_qos(void)
{
/* Set read QoS of dcnano on LPAV NIC */
diff --git a/board/freescale/imx8ulp_evk/spl.c b/board/freescale/imx8ulp_evk/spl.c
index 42f8e26..c17d5ef 100644
--- a/board/freescale/imx8ulp_evk/spl.c
+++ b/board/freescale/imx8ulp_evk/spl.c
@@ -77,6 +77,12 @@
/* After AP set iomuxc0, the i2c can't work, Need M33 to set it now */
+ /* Load the lposc fuse for single boot to work around ROM issue,
+ * The fuse depends on S400 to read.
+ */
+ if (is_soc_rev(CHIP_REV_1_0) && get_boot_mode() == SINGLE_BOOT)
+ load_lposc_fuse();
+
upower_init();
power_init_board();