commit 9d12a82ed36db2093998791e56c3cee6d6993223
author Jagan Teki <jagan@amarulasolutions.com> Mon May 07 13:03:22 2018 +0530
committer Jagan Teki <jagan@amarulasolutions.com> Mon May 28 16:40:43 2018 +0530
tree ba5d29bfdecccb270b6c196c62026e85b4a3395f
parent 26fc4d6c5198910d09fe26ef7c556e3b1ef918a5

musb: sunxi: Add OTG device clkgate and reset for H3/H5

Add OTG device clkgate and reset for H3/H5 through driver_data.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Jun Nie <jun.nie@linaro.org>

drivers/usb/musb-new/sunxi.c

diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c
index 77ee619..b473e2f 100644
--- a/drivers/usb/musb-new/sunxi.c
+++ b/drivers/usb/musb-new/sunxi.c
@@ -77,6 +77,8 @@
 
 struct sunxi_musb_config {
 	struct musb_hdrc_config *config;
+	u8 rst_bit;
+	u8 clkgate_bit;
 };
 
 struct sunxi_glue {
@@ -274,9 +276,16 @@
 	musb->isr = sunxi_musb_interrupt;
 
 	setbits_le32(&glue->ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
+	if (glue->cfg->clkgate_bit)
+		setbits_le32(&glue->ccm->ahb_gate0,
+			     1 << glue->cfg->clkgate_bit);
 #ifdef CONFIG_SUNXI_GEN_SUN6I
 	setbits_le32(&glue->ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
+	if (glue->cfg->rst_bit)
+		setbits_le32(&glue->ccm->ahb_reset0_cfg,
+			     1 << glue->cfg->rst_bit);
 #endif
+
 	sunxi_usb_phy_init(0);
 
 	USBC_ConfigFIFO_Base();
@@ -407,8 +416,14 @@
 	sunxi_usb_phy_exit(0);
 #ifdef CONFIG_SUNXI_GEN_SUN6I
 	clrbits_le32(&glue->ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
+	if (glue->cfg->rst_bit)
+		clrbits_le32(&glue->ccm->ahb_reset0_cfg,
+			     1 << glue->cfg->rst_bit);
 #endif
 	clrbits_le32(&glue->ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
+	if (glue->cfg->clkgate_bit)
+		clrbits_le32(&glue->ccm->ahb_gate0,
+			     1 << glue->cfg->clkgate_bit);
 
 	free(host->host);
 	host->host = NULL;
@@ -422,6 +437,8 @@
 
 static const struct sunxi_musb_config sun8i_h3_cfg = {
 	.config = &musb_config_h3,
+	.rst_bit = 23,
+	.clkgate_bit = 23,
 };
 
 static const struct udevice_id sunxi_musb_ids[] = {