commit 9d4fc99dbdbfda1260aad478e83fca7cdf0e1a32
author Dirk Behme <dirk.behme@googlemail.com> Sun May 31 12:44:42 2009 +0200
committer Wolfgang Denk <wd@denx.de> Fri Jun 12 20:39:53 2009 +0200
tree 0f11f99f9ff8cc0306926f0a96f3d1f561ce64b6
parent 3962c4f9fc4482a6547f3c3d3d5e986e625abb8a

OMAP3: Fix CKE1 MUX setting to allow self-refresh

The Beagle rev Cx and Overo boards are using both SDRC CSes. The MUX
setting is needed for the second CS clock signal to allow the 2 RAM
parts to be put in self-refresh correctly. This also works on rev B
Beagle boards with 128M of RAM.

From: Steve Sakoman <steve@sakoman.com>
From: Jean Pihet <jpihet@mvista.com>
Signed-off-by: Jean Pihet <jpihet@mvista.com>
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>

board/omap3/beagle/beagle.h

diff --git a/board/omap3/beagle/beagle.h b/board/omap3/beagle/beagle.h
index 324ec66..3a0f907 100644
--- a/board/omap3/beagle/beagle.h
+++ b/board/omap3/beagle/beagle.h
@@ -371,7 +371,7 @@
  MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_mbusflag*/\
  MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_sbusflag*/\
  MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
- MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTD | DIS | M7)) /*sdrc_cke1*/
+ MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTU | EN  | M0)) /*sdrc_cke1*/
 
 #define MUX_BEAGLE_C() \
  MUX_VAL(CP(MCBSP3_DX),		(IEN | PTD | DIS | M4)) /*GPIO_140*/\

board/omap3/overo/overo.h

diff --git a/board/omap3/overo/overo.h b/board/omap3/overo/overo.h
index b595f6a..0b59120 100644
--- a/board/omap3/overo/overo.h
+++ b/board/omap3/overo/overo.h
@@ -376,6 +376,6 @@
  MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_mbusflag*/\
  MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_sbusflag*/\
  MUX_VAL(CP(SDRC_CKE0),		(IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
- MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTD | DIS | M7)) /*sdrc_cke1*/
+ MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTU | EN  | M0)) /*sdrc_cke1*/
 
 #endif