Merge branch 'master' of http://git.denx.de/u-boot-sunxi
diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h
index 47f45c1..017d55f 100644
--- a/arch/arm/mach-mvebu/include/mach/cpu.h
+++ b/arch/arm/mach-mvebu/include/mach/cpu.h
@@ -145,5 +145,18 @@
* drivers/ddr/marvell
*/
int ddr3_init(void);
+
+struct mvebu_lcd_info {
+ u32 fb_base;
+ int x_res;
+ int y_res;
+ int x_fp; /* frontporch */
+ int y_fp;
+ int x_bp; /* backporch */
+ int y_bp;
+};
+
+int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info);
+
#endif /* __ASSEMBLY__ */
#endif /* _MVEBU_CPU_H */
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h
index cb216bc..b317940 100644
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -67,6 +67,7 @@
#define MVEBU_SATA0_BASE (MVEBU_REGISTER(0xa8000))
#define MVEBU_NAND_BASE (MVEBU_REGISTER(0xd0000))
#define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000))
+#define MVEBU_LCD_BASE (MVEBU_REGISTER(0xe0000))
#define SOC_COHERENCY_FABRIC_CTRL_REG (MVEBU_REGISTER(0x20200))
#define MBUS_ERR_PROP_EN (1 << 8)
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index b8ac5a5..f71e342 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -10,6 +10,7 @@
#ifndef _ASM_IO_H
#define _ASM_IO_H
+#include <linux/bug.h>
#include <linux/compiler.h>
#include <linux/types.h>
diff --git a/arch/powerpc/cpu/mpc83xx/law.c b/arch/powerpc/cpu/mpc83xx/law.c
index 997aea4..5659ab8 100644
--- a/arch/powerpc/cpu/mpc83xx/law.c
+++ b/arch/powerpc/cpu/mpc83xx/law.c
@@ -19,7 +19,7 @@
if (start == 0)
start_align = 1ull << (LAW_SIZE_2G + 1);
else
- start_align = 1ull << (__ffs64(start) - 1);
+ start_align = 1ull << (__ffs64(start));
law_sz = min(start_align, sz);
law_sz_enc = __ilog2_u64(law_sz) - 1;
@@ -39,7 +39,7 @@
if (sz) {
start += law_sz;
- start_align = 1ull << (__ffs64(start) - 1);
+ start_align = 1ull << (__ffs64(start));
law_sz = min(start_align, sz);
law_sz_enc = __ilog2_u64(law_sz) - 1;
ecm = &immap->sysconf.ddrlaw[1];
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 13a7d0f..8c6b678 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -23,6 +23,10 @@
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_srio.h>
+#ifdef CONFIG_FSL_CORENET
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#endif
#include <fsl_usb.h>
#include <hwconfig.h>
#include <linux/compiler.h>
@@ -788,6 +792,13 @@
spin_table_compat = 1;
#endif
+#ifdef CONFIG_FSL_CORENET
+ set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ setup_portals();
+#endif
+#endif
+
l2cache_init();
#if defined(CONFIG_RAMBOOT_PBL)
disable_cpc_sram();
diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c
index 24baad4..bd79297 100644
--- a/arch/powerpc/cpu/mpc8xxx/law.c
+++ b/arch/powerpc/cpu/mpc8xxx/law.c
@@ -188,7 +188,7 @@
if (start == 0)
start_align = 1ull << (LAW_SIZE_32G + 1);
else
- start_align = 1ull << (__ffs64(start) - 1);
+ start_align = 1ull << (__ffs64(start));
law_sz = min(start_align, sz);
law_sz_enc = __ilog2_u64(law_sz) - 1;
@@ -203,7 +203,7 @@
if (sz) {
start += law_sz;
- start_align = 1ull << (__ffs64(start) - 1);
+ start_align = 1ull << (__ffs64(start));
law_sz = min(start_align, sz);
law_sz_enc = __ilog2_u64(law_sz) - 1;
diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c
index 6a8fca6..e582abb 100644
--- a/board/freescale/b4860qds/b4860qds.c
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -16,7 +16,6 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include <hwconfig.h>
@@ -1023,10 +1022,6 @@
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
- set_liodns();
-#ifdef CONFIG_SYS_DPAA_QBMAN
- setup_portals();
-#endif
/*
* Adjust core voltage according to voltage ID
* This function changes I2C mux to channel 2.
diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c
index f1bed51..1bd65a8 100644
--- a/board/freescale/common/vid.c
+++ b/board/freescale/common/vid.c
@@ -42,7 +42,7 @@
* The IR chip can show up under the following addresses:
* 0x08 (Verified on T1040RDB-PA,T4240RDB-PB,X-T4240RDB-16GPA)
* 0x09 (Verified on T1040RDB-PA)
- * 0x38 (Verified on T2080QDS, T2081QDS)
+ * 0x38 (Verified on T2080QDS, T2081QDS, T4240RDB)
*/
static int find_ir_chip_on_i2c(void)
{
@@ -292,7 +292,7 @@
(void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif
u32 fusesr;
- u8 vid;
+ u8 vid, buf;
int vdd_target, vdd_current, vdd_last;
int ret, i2caddress;
unsigned long vdd_string_override;
@@ -346,6 +346,21 @@
debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress);
}
+ /* check IR chip work on Intel mode*/
+ ret = i2c_read(i2caddress,
+ IR36021_INTEL_MODE_OOFSET,
+ 1, (void *)&buf, 1);
+ if (ret) {
+ printf("VID: failed to read IR chip mode.\n");
+ ret = -1;
+ goto exit;
+ }
+ if ((buf & IR36021_MODE_MASK) != IR36021_INTEL_MODE) {
+ printf("VID: IR Chip is not used in Intel mode.\n");
+ ret = -1;
+ goto exit;
+ }
+
/* get the voltage ID from fuse status register */
fusesr = in_be32(&gur->dcfg_fusesr);
/*
diff --git a/board/freescale/common/vid.h b/board/freescale/common/vid.h
index a9c7bb4..9182c20 100644
--- a/board/freescale/common/vid.h
+++ b/board/freescale/common/vid.h
@@ -11,6 +11,10 @@
#define IR36021_LOOP1_VOUT_OFFSET 0x9A
#define IR36021_MFR_ID_OFFSET 0x92
#define IR36021_MFR_ID 0x43
+#define IR36021_INTEL_MODE_OOFSET 0x14
+#define IR36021_MODE_MASK 0x20
+#define IR36021_INTEL_MODE 0x00
+#define IR36021_AMD_MODE 0x20
/* step the IR regulator in 5mV increments */
#define IR_VDD_STEP_DOWN 5
diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c
index 6f0fea1..f41985d 100644
--- a/board/freescale/corenet_ds/corenet_ds.c
+++ b/board/freescale/corenet_ds/corenet_ds.c
@@ -14,7 +14,6 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
@@ -125,11 +124,6 @@
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
- set_liodns();
-#ifdef CONFIG_SYS_DPAA_QBMAN
- setup_portals();
-#endif
-
return 0;
}
diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c
index e600bdb..c6a7242 100644
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ b/board/freescale/p2041rdb/p2041rdb.c
@@ -14,7 +14,6 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
@@ -140,8 +139,6 @@
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
- set_liodns();
- setup_portals();
board_config_lanes_mux();
return 0;
diff --git a/board/freescale/t102xqds/t102xqds.c b/board/freescale/t102xqds/t102xqds.c
index 708afca..76793a1 100644
--- a/board/freescale/t102xqds/t102xqds.c
+++ b/board/freescale/t102xqds/t102xqds.c
@@ -15,7 +15,6 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include <hwconfig.h>
@@ -280,10 +279,6 @@
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
#endif
- set_liodns();
-#ifdef CONFIG_SYS_DPAA_QBMAN
- setup_portals();
-#endif
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
board_mux_lane_to_slot();
board_retimer_ds125df111_init();
diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c
index fddd240..01dbf38 100644
--- a/board/freescale/t102xrdb/t102xrdb.c
+++ b/board/freescale/t102xrdb/t102xrdb.c
@@ -14,7 +14,6 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include "t102xrdb.h"
@@ -151,10 +150,6 @@
0, flash_esel, BOOKE_PAGESZ_256M, 1);
#endif
- set_liodns();
-#ifdef CONFIG_SYS_DPAA_QBMAN
- setup_portals();
-#endif
#ifdef CONFIG_T1024RDB
board_mux_lane();
#endif
diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c
index eaca57f..d7d56b4 100644
--- a/board/freescale/t1040qds/t1040qds.c
+++ b/board/freescale/t1040qds/t1040qds.c
@@ -15,7 +15,6 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include <hwconfig.h>
@@ -153,10 +152,6 @@
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
#endif
- set_liodns();
-#ifdef CONFIG_SYS_DPAA_QBMAN
- setup_portals();
-#endif
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
return 0;
diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c
index 3227652..ec97677 100644
--- a/board/freescale/t104xrdb/t104xrdb.c
+++ b/board/freescale/t104xrdb/t104xrdb.c
@@ -16,7 +16,6 @@
#include <asm/fsl_fdt.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include "../common/sleep.h"
@@ -84,11 +83,6 @@
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
#endif
- set_liodns();
-#ifdef CONFIG_SYS_DPAA_QBMAN
- setup_portals();
-#endif
-
return 0;
}
diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c
index 7c89cd5..bfea3a1 100644
--- a/board/freescale/t208xqds/t208xqds.c
+++ b/board/freescale/t208xqds/t208xqds.c
@@ -14,7 +14,6 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
@@ -356,11 +355,6 @@
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
- set_liodns();
-#ifdef CONFIG_SYS_DPAA_QBMAN
- setup_portals();
-#endif
-
/* Disable remote I2C connection to qixis fpga */
QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c
index 0c2c1c5..0cb05aa 100644
--- a/board/freescale/t208xrdb/t208xrdb.c
+++ b/board/freescale/t208xrdb/t208xrdb.c
@@ -14,7 +14,6 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include "t208xrdb.h"
@@ -81,11 +80,6 @@
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
- set_liodns();
-#ifdef CONFIG_SYS_DPAA_QBMAN
- setup_portals();
-#endif
-
/*
* Adjust core voltage according to voltage ID
* This function changes I2C mux to channel 2.
diff --git a/board/freescale/t4qds/t4240emu.c b/board/freescale/t4qds/t4240emu.c
index 5441094..f1393f2 100644
--- a/board/freescale/t4qds/t4240emu.c
+++ b/board/freescale/t4qds/t4240emu.c
@@ -15,7 +15,6 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -56,11 +55,6 @@
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
- set_liodns();
-#ifdef CONFIG_SYS_DPAA_QBMAN
- setup_portals();
-#endif
-
return 0;
}
diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c
index 4f2cccd..d6df144 100644
--- a/board/freescale/t4qds/t4240qds.c
+++ b/board/freescale/t4qds/t4240qds.c
@@ -15,7 +15,6 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
@@ -552,11 +551,6 @@
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
- set_liodns();
-#ifdef CONFIG_SYS_DPAA_QBMAN
- setup_portals();
-#endif
-
/* Disable remote I2C connection to qixis fpga */
QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
diff --git a/board/freescale/t4rdb/t4240rdb.c b/board/freescale/t4rdb/t4240rdb.c
index fac442b..406fb13 100644
--- a/board/freescale/t4rdb/t4240rdb.c
+++ b/board/freescale/t4rdb/t4240rdb.c
@@ -15,12 +15,12 @@
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include "t4rdb.h"
#include "cpld.h"
+#include "../common/vid.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -75,10 +75,12 @@
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
- set_liodns();
-#ifdef CONFIG_SYS_DPAA_QBMAN
- setup_portals();
-#endif
+ /*
+ * Adjust core voltage according to voltage ID
+ * This function changes I2C mux to channel 2.
+ */
+ if (adjust_vdd(0))
+ printf("Warning: Adjusting core voltage failed.\n");
return 0;
}
diff --git a/common/lcd.c b/common/lcd.c
index 2f3594a..51705ad 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -89,13 +89,24 @@
/* Small utility to check that you got the colours right */
#ifdef LCD_TEST_PATTERN
+#if LCD_BPP == LCD_COLOR8
#define N_BLK_VERT 2
#define N_BLK_HOR 3
static int test_colors[N_BLK_HOR * N_BLK_VERT] = {
CONSOLE_COLOR_RED, CONSOLE_COLOR_GREEN, CONSOLE_COLOR_YELLOW,
CONSOLE_COLOR_BLUE, CONSOLE_COLOR_MAGENTA, CONSOLE_COLOR_CYAN,
+}; /*LCD_BPP == LCD_COLOR8 */
+
+#elif LCD_BPP == LCD_COLOR16
+#define N_BLK_VERT 2
+#define N_BLK_HOR 4
+
+static int test_colors[N_BLK_HOR * N_BLK_VERT] = {
+ CONSOLE_COLOR_RED, CONSOLE_COLOR_GREEN, CONSOLE_COLOR_YELLOW, CONSOLE_COLOR_BLUE,
+ CONSOLE_COLOR_MAGENTA, CONSOLE_COLOR_CYAN, CONSOLE_COLOR_GREY, CONSOLE_COLOR_WHITE,
};
+#endif /*LCD_BPP == LCD_COLOR16 */
static void test_pattern(void)
{
@@ -104,12 +115,15 @@
ushort v_step = (v_max + N_BLK_VERT - 1) / N_BLK_VERT;
ushort h_step = (h_max + N_BLK_HOR - 1) / N_BLK_HOR;
ushort v, h;
+#if LCD_BPP == LCD_COLOR8
uchar *pix = (uchar *)lcd_base;
+#elif LCD_BPP == LCD_COLOR16
+ ushort *pix = (ushort *)lcd_base;
+#endif
printf("[LCD] Test Pattern: %d x %d [%d x %d]\n",
h_max, v_max, h_step, v_step);
- /* WARNING: Code silently assumes 8bit/pixel */
for (v = 0; v < v_max; ++v) {
uchar iy = v / v_step;
for (h = 0; h < h_max; ++h) {
diff --git a/common/usb_kbd.c b/common/usb_kbd.c
index cbb1995..d84865f 100644
--- a/common/usb_kbd.c
+++ b/common/usb_kbd.c
@@ -199,7 +199,7 @@
}
}
- if ((scancode > 0x1d) && (scancode < 0x3a)) {
+ if ((scancode > 0x1d) && (scancode < 0x39)) {
/* Shift pressed */
if (modifier & (LEFT_SHIFT | RIGHT_SHIFT))
keycode = usb_kbd_numkey_shifted[scancode - 0x1e];
diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
index 27e53c1..bd8b964 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -55,6 +55,8 @@
CONFIG_SYS_NS16550=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_DM_VIDEO=y
+CONFIG_I2C_EDID=y
+CONFIG_DISPLAY=y
CONFIG_VIDEO_ROTATION=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index 15eb4d8..3b29158 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -47,6 +47,8 @@
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_DM_VIDEO=y
+CONFIG_I2C_EDID=y
+CONFIG_DISPLAY=y
CONFIG_VIDEO_ROTATION=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig
index 03348a6..ca0f9e0 100644
--- a/configs/nyan-big_defconfig
+++ b/configs/nyan-big_defconfig
@@ -26,6 +26,7 @@
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_DISPLAY=y
+CONFIG_I2C_EDID=y
CONFIG_VIDEO_TEGRA124=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_TPM=y
diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig
index 2563775..68e3b36 100644
--- a/configs/rock2_defconfig
+++ b/configs/rock2_defconfig
@@ -45,6 +45,8 @@
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_DM_VIDEO=y
+CONFIG_I2C_EDID=y
+CONFIG_DISPLAY=y
CONFIG_VIDEO_ROTATION=y
CONFIG_VIDEO_ROCKCHIP=y
CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/drivers/usb/eth/Makefile b/drivers/usb/eth/Makefile
index c92d2b0..4c44efc 100644
--- a/drivers/usb/eth/Makefile
+++ b/drivers/usb/eth/Makefile
@@ -9,3 +9,4 @@
obj-$(CONFIG_USB_ETHER_ASIX88179) += asix88179.o
obj-$(CONFIG_USB_ETHER_MCS7830) += mcs7830.o
obj-$(CONFIG_USB_ETHER_SMSC95XX) += smsc95xx.o
+obj-$(CONFIG_USB_ETHER_RTL8152) += r8152.o r8152_fw.o
diff --git a/drivers/usb/eth/r8152.c b/drivers/usb/eth/r8152.c
new file mode 100644
index 0000000..325b70c
--- /dev/null
+++ b/drivers/usb/eth/r8152.c
@@ -0,0 +1,1456 @@
+/*
+ * Copyright (c) 2015 Realtek Semiconductor Corp. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <malloc.h>
+#include <usb.h>
+#include <usb/lin_gadget_compat.h>
+#include <linux/mii.h>
+#include <linux/bitops.h>
+#include "usb_ether.h"
+#include "r8152.h"
+
+/* local vars */
+static int curr_eth_dev; /* index for name of next device detected */
+
+struct r8152_dongle {
+ unsigned short vendor;
+ unsigned short product;
+};
+
+struct r8152_version {
+ unsigned short tcr;
+ unsigned short version;
+ bool gmii;
+};
+
+static const struct r8152_dongle const r8152_dongles[] = {
+ /* Realtek */
+ { 0x0bda, 0x8050 },
+ { 0x0bda, 0x8152 },
+ { 0x0bda, 0x8153 },
+
+ /* Samsung */
+ { 0x04e8, 0xa101 },
+
+ /* Lenovo */
+ { 0x17ef, 0x304f },
+ { 0x17ef, 0x3052 },
+ { 0x17ef, 0x3054 },
+ { 0x17ef, 0x3057 },
+ { 0x17ef, 0x7205 },
+ { 0x17ef, 0x720a },
+ { 0x17ef, 0x720b },
+ { 0x17ef, 0x720c },
+
+ /* TP-LINK */
+ { 0x2357, 0x0601 },
+
+ /* Nvidia */
+ { 0x0955, 0x09ff },
+};
+
+static const struct r8152_version const r8152_versions[] = {
+ { 0x4c00, RTL_VER_01, 0 },
+ { 0x4c10, RTL_VER_02, 0 },
+ { 0x5c00, RTL_VER_03, 1 },
+ { 0x5c10, RTL_VER_04, 1 },
+ { 0x5c20, RTL_VER_05, 1 },
+ { 0x5c30, RTL_VER_06, 1 },
+ { 0x4800, RTL_VER_07, 0 },
+};
+
+static
+int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
+{
+ return usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
+ RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
+ value, index, data, size, 500);
+}
+
+static
+int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
+{
+ return usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
+ RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
+ value, index, data, size, 500);
+}
+
+int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
+ void *data, u16 type)
+{
+ u16 burst_size = 64;
+ int ret;
+ int txsize;
+
+ /* both size and index must be 4 bytes align */
+ if ((size & 3) || !size || (index & 3) || !data)
+ return -EINVAL;
+
+ if (index + size > 0xffff)
+ return -EINVAL;
+
+ while (size) {
+ txsize = min(size, burst_size);
+ ret = get_registers(tp, index, type, txsize, data);
+ if (ret < 0)
+ break;
+
+ index += txsize;
+ data += txsize;
+ size -= txsize;
+ }
+
+ return ret;
+}
+
+int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
+ u16 size, void *data, u16 type)
+{
+ int ret;
+ u16 byteen_start, byteen_end, byte_en_to_hw;
+ u16 burst_size = 512;
+ int txsize;
+
+ /* both size and index must be 4 bytes align */
+ if ((size & 3) || !size || (index & 3) || !data)
+ return -EINVAL;
+
+ if (index + size > 0xffff)
+ return -EINVAL;
+
+ byteen_start = byteen & BYTE_EN_START_MASK;
+ byteen_end = byteen & BYTE_EN_END_MASK;
+
+ byte_en_to_hw = byteen_start | (byteen_start << 4);
+ ret = set_registers(tp, index, type | byte_en_to_hw, 4, data);
+ if (ret < 0)
+ return ret;
+
+ index += 4;
+ data += 4;
+ size -= 4;
+
+ if (size) {
+ size -= 4;
+
+ while (size) {
+ txsize = min(size, burst_size);
+
+ ret = set_registers(tp, index,
+ type | BYTE_EN_DWORD,
+ txsize, data);
+ if (ret < 0)
+ return ret;
+
+ index += txsize;
+ data += txsize;
+ size -= txsize;
+ }
+
+ byte_en_to_hw = byteen_end | (byteen_end >> 4);
+ ret = set_registers(tp, index, type | byte_en_to_hw, 4, data);
+ if (ret < 0)
+ return ret;
+ }
+
+ return ret;
+}
+
+int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
+{
+ return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
+}
+
+int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
+{
+ return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
+}
+
+int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
+{
+ return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
+}
+
+int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
+{
+ return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
+}
+
+u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
+{
+ __le32 data;
+
+ generic_ocp_read(tp, index, sizeof(data), &data, type);
+
+ return __le32_to_cpu(data);
+}
+
+void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
+{
+ __le32 tmp = __cpu_to_le32(data);
+
+ generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
+}
+
+u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
+{
+ u32 data;
+ __le32 tmp;
+ u8 shift = index & 2;
+
+ index &= ~3;
+
+ generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
+
+ data = __le32_to_cpu(tmp);
+ data >>= (shift * 8);
+ data &= 0xffff;
+
+ return data;
+}
+
+void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
+{
+ u32 mask = 0xffff;
+ __le32 tmp;
+ u16 byen = BYTE_EN_WORD;
+ u8 shift = index & 2;
+
+ data &= mask;
+
+ if (index & 2) {
+ byen <<= shift;
+ mask <<= (shift * 8);
+ data <<= (shift * 8);
+ index &= ~3;
+ }
+
+ tmp = __cpu_to_le32(data);
+
+ generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
+}
+
+u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
+{
+ u32 data;
+ __le32 tmp;
+ u8 shift = index & 3;
+
+ index &= ~3;
+
+ generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
+
+ data = __le32_to_cpu(tmp);
+ data >>= (shift * 8);
+ data &= 0xff;
+
+ return data;
+}
+
+void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
+{
+ u32 mask = 0xff;
+ __le32 tmp;
+ u16 byen = BYTE_EN_BYTE;
+ u8 shift = index & 3;
+
+ data &= mask;
+
+ if (index & 3) {
+ byen <<= shift;
+ mask <<= (shift * 8);
+ data <<= (shift * 8);
+ index &= ~3;
+ }
+
+ tmp = __cpu_to_le32(data);
+
+ generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
+}
+
+u16 ocp_reg_read(struct r8152 *tp, u16 addr)
+{
+ u16 ocp_base, ocp_index;
+
+ ocp_base = addr & 0xf000;
+ if (ocp_base != tp->ocp_base) {
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
+ tp->ocp_base = ocp_base;
+ }
+
+ ocp_index = (addr & 0x0fff) | 0xb000;
+ return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
+}
+
+void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
+{
+ u16 ocp_base, ocp_index;
+
+ ocp_base = addr & 0xf000;
+ if (ocp_base != tp->ocp_base) {
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
+ tp->ocp_base = ocp_base;
+ }
+
+ ocp_index = (addr & 0x0fff) | 0xb000;
+ ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
+}
+
+static void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
+{
+ ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
+}
+
+static int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
+{
+ return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
+}
+
+void sram_write(struct r8152 *tp, u16 addr, u16 data)
+{
+ ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
+ ocp_reg_write(tp, OCP_SRAM_DATA, data);
+}
+
+int r8152_wait_for_bit(struct r8152 *tp, bool ocp_reg, u16 type, u16 index,
+ const u32 mask, bool set, unsigned int timeout)
+{
+ u32 val;
+
+ while (--timeout) {
+ if (ocp_reg)
+ val = ocp_reg_read(tp, index);
+ else
+ val = ocp_read_dword(tp, type, index);
+
+ if (!set)
+ val = ~val;
+
+ if ((val & mask) == mask)
+ return 0;
+
+ mdelay(1);
+ }
+
+ debug("%s: Timeout (index=%04x mask=%08x timeout=%d)\n",
+ __func__, index, mask, timeout);
+
+ return -ETIMEDOUT;
+}
+
+static void r8152b_reset_packet_filter(struct r8152 *tp)
+{
+ u32 ocp_data;
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
+ ocp_data &= ~FMC_FCR_MCU_EN;
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
+ ocp_data |= FMC_FCR_MCU_EN;
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
+}
+
+static void rtl8152_wait_fifo_empty(struct r8152 *tp)
+{
+ int ret;
+
+ ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
+ PLA_PHY_PWR_TXEMP, 1, R8152_WAIT_TIMEOUT);
+ if (ret)
+ debug("Timeout waiting for FIFO empty\n");
+
+ ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_TCR0,
+ TCR0_TX_EMPTY, 1, R8152_WAIT_TIMEOUT);
+ if (ret)
+ debug("Timeout waiting for TX empty\n");
+}
+
+static void rtl8152_nic_reset(struct r8152 *tp)
+{
+ int ret;
+ u32 ocp_data;
+
+ ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, BIST_CTRL);
+ ocp_data |= BIST_CTRL_SW_RESET;
+ ocp_write_dword(tp, MCU_TYPE_PLA, BIST_CTRL, ocp_data);
+
+ ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, BIST_CTRL,
+ BIST_CTRL_SW_RESET, 0, R8152_WAIT_TIMEOUT);
+ if (ret)
+ debug("Timeout waiting for NIC reset\n");
+}
+
+static u8 rtl8152_get_speed(struct r8152 *tp)
+{
+ return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
+}
+
+static void rtl_set_eee_plus(struct r8152 *tp)
+{
+ u32 ocp_data;
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
+ ocp_data &= ~EEEP_CR_EEEP_TX;
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
+}
+
+static void rxdy_gated_en(struct r8152 *tp, bool enable)
+{
+ u32 ocp_data;
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
+ if (enable)
+ ocp_data |= RXDY_GATED_EN;
+ else
+ ocp_data &= ~RXDY_GATED_EN;
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
+}
+
+static void rtl8152_set_rx_mode(struct r8152 *tp)
+{
+ u32 ocp_data;
+ __le32 tmp[2];
+
+ tmp[0] = 0xffffffff;
+ tmp[1] = 0xffffffff;
+
+ pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
+
+ ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
+ ocp_data |= RCR_APM | RCR_AM | RCR_AB;
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
+}
+
+static int rtl_enable(struct r8152 *tp)
+{
+ u32 ocp_data;
+
+ r8152b_reset_packet_filter(tp);
+
+ ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
+ ocp_data |= PLA_CR_RE | PLA_CR_TE;
+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
+
+ rxdy_gated_en(tp, false);
+
+ rtl8152_set_rx_mode(tp);
+
+ return 0;
+}
+
+static int rtl8152_enable(struct r8152 *tp)
+{
+ rtl_set_eee_plus(tp);
+
+ return rtl_enable(tp);
+}
+
+static void r8153_set_rx_early_timeout(struct r8152 *tp)
+{
+ u32 ocp_data = tp->coalesce / 8;
+
+ ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data);
+}
+
+static void r8153_set_rx_early_size(struct r8152 *tp)
+{
+ u32 ocp_data = (RTL8152_AGG_BUF_SZ - RTL8153_RMS) / 4;
+
+ ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data);
+}
+
+static int rtl8153_enable(struct r8152 *tp)
+{
+ rtl_set_eee_plus(tp);
+ r8153_set_rx_early_timeout(tp);
+ r8153_set_rx_early_size(tp);
+
+ return rtl_enable(tp);
+}
+
+static void rtl_disable(struct r8152 *tp)
+{
+ u32 ocp_data;
+
+ ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
+ ocp_data &= ~RCR_ACPT_ALL;
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
+
+ rxdy_gated_en(tp, true);
+
+ rtl8152_wait_fifo_empty(tp);
+ rtl8152_nic_reset(tp);
+}
+
+static void r8152_power_cut_en(struct r8152 *tp, bool enable)
+{
+ u32 ocp_data;
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
+ if (enable)
+ ocp_data |= POWER_CUT;
+ else
+ ocp_data &= ~POWER_CUT;
+ ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
+ ocp_data &= ~RESUME_INDICATE;
+ ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
+}
+
+static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
+{
+ u32 ocp_data;
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
+ if (enable)
+ ocp_data |= CPCR_RX_VLAN;
+ else
+ ocp_data &= ~CPCR_RX_VLAN;
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
+}
+
+static void r8153_u1u2en(struct r8152 *tp, bool enable)
+{
+ u8 u1u2[8];
+
+ if (enable)
+ memset(u1u2, 0xff, sizeof(u1u2));
+ else
+ memset(u1u2, 0x00, sizeof(u1u2));
+
+ usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
+}
+
+static void r8153_u2p3en(struct r8152 *tp, bool enable)
+{
+ u32 ocp_data;
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
+ if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04)
+ ocp_data |= U2P3_ENABLE;
+ else
+ ocp_data &= ~U2P3_ENABLE;
+ ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
+}
+
+static void r8153_power_cut_en(struct r8152 *tp, bool enable)
+{
+ u32 ocp_data;
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
+ if (enable)
+ ocp_data |= PWR_EN | PHASE2_EN;
+ else
+ ocp_data &= ~(PWR_EN | PHASE2_EN);
+ ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
+ ocp_data &= ~PCUT_STATUS;
+ ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
+}
+
+static int r8152_read_mac(struct r8152 *tp, unsigned char *macaddr)
+{
+ int ret;
+ unsigned char enetaddr[8] = {0};
+
+ ret = pla_ocp_read(tp, PLA_IDR, 8, enetaddr);
+ if (ret < 0)
+ return ret;
+
+ memcpy(macaddr, enetaddr, ETH_ALEN);
+ return 0;
+}
+
+static void r8152b_disable_aldps(struct r8152 *tp)
+{
+ ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
+ mdelay(20);
+}
+
+static void r8152b_enable_aldps(struct r8152 *tp)
+{
+ ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
+ LINKENA | DIS_SDSAVE);
+}
+
+static void rtl8152_disable(struct r8152 *tp)
+{
+ r8152b_disable_aldps(tp);
+ rtl_disable(tp);
+ r8152b_enable_aldps(tp);
+}
+
+static void r8152b_hw_phy_cfg(struct r8152 *tp)
+{
+ u16 data;
+
+ data = r8152_mdio_read(tp, MII_BMCR);
+ if (data & BMCR_PDOWN) {
+ data &= ~BMCR_PDOWN;
+ r8152_mdio_write(tp, MII_BMCR, data);
+ }
+
+ r8152b_firmware(tp);
+}
+
+static void rtl8152_reinit_ll(struct r8152 *tp)
+{
+ u32 ocp_data;
+ int ret;
+
+ ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
+ PLA_PHY_PWR_LLR, 1, R8152_WAIT_TIMEOUT);
+ if (ret)
+ debug("Timeout waiting for link list ready\n");
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
+ ocp_data |= RE_INIT_LL;
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
+
+ ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
+ PLA_PHY_PWR_LLR, 1, R8152_WAIT_TIMEOUT);
+ if (ret)
+ debug("Timeout waiting for link list ready\n");
+}
+
+static void r8152b_exit_oob(struct r8152 *tp)
+{
+ u32 ocp_data;
+
+ ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
+ ocp_data &= ~RCR_ACPT_ALL;
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
+
+ rxdy_gated_en(tp, true);
+ r8152b_hw_phy_cfg(tp);
+
+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
+
+ ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
+ ocp_data &= ~NOW_IS_OOB;
+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
+ ocp_data &= ~MCU_BORW_EN;
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
+
+ rtl8152_reinit_ll(tp);
+ rtl8152_nic_reset(tp);
+
+ /* rx share fifo credit full threshold */
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
+
+ if (tp->udev->speed == USB_SPEED_FULL ||
+ tp->udev->speed == USB_SPEED_LOW) {
+ /* rx share fifo credit near full threshold */
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
+ RXFIFO_THR2_FULL);
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
+ RXFIFO_THR3_FULL);
+ } else {
+ /* rx share fifo credit near full threshold */
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
+ RXFIFO_THR2_HIGH);
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
+ RXFIFO_THR3_HIGH);
+ }
+
+ /* TX share fifo free credit full threshold */
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
+
+ ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
+ ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
+ ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
+ TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
+
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
+ ocp_data |= TCR0_AUTO_FIFO;
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
+}
+
+static void r8152b_enter_oob(struct r8152 *tp)
+{
+ u32 ocp_data;
+
+ ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
+ ocp_data &= ~NOW_IS_OOB;
+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
+
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
+
+ rtl_disable(tp);
+
+ rtl8152_reinit_ll(tp);
+
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
+
+ rtl_rx_vlan_en(tp, false);
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
+ ocp_data |= ALDPS_PROXY_MODE;
+ ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
+
+ ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
+ ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
+
+ rxdy_gated_en(tp, false);
+
+ ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
+ ocp_data |= RCR_APM | RCR_AM | RCR_AB;
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
+}
+
+static void r8153_hw_phy_cfg(struct r8152 *tp)
+{
+ u32 ocp_data;
+ u16 data;
+
+ if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
+ tp->version == RTL_VER_05)
+ ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
+
+ data = r8152_mdio_read(tp, MII_BMCR);
+ if (data & BMCR_PDOWN) {
+ data &= ~BMCR_PDOWN;
+ r8152_mdio_write(tp, MII_BMCR, data);
+ }
+
+ r8153_firmware(tp);
+
+ if (tp->version == RTL_VER_03) {
+ data = ocp_reg_read(tp, OCP_EEE_CFG);
+ data &= ~CTAP_SHORT_EN;
+ ocp_reg_write(tp, OCP_EEE_CFG, data);
+ }
+
+ data = ocp_reg_read(tp, OCP_POWER_CFG);
+ data |= EEE_CLKDIV_EN;
+ ocp_reg_write(tp, OCP_POWER_CFG, data);
+
+ data = ocp_reg_read(tp, OCP_DOWN_SPEED);
+ data |= EN_10M_BGOFF;
+ ocp_reg_write(tp, OCP_DOWN_SPEED, data);
+ data = ocp_reg_read(tp, OCP_POWER_CFG);
+ data |= EN_10M_PLLOFF;
+ ocp_reg_write(tp, OCP_POWER_CFG, data);
+ sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
+ ocp_data |= PFM_PWM_SWITCH;
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
+
+ /* Enable LPF corner auto tune */
+ sram_write(tp, SRAM_LPF_CFG, 0xf70f);
+
+ /* Adjust 10M Amplitude */
+ sram_write(tp, SRAM_10M_AMP1, 0x00af);
+ sram_write(tp, SRAM_10M_AMP2, 0x0208);
+}
+
+static void r8153_first_init(struct r8152 *tp)
+{
+ u32 ocp_data;
+
+ rxdy_gated_en(tp, true);
+
+ ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
+ ocp_data &= ~RCR_ACPT_ALL;
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
+
+ r8153_hw_phy_cfg(tp);
+
+ rtl8152_nic_reset(tp);
+
+ ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
+ ocp_data &= ~NOW_IS_OOB;
+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
+ ocp_data &= ~MCU_BORW_EN;
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
+
+ rtl8152_reinit_ll(tp);
+
+ rtl_rx_vlan_en(tp, false);
+
+ ocp_data = RTL8153_RMS;
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
+ ocp_data |= TCR0_AUTO_FIFO;
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
+
+ rtl8152_nic_reset(tp);
+
+ /* rx share fifo credit full threshold */
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
+ /* TX share fifo free credit full threshold */
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
+
+ /* rx aggregation */
+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
+
+ ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
+ ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
+}
+
+static void r8153_enter_oob(struct r8152 *tp)
+{
+ u32 ocp_data;
+
+ ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
+ ocp_data &= ~NOW_IS_OOB;
+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
+
+ rtl_disable(tp);
+
+ rtl8152_reinit_ll(tp);
+
+ ocp_data = RTL8153_RMS;
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
+ ocp_data &= ~TEREDO_WAKE_MASK;
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
+
+ rtl_rx_vlan_en(tp, false);
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
+ ocp_data |= ALDPS_PROXY_MODE;
+ ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
+
+ ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
+ ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
+
+ rxdy_gated_en(tp, false);
+
+ ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
+ ocp_data |= RCR_APM | RCR_AM | RCR_AB;
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
+}
+
+static void r8153_disable_aldps(struct r8152 *tp)
+{
+ u16 data;
+
+ data = ocp_reg_read(tp, OCP_POWER_CFG);
+ data &= ~EN_ALDPS;
+ ocp_reg_write(tp, OCP_POWER_CFG, data);
+ mdelay(20);
+}
+
+static void rtl8153_disable(struct r8152 *tp)
+{
+ r8153_disable_aldps(tp);
+ rtl_disable(tp);
+}
+
+static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
+{
+ u16 bmcr, anar, gbcr;
+
+ anar = r8152_mdio_read(tp, MII_ADVERTISE);
+ anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
+ ADVERTISE_100HALF | ADVERTISE_100FULL);
+ if (tp->supports_gmii) {
+ gbcr = r8152_mdio_read(tp, MII_CTRL1000);
+ gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
+ } else {
+ gbcr = 0;
+ }
+
+ if (autoneg == AUTONEG_DISABLE) {
+ if (speed == SPEED_10) {
+ bmcr = 0;
+ anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
+ } else if (speed == SPEED_100) {
+ bmcr = BMCR_SPEED100;
+ anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
+ } else if (speed == SPEED_1000 && tp->supports_gmii) {
+ bmcr = BMCR_SPEED1000;
+ gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
+ } else {
+ return -EINVAL;
+ }
+
+ if (duplex == DUPLEX_FULL)
+ bmcr |= BMCR_FULLDPLX;
+ } else {
+ if (speed == SPEED_10) {
+ if (duplex == DUPLEX_FULL)
+ anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
+ else
+ anar |= ADVERTISE_10HALF;
+ } else if (speed == SPEED_100) {
+ if (duplex == DUPLEX_FULL) {
+ anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
+ anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
+ } else {
+ anar |= ADVERTISE_10HALF;
+ anar |= ADVERTISE_100HALF;
+ }
+ } else if (speed == SPEED_1000 && tp->supports_gmii) {
+ if (duplex == DUPLEX_FULL) {
+ anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
+ anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
+ gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
+ } else {
+ anar |= ADVERTISE_10HALF;
+ anar |= ADVERTISE_100HALF;
+ gbcr |= ADVERTISE_1000HALF;
+ }
+ } else {
+ return -EINVAL;
+ }
+
+ bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
+ }
+
+ if (tp->supports_gmii)
+ r8152_mdio_write(tp, MII_CTRL1000, gbcr);
+
+ r8152_mdio_write(tp, MII_ADVERTISE, anar);
+ r8152_mdio_write(tp, MII_BMCR, bmcr);
+
+ return 0;
+}
+
+static void rtl8152_up(struct r8152 *tp)
+{
+ r8152b_disable_aldps(tp);
+ r8152b_exit_oob(tp);
+ r8152b_enable_aldps(tp);
+}
+
+static void rtl8152_down(struct r8152 *tp)
+{
+ r8152_power_cut_en(tp, false);
+ r8152b_disable_aldps(tp);
+ r8152b_enter_oob(tp);
+ r8152b_enable_aldps(tp);
+}
+
+static void rtl8153_up(struct r8152 *tp)
+{
+ r8153_u1u2en(tp, false);
+ r8153_disable_aldps(tp);
+ r8153_first_init(tp);
+ r8153_u2p3en(tp, false);
+}
+
+static void rtl8153_down(struct r8152 *tp)
+{
+ r8153_u1u2en(tp, false);
+ r8153_u2p3en(tp, false);
+ r8153_power_cut_en(tp, false);
+ r8153_disable_aldps(tp);
+ r8153_enter_oob(tp);
+}
+
+static void r8152b_get_version(struct r8152 *tp)
+{
+ u32 ocp_data;
+ u16 tcr;
+ int i;
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
+ tcr = (u16)(ocp_data & VERSION_MASK);
+
+ for (i = 0; i < ARRAY_SIZE(r8152_versions); i++) {
+ if (tcr == r8152_versions[i].tcr) {
+ /* Found a supported version */
+ tp->version = r8152_versions[i].version;
+ tp->supports_gmii = r8152_versions[i].gmii;
+ break;
+ }
+ }
+
+ if (tp->version == RTL_VER_UNKNOWN)
+ debug("r8152 Unknown tcr version 0x%04x\n", tcr);
+}
+
+static void r8152b_enable_fc(struct r8152 *tp)
+{
+ u16 anar;
+ anar = r8152_mdio_read(tp, MII_ADVERTISE);
+ anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
+ r8152_mdio_write(tp, MII_ADVERTISE, anar);
+}
+
+static void rtl_tally_reset(struct r8152 *tp)
+{
+ u32 ocp_data;
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
+ ocp_data |= TALLY_RESET;
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
+}
+
+static void r8152b_init(struct r8152 *tp)
+{
+ u32 ocp_data;
+
+ r8152b_disable_aldps(tp);
+
+ if (tp->version == RTL_VER_01) {
+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
+ ocp_data &= ~LED_MODE_MASK;
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
+ }
+
+ r8152_power_cut_en(tp, false);
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
+ ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
+ ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
+ ocp_data &= ~MCU_CLK_RATIO_MASK;
+ ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
+ ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
+ SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_TIMER);
+ ocp_data |= BIT(15);
+ ocp_write_word(tp, MCU_TYPE_USB, USB_USB_TIMER, ocp_data);
+ ocp_write_word(tp, MCU_TYPE_USB, 0xcbfc, 0x03e8);
+ ocp_data &= ~BIT(15);
+ ocp_write_word(tp, MCU_TYPE_USB, USB_USB_TIMER, ocp_data);
+
+ r8152b_enable_fc(tp);
+ rtl_tally_reset(tp);
+
+ /* enable rx aggregation */
+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
+
+ ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
+ ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
+}
+
+static void r8153_init(struct r8152 *tp)
+{
+ int i;
+ u32 ocp_data;
+
+ r8153_disable_aldps(tp);
+ r8153_u1u2en(tp, false);
+
+ r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_BOOT_CTRL,
+ AUTOLOAD_DONE, 1, R8152_WAIT_TIMEOUT);
+
+ for (i = 0; i < R8152_WAIT_TIMEOUT; i++) {
+ ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
+ if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
+ break;
+
+ mdelay(1);
+ }
+
+ r8153_u2p3en(tp, false);
+
+ if (tp->version == RTL_VER_04) {
+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
+ ocp_data &= ~pwd_dn_scale_mask;
+ ocp_data |= pwd_dn_scale(96);
+ ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
+
+ ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
+ ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
+ ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
+ } else if (tp->version == RTL_VER_05) {
+ ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
+ ocp_data &= ~ECM_ALDPS;
+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
+
+ ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
+ if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
+ ocp_data &= ~DYNAMIC_BURST;
+ else
+ ocp_data |= DYNAMIC_BURST;
+ ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
+ } else if (tp->version == RTL_VER_06) {
+ ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
+ if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
+ ocp_data &= ~DYNAMIC_BURST;
+ else
+ ocp_data |= DYNAMIC_BURST;
+ ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
+ }
+
+ ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
+ ocp_data |= EP4_FULL_FC;
+ ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
+ ocp_data &= ~TIMER11_EN;
+ ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
+ ocp_data &= ~LED_MODE_MASK;
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
+
+ ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
+ if (tp->version == RTL_VER_04 && tp->udev->speed != USB_SPEED_SUPER)
+ ocp_data |= LPM_TIMER_500MS;
+ else
+ ocp_data |= LPM_TIMER_500US;
+ ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
+ ocp_data &= ~SEN_VAL_MASK;
+ ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
+ ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
+
+ ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
+
+ r8153_power_cut_en(tp, false);
+
+ r8152b_enable_fc(tp);
+ rtl_tally_reset(tp);
+}
+
+static void rtl8152_unload(struct r8152 *tp)
+{
+ if (tp->version != RTL_VER_01)
+ r8152_power_cut_en(tp, true);
+}
+
+static void rtl8153_unload(struct r8152 *tp)
+{
+ r8153_power_cut_en(tp, false);
+}
+
+static int rtl_ops_init(struct r8152 *tp)
+{
+ struct rtl_ops *ops = &tp->rtl_ops;
+ int ret = 0;
+
+ switch (tp->version) {
+ case RTL_VER_01:
+ case RTL_VER_02:
+ case RTL_VER_07:
+ ops->init = r8152b_init;
+ ops->enable = rtl8152_enable;
+ ops->disable = rtl8152_disable;
+ ops->up = rtl8152_up;
+ ops->down = rtl8152_down;
+ ops->unload = rtl8152_unload;
+ break;
+
+ case RTL_VER_03:
+ case RTL_VER_04:
+ case RTL_VER_05:
+ case RTL_VER_06:
+ ops->init = r8153_init;
+ ops->enable = rtl8153_enable;
+ ops->disable = rtl8153_disable;
+ ops->up = rtl8153_up;
+ ops->down = rtl8153_down;
+ ops->unload = rtl8153_unload;
+ break;
+
+ default:
+ ret = -ENODEV;
+ printf("r8152 Unknown Device\n");
+ break;
+ }
+
+ return ret;
+}
+
+static int r8152_init(struct eth_device *eth, bd_t *bd)
+{
+ struct ueth_data *dev = (struct ueth_data *)eth->priv;
+ struct r8152 *tp = (struct r8152 *)dev->dev_priv;
+
+ u8 speed;
+ int timeout = 0;
+ int link_detected;
+
+ debug("** %s()\n", __func__);
+
+ do {
+ speed = rtl8152_get_speed(tp);
+
+ link_detected = speed & LINK_STATUS;
+ if (!link_detected) {
+ if (timeout == 0)
+ printf("Waiting for Ethernet connection... ");
+ mdelay(TIMEOUT_RESOLUTION);
+ timeout += TIMEOUT_RESOLUTION;
+ }
+ } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
+ if (link_detected) {
+ tp->rtl_ops.enable(tp);
+
+ if (timeout != 0)
+ printf("done.\n");
+ } else {
+ printf("unable to connect.\n");
+ }
+
+ return 0;
+}
+
+static int r8152_send(struct eth_device *eth, void *packet, int length)
+{
+ struct ueth_data *dev = (struct ueth_data *)eth->priv;
+
+ u32 opts1, opts2 = 0;
+
+ int err;
+
+ int actual_len;
+ unsigned char msg[PKTSIZE + sizeof(struct tx_desc)];
+ struct tx_desc *tx_desc = (struct tx_desc *)msg;
+
+ debug("** %s(), len %d\n", __func__, length);
+
+ opts1 = length | TX_FS | TX_LS;
+
+ tx_desc->opts2 = cpu_to_le32(opts2);
+ tx_desc->opts1 = cpu_to_le32(opts1);
+
+ memcpy(msg + sizeof(struct tx_desc), (void *)packet, length);
+
+ err = usb_bulk_msg(dev->pusb_dev,
+ usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
+ (void *)msg,
+ length + sizeof(struct tx_desc),
+ &actual_len,
+ USB_BULK_SEND_TIMEOUT);
+ debug("Tx: len = %zu, actual = %u, err = %d\n",
+ length + sizeof(struct tx_desc), actual_len, err);
+
+ return err;
+}
+
+static int r8152_recv(struct eth_device *eth)
+{
+ struct ueth_data *dev = (struct ueth_data *)eth->priv;
+
+ static unsigned char recv_buf[RTL8152_AGG_BUF_SZ];
+ unsigned char *pkt_ptr;
+ int err;
+ int actual_len;
+ u16 packet_len;
+
+ u32 bytes_process = 0;
+ struct rx_desc *rx_desc;
+
+ debug("** %s()\n", __func__);
+
+ err = usb_bulk_msg(dev->pusb_dev,
+ usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
+ (void *)recv_buf,
+ RTL8152_AGG_BUF_SZ,
+ &actual_len,
+ USB_BULK_RECV_TIMEOUT);
+ debug("Rx: len = %u, actual = %u, err = %d\n", RTL8152_AGG_BUF_SZ,
+ actual_len, err);
+ if (err != 0) {
+ debug("Rx: failed to receive\n");
+ return -1;
+ }
+ if (actual_len > RTL8152_AGG_BUF_SZ) {
+ debug("Rx: received too many bytes %d\n", actual_len);
+ return -1;
+ }
+
+ while (bytes_process < actual_len) {
+ rx_desc = (struct rx_desc *)(recv_buf + bytes_process);
+ pkt_ptr = recv_buf + sizeof(struct rx_desc) + bytes_process;
+
+ packet_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
+ packet_len -= CRC_SIZE;
+
+ net_process_received_packet(pkt_ptr, packet_len);
+
+ bytes_process +=
+ (packet_len + sizeof(struct rx_desc) + CRC_SIZE);
+
+ if (bytes_process % 8)
+ bytes_process = bytes_process + 8 - (bytes_process % 8);
+ }
+
+ return 0;
+}
+
+static void r8152_halt(struct eth_device *eth)
+{
+ struct ueth_data *dev = (struct ueth_data *)eth->priv;
+ struct r8152 *tp = (struct r8152 *)dev->dev_priv;
+
+ debug("** %s()\n", __func__);
+
+ tp->rtl_ops.disable(tp);
+}
+
+static int r8152_write_hwaddr(struct eth_device *eth)
+{
+ struct ueth_data *dev = (struct ueth_data *)eth->priv;
+ struct r8152 *tp = (struct r8152 *)dev->dev_priv;
+
+ unsigned char enetaddr[8] = {0};
+
+ memcpy(enetaddr, eth->enetaddr, ETH_ALEN);
+
+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
+ pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, enetaddr);
+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
+
+ debug("MAC %pM\n", eth->enetaddr);
+ return 0;
+}
+
+void r8152_eth_before_probe(void)
+{
+ curr_eth_dev = 0;
+}
+
+/* Probe to see if a new device is actually an realtek device */
+int r8152_eth_probe(struct usb_device *dev, unsigned int ifnum,
+ struct ueth_data *ss)
+{
+ struct usb_interface *iface;
+ struct usb_interface_descriptor *iface_desc;
+ int ep_in_found = 0, ep_out_found = 0;
+ int i;
+
+ struct r8152 *tp;
+
+ /* let's examine the device now */
+ iface = &dev->config.if_desc[ifnum];
+ iface_desc = &dev->config.if_desc[ifnum].desc;
+
+ for (i = 0; i < ARRAY_SIZE(r8152_dongles); i++) {
+ if (dev->descriptor.idVendor == r8152_dongles[i].vendor &&
+ dev->descriptor.idProduct == r8152_dongles[i].product)
+ /* Found a supported dongle */
+ break;
+ }
+
+ if (i == ARRAY_SIZE(r8152_dongles))
+ return 0;
+
+ memset(ss, 0, sizeof(struct ueth_data));
+
+ /* At this point, we know we've got a live one */
+ debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n",
+ dev->descriptor.idVendor, dev->descriptor.idProduct);
+
+ /* Initialize the ueth_data structure with some useful info */
+ ss->ifnum = ifnum;
+ ss->pusb_dev = dev;
+ ss->subclass = iface_desc->bInterfaceSubClass;
+ ss->protocol = iface_desc->bInterfaceProtocol;
+
+ /* alloc driver private */
+ ss->dev_priv = calloc(1, sizeof(struct r8152));
+
+ if (!ss->dev_priv)
+ return 0;
+
+ /*
+ * We are expecting a minimum of 3 endpoints - in, out (bulk), and
+ * int. We will ignore any others.
+ */
+ for (i = 0; i < iface_desc->bNumEndpoints; i++) {
+ /* is it an BULK endpoint? */
+ if ((iface->ep_desc[i].bmAttributes &
+ USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
+ u8 ep_addr = iface->ep_desc[i].bEndpointAddress;
+ if ((ep_addr & USB_DIR_IN) && !ep_in_found) {
+ ss->ep_in = ep_addr &
+ USB_ENDPOINT_NUMBER_MASK;
+ ep_in_found = 1;
+ } else {
+ if (!ep_out_found) {
+ ss->ep_out = ep_addr &
+ USB_ENDPOINT_NUMBER_MASK;
+ ep_out_found = 1;
+ }
+ }
+ }
+
+ /* is it an interrupt endpoint? */
+ if ((iface->ep_desc[i].bmAttributes &
+ USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
+ ss->ep_int = iface->ep_desc[i].bEndpointAddress &
+ USB_ENDPOINT_NUMBER_MASK;
+ ss->irqinterval = iface->ep_desc[i].bInterval;
+ }
+ }
+
+ debug("Endpoints In %d Out %d Int %d\n",
+ ss->ep_in, ss->ep_out, ss->ep_int);
+
+ /* Do some basic sanity checks, and bail if we find a problem */
+ if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
+ !ss->ep_in || !ss->ep_out || !ss->ep_int) {
+ debug("Problems with device\n");
+ return 0;
+ }
+
+ dev->privptr = (void *)ss;
+
+ tp = ss->dev_priv;
+ tp->udev = dev;
+ tp->intf = iface;
+
+ r8152b_get_version(tp);
+
+ if (rtl_ops_init(tp))
+ return 0;
+
+ tp->rtl_ops.init(tp);
+ tp->rtl_ops.up(tp);
+
+ rtl8152_set_speed(tp, AUTONEG_ENABLE,
+ tp->supports_gmii ? SPEED_1000 : SPEED_100,
+ DUPLEX_FULL);
+
+ return 1;
+}
+
+int r8152_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
+ struct eth_device *eth)
+{
+ if (!eth) {
+ debug("%s: missing parameter.\n", __func__);
+ return 0;
+ }
+
+ sprintf(eth->name, "%s#%d", R8152_BASE_NAME, curr_eth_dev++);
+ eth->init = r8152_init;
+ eth->send = r8152_send;
+ eth->recv = r8152_recv;
+ eth->halt = r8152_halt;
+ eth->write_hwaddr = r8152_write_hwaddr;
+ eth->priv = ss;
+
+ /* Get the MAC address */
+ if (r8152_read_mac(ss->dev_priv, eth->enetaddr) < 0)
+ return 0;
+
+ debug("MAC %pM\n", eth->enetaddr);
+ return 1;
+}
diff --git a/drivers/usb/eth/r8152.h b/drivers/usb/eth/r8152.h
new file mode 100644
index 0000000..cd44da2
--- /dev/null
+++ b/drivers/usb/eth/r8152.h
@@ -0,0 +1,631 @@
+/*
+ * Copyright (c) 2015 Realtek Semiconductor Corp. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ */
+
+#ifndef _RTL8152_ETH_H
+#define _RTL8152_ETH_H
+
+#define R8152_BASE_NAME "r8152"
+
+#define PLA_IDR 0xc000
+#define PLA_RCR 0xc010
+#define PLA_RMS 0xc016
+#define PLA_RXFIFO_CTRL0 0xc0a0
+#define PLA_RXFIFO_CTRL1 0xc0a4
+#define PLA_RXFIFO_CTRL2 0xc0a8
+#define PLA_DMY_REG0 0xc0b0
+#define PLA_FMC 0xc0b4
+#define PLA_CFG_WOL 0xc0b6
+#define PLA_TEREDO_CFG 0xc0bc
+#define PLA_MAR 0xcd00
+#define PLA_BACKUP 0xd000
+#define PAL_BDC_CR 0xd1a0
+#define PLA_TEREDO_TIMER 0xd2cc
+#define PLA_REALWOW_TIMER 0xd2e8
+#define PLA_LEDSEL 0xdd90
+#define PLA_LED_FEATURE 0xdd92
+#define PLA_PHYAR 0xde00
+#define PLA_BOOT_CTRL 0xe004
+#define PLA_GPHY_INTR_IMR 0xe022
+#define PLA_EEE_CR 0xe040
+#define PLA_EEEP_CR 0xe080
+#define PLA_MAC_PWR_CTRL 0xe0c0
+#define PLA_MAC_PWR_CTRL2 0xe0ca
+#define PLA_MAC_PWR_CTRL3 0xe0cc
+#define PLA_MAC_PWR_CTRL4 0xe0ce
+#define PLA_WDT6_CTRL 0xe428
+#define PLA_TCR0 0xe610
+#define PLA_TCR1 0xe612
+#define PLA_MTPS 0xe615
+#define PLA_TXFIFO_CTRL 0xe618
+#define PLA_RSTTALLY 0xe800
+#define BIST_CTRL 0xe810
+#define PLA_CR 0xe813
+#define PLA_CRWECR 0xe81c
+#define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
+#define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
+#define PLA_CONFIG5 0xe822
+#define PLA_PHY_PWR 0xe84c
+#define PLA_OOB_CTRL 0xe84f
+#define PLA_CPCR 0xe854
+#define PLA_MISC_0 0xe858
+#define PLA_MISC_1 0xe85a
+#define PLA_OCP_GPHY_BASE 0xe86c
+#define PLA_TALLYCNT 0xe890
+#define PLA_SFF_STS_7 0xe8de
+#define PLA_PHYSTATUS 0xe908
+#define PLA_BP_BA 0xfc26
+#define PLA_BP_0 0xfc28
+#define PLA_BP_1 0xfc2a
+#define PLA_BP_2 0xfc2c
+#define PLA_BP_3 0xfc2e
+#define PLA_BP_4 0xfc30
+#define PLA_BP_5 0xfc32
+#define PLA_BP_6 0xfc34
+#define PLA_BP_7 0xfc36
+#define PLA_BP_EN 0xfc38
+
+#define USB_USB2PHY 0xb41e
+#define USB_SSPHYLINK2 0xb428
+#define USB_U2P3_CTRL 0xb460
+#define USB_CSR_DUMMY1 0xb464
+#define USB_CSR_DUMMY2 0xb466
+#define USB_DEV_STAT 0xb808
+#define USB_CONNECT_TIMER 0xcbf8
+#define USB_BURST_SIZE 0xcfc0
+#define USB_USB_CTRL 0xd406
+#define USB_PHY_CTRL 0xd408
+#define USB_TX_AGG 0xd40a
+#define USB_RX_BUF_TH 0xd40c
+#define USB_USB_TIMER 0xd428
+#define USB_RX_EARLY_TIMEOUT 0xd42c
+#define USB_RX_EARLY_SIZE 0xd42e
+#define USB_PM_CTRL_STATUS 0xd432
+#define USB_TX_DMA 0xd434
+#define USB_TOLERANCE 0xd490
+#define USB_LPM_CTRL 0xd41a
+#define USB_UPS_CTRL 0xd800
+#define USB_MISC_0 0xd81a
+#define USB_POWER_CUT 0xd80a
+#define USB_AFE_CTRL2 0xd824
+#define USB_WDT11_CTRL 0xe43c
+#define USB_BP_BA 0xfc26
+#define USB_BP_0 0xfc28
+#define USB_BP_1 0xfc2a
+#define USB_BP_2 0xfc2c
+#define USB_BP_3 0xfc2e
+#define USB_BP_4 0xfc30
+#define USB_BP_5 0xfc32
+#define USB_BP_6 0xfc34
+#define USB_BP_7 0xfc36
+#define USB_BP_EN 0xfc38
+
+/* OCP Registers */
+#define OCP_ALDPS_CONFIG 0x2010
+#define OCP_EEE_CONFIG1 0x2080
+#define OCP_EEE_CONFIG2 0x2092
+#define OCP_EEE_CONFIG3 0x2094
+#define OCP_BASE_MII 0xa400
+#define OCP_EEE_AR 0xa41a
+#define OCP_EEE_DATA 0xa41c
+#define OCP_PHY_STATUS 0xa420
+#define OCP_POWER_CFG 0xa430
+#define OCP_EEE_CFG 0xa432
+#define OCP_SRAM_ADDR 0xa436
+#define OCP_SRAM_DATA 0xa438
+#define OCP_DOWN_SPEED 0xa442
+#define OCP_EEE_ABLE 0xa5c4
+#define OCP_EEE_ADV 0xa5d0
+#define OCP_EEE_LPABLE 0xa5d2
+#define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
+#define OCP_ADC_CFG 0xbc06
+
+/* SRAM Register */
+#define SRAM_LPF_CFG 0x8012
+#define SRAM_10M_AMP1 0x8080
+#define SRAM_10M_AMP2 0x8082
+#define SRAM_IMPEDANCE 0x8084
+
+/* PLA_RCR */
+#define RCR_AAP 0x00000001
+#define RCR_APM 0x00000002
+#define RCR_AM 0x00000004
+#define RCR_AB 0x00000008
+#define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
+
+/* PLA_RXFIFO_CTRL0 */
+#define RXFIFO_THR1_NORMAL 0x00080002
+#define RXFIFO_THR1_OOB 0x01800003
+
+/* PLA_RXFIFO_CTRL1 */
+#define RXFIFO_THR2_FULL 0x00000060
+#define RXFIFO_THR2_HIGH 0x00000038
+#define RXFIFO_THR2_OOB 0x0000004a
+#define RXFIFO_THR2_NORMAL 0x00a0
+
+/* PLA_RXFIFO_CTRL2 */
+#define RXFIFO_THR3_FULL 0x00000078
+#define RXFIFO_THR3_HIGH 0x00000048
+#define RXFIFO_THR3_OOB 0x0000005a
+#define RXFIFO_THR3_NORMAL 0x0110
+
+/* PLA_TXFIFO_CTRL */
+#define TXFIFO_THR_NORMAL 0x00400008
+#define TXFIFO_THR_NORMAL2 0x01000008
+
+/* PLA_DMY_REG0 */
+#define ECM_ALDPS 0x0002
+
+/* PLA_FMC */
+#define FMC_FCR_MCU_EN 0x0001
+
+/* PLA_EEEP_CR */
+#define EEEP_CR_EEEP_TX 0x0002
+
+/* PLA_WDT6_CTRL */
+#define WDT6_SET_MODE 0x0010
+
+/* PLA_TCR0 */
+#define TCR0_TX_EMPTY 0x0800
+#define TCR0_AUTO_FIFO 0x0080
+
+/* PLA_TCR1 */
+#define VERSION_MASK 0x7cf0
+
+/* PLA_MTPS */
+#define MTPS_JUMBO (12 * 1024 / 64)
+#define MTPS_DEFAULT (6 * 1024 / 64)
+
+/* PLA_RSTTALLY */
+#define TALLY_RESET 0x0001
+
+/* PLA_CR */
+#define PLA_CR_RST 0x10
+#define PLA_CR_RE 0x08
+#define PLA_CR_TE 0x04
+
+/* PLA_BIST_CTRL */
+#define BIST_CTRL_SW_RESET (0x10 << 24)
+
+/* PLA_CRWECR */
+#define CRWECR_NORAML 0x00
+#define CRWECR_CONFIG 0xc0
+
+/* PLA_OOB_CTRL */
+#define NOW_IS_OOB 0x80
+#define TXFIFO_EMPTY 0x20
+#define RXFIFO_EMPTY 0x10
+#define LINK_LIST_READY 0x02
+#define DIS_MCU_CLROOB 0x01
+#define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
+
+/* PLA_PHY_PWR */
+#define PLA_PHY_PWR_LLR (LINK_LIST_READY << 24)
+#define PLA_PHY_PWR_TXEMP (TXFIFO_EMPTY << 24)
+
+/* PLA_MISC_1 */
+#define RXDY_GATED_EN 0x0008
+
+/* PLA_SFF_STS_7 */
+#define RE_INIT_LL 0x8000
+#define MCU_BORW_EN 0x4000
+
+/* PLA_CPCR */
+#define CPCR_RX_VLAN 0x0040
+
+/* PLA_CFG_WOL */
+#define MAGIC_EN 0x0001
+
+/* PLA_TEREDO_CFG */
+#define TEREDO_SEL 0x8000
+#define TEREDO_WAKE_MASK 0x7f00
+#define TEREDO_RS_EVENT_MASK 0x00fe
+#define OOB_TEREDO_EN 0x0001
+
+/* PAL_BDC_CR */
+#define ALDPS_PROXY_MODE 0x0001
+
+/* PLA_CONFIG34 */
+#define LINK_ON_WAKE_EN 0x0010
+#define LINK_OFF_WAKE_EN 0x0008
+
+/* PLA_CONFIG5 */
+#define BWF_EN 0x0040
+#define MWF_EN 0x0020
+#define UWF_EN 0x0010
+#define LAN_WAKE_EN 0x0002
+
+/* PLA_LED_FEATURE */
+#define LED_MODE_MASK 0x0700
+
+/* PLA_PHY_PWR */
+#define TX_10M_IDLE_EN 0x0080
+#define PFM_PWM_SWITCH 0x0040
+
+/* PLA_MAC_PWR_CTRL */
+#define D3_CLK_GATED_EN 0x00004000
+#define MCU_CLK_RATIO 0x07010f07
+#define MCU_CLK_RATIO_MASK 0x0f0f0f0f
+#define ALDPS_SPDWN_RATIO 0x0f87
+
+/* PLA_MAC_PWR_CTRL2 */
+#define EEE_SPDWN_RATIO 0x8007
+
+/* PLA_MAC_PWR_CTRL3 */
+#define PKT_AVAIL_SPDWN_EN 0x0100
+#define SUSPEND_SPDWN_EN 0x0004
+#define U1U2_SPDWN_EN 0x0002
+#define L1_SPDWN_EN 0x0001
+
+/* PLA_MAC_PWR_CTRL4 */
+#define PWRSAVE_SPDWN_EN 0x1000
+#define RXDV_SPDWN_EN 0x0800
+#define TX10MIDLE_EN 0x0100
+#define TP100_SPDWN_EN 0x0020
+#define TP500_SPDWN_EN 0x0010
+#define TP1000_SPDWN_EN 0x0008
+#define EEE_SPDWN_EN 0x0001
+
+/* PLA_GPHY_INTR_IMR */
+#define GPHY_STS_MSK 0x0001
+#define SPEED_DOWN_MSK 0x0002
+#define SPDWN_RXDV_MSK 0x0004
+#define SPDWN_LINKCHG_MSK 0x0008
+
+/* PLA_PHYAR */
+#define PHYAR_FLAG 0x80000000
+
+/* PLA_EEE_CR */
+#define EEE_RX_EN 0x0001
+#define EEE_TX_EN 0x0002
+
+/* PLA_BOOT_CTRL */
+#define AUTOLOAD_DONE 0x0002
+
+/* USB_USB2PHY */
+#define USB2PHY_SUSPEND 0x0001
+#define USB2PHY_L1 0x0002
+
+/* USB_SSPHYLINK2 */
+#define pwd_dn_scale_mask 0x3ffe
+#define pwd_dn_scale(x) ((x) << 1)
+
+/* USB_CSR_DUMMY1 */
+#define DYNAMIC_BURST 0x0001
+
+/* USB_CSR_DUMMY2 */
+#define EP4_FULL_FC 0x0001
+
+/* USB_DEV_STAT */
+#define STAT_SPEED_MASK 0x0006
+#define STAT_SPEED_HIGH 0x0000
+#define STAT_SPEED_FULL 0x0002
+
+/* USB_TX_AGG */
+#define TX_AGG_MAX_THRESHOLD 0x03
+
+/* USB_RX_BUF_TH */
+#define RX_THR_SUPPER 0x0c350180
+#define RX_THR_HIGH 0x7a120180
+#define RX_THR_SLOW 0xffff0180
+
+/* USB_TX_DMA */
+#define TEST_MODE_DISABLE 0x00000001
+#define TX_SIZE_ADJUST1 0x00000100
+
+/* USB_UPS_CTRL */
+#define POWER_CUT 0x0100
+
+/* USB_PM_CTRL_STATUS */
+#define RESUME_INDICATE 0x0001
+
+/* USB_USB_CTRL */
+#define RX_AGG_DISABLE 0x0010
+#define RX_ZERO_EN 0x0080
+
+/* USB_U2P3_CTRL */
+#define U2P3_ENABLE 0x0001
+
+/* USB_POWER_CUT */
+#define PWR_EN 0x0001
+#define PHASE2_EN 0x0008
+
+/* USB_MISC_0 */
+#define PCUT_STATUS 0x0001
+
+/* USB_RX_EARLY_TIMEOUT */
+#define COALESCE_SUPER 85000U
+#define COALESCE_HIGH 250000U
+#define COALESCE_SLOW 524280U
+
+/* USB_WDT11_CTRL */
+#define TIMER11_EN 0x0001
+
+/* USB_LPM_CTRL */
+/* bit 4 ~ 5: fifo empty boundary */
+#define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
+/* bit 2 ~ 3: LMP timer */
+#define LPM_TIMER_MASK 0x0c
+#define LPM_TIMER_500MS 0x04 /* 500 ms */
+#define LPM_TIMER_500US 0x0c /* 500 us */
+#define ROK_EXIT_LPM 0x02
+
+/* USB_AFE_CTRL2 */
+#define SEN_VAL_MASK 0xf800
+#define SEN_VAL_NORMAL 0xa000
+#define SEL_RXIDLE 0x0100
+
+/* OCP_ALDPS_CONFIG */
+#define ENPWRSAVE 0x8000
+#define ENPDNPS 0x0200
+#define LINKENA 0x0100
+#define DIS_SDSAVE 0x0010
+
+/* OCP_PHY_STATUS */
+#define PHY_STAT_MASK 0x0007
+#define PHY_STAT_LAN_ON 3
+#define PHY_STAT_PWRDN 5
+
+/* OCP_POWER_CFG */
+#define EEE_CLKDIV_EN 0x8000
+#define EN_ALDPS 0x0004
+#define EN_10M_PLLOFF 0x0001
+
+/* OCP_EEE_CONFIG1 */
+#define RG_TXLPI_MSK_HFDUP 0x8000
+#define RG_MATCLR_EN 0x4000
+#define EEE_10_CAP 0x2000
+#define EEE_NWAY_EN 0x1000
+#define TX_QUIET_EN 0x0200
+#define RX_QUIET_EN 0x0100
+#define sd_rise_time_mask 0x0070
+#define sd_rise_time(x) (min((x), 7) << 4) /* bit 4 ~ 6 */
+#define RG_RXLPI_MSK_HFDUP 0x0008
+#define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
+
+/* OCP_EEE_CONFIG2 */
+#define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
+#define RG_DACQUIET_EN 0x0400
+#define RG_LDVQUIET_EN 0x0200
+#define RG_CKRSEL 0x0020
+#define RG_EEEPRG_EN 0x0010
+
+/* OCP_EEE_CONFIG3 */
+#define fast_snr_mask 0xff80
+#define fast_snr(x) (min((x), 0x1ff) << 7) /* bit 7 ~ 15 */
+#define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
+#define MSK_PH 0x0006 /* bit 0 ~ 3 */
+
+/* OCP_EEE_AR */
+/* bit[15:14] function */
+#define FUN_ADDR 0x0000
+#define FUN_DATA 0x4000
+/* bit[4:0] device addr */
+
+/* OCP_EEE_CFG */
+#define CTAP_SHORT_EN 0x0040
+#define EEE10_EN 0x0010
+
+/* OCP_DOWN_SPEED */
+#define EN_10M_BGOFF 0x0080
+
+/* OCP_PHY_STATE */
+#define TXDIS_STATE 0x01
+#define ABD_STATE 0x02
+
+/* OCP_ADC_CFG */
+#define CKADSEL_L 0x0100
+#define ADC_EN 0x0080
+#define EN_EMI_L 0x0040
+
+/* SRAM_LPF_CFG */
+#define LPF_AUTO_TUNE 0x8000
+
+/* SRAM_10M_AMP1 */
+#define GDAC_IB_UPALL 0x0008
+
+/* SRAM_10M_AMP2 */
+#define AMP_DN 0x0200
+
+/* SRAM_IMPEDANCE */
+#define RX_DRIVING_MASK 0x6000
+
+#define RTL8152_MAX_TX 4
+#define RTL8152_MAX_RX 10
+#define INTBUFSIZE 2
+#define CRC_SIZE 4
+#define TX_ALIGN 4
+#define RX_ALIGN 8
+
+#define INTR_LINK 0x0004
+
+#define RTL8152_REQT_READ 0xc0
+#define RTL8152_REQT_WRITE 0x40
+#define RTL8152_REQ_GET_REGS 0x05
+#define RTL8152_REQ_SET_REGS 0x05
+
+#define BYTE_EN_DWORD 0xff
+#define BYTE_EN_WORD 0x33
+#define BYTE_EN_BYTE 0x11
+#define BYTE_EN_SIX_BYTES 0x3f
+#define BYTE_EN_START_MASK 0x0f
+#define BYTE_EN_END_MASK 0xf0
+
+#define RTL8152_ETH_FRAME_LEN 1514
+#define RTL8152_AGG_BUF_SZ 2048
+
+#define RTL8152_RMS (RTL8152_ETH_FRAME_LEN + CRC_SIZE)
+#define RTL8153_RMS (RTL8152_ETH_FRAME_LEN + CRC_SIZE)
+#define RTL8152_TX_TIMEOUT (5 * HZ)
+
+#define MCU_TYPE_PLA 0x0100
+#define MCU_TYPE_USB 0x0000
+
+/* The forced speed, 10Mb, 100Mb, gigabit. */
+#define SPEED_10 10
+#define SPEED_100 100
+#define SPEED_1000 1000
+
+#define SPEED_UNKNOWN -1
+
+/* Duplex, half or full. */
+#define DUPLEX_HALF 0x00
+#define DUPLEX_FULL 0x01
+#define DUPLEX_UNKNOWN 0xff
+
+/* Enable or disable autonegotiation. */
+#define AUTONEG_DISABLE 0x00
+#define AUTONEG_ENABLE 0x01
+
+/* Generic MII registers. */
+#define MII_BMCR 0x00 /* Basic mode control register */
+#define MII_BMSR 0x01 /* Basic mode status register */
+#define MII_PHYSID1 0x02 /* PHYS ID 1 */
+#define MII_PHYSID2 0x03 /* PHYS ID 2 */
+#define MII_ADVERTISE 0x04 /* Advertisement control reg */
+#define MII_LPA 0x05 /* Link partner ability reg */
+#define MII_EXPANSION 0x06 /* Expansion register */
+#define MII_CTRL1000 0x09 /* 1000BASE-T control */
+#define MII_STAT1000 0x0a /* 1000BASE-T status */
+#define MII_MMD_CTRL 0x0d /* MMD Access Control Register */
+#define MII_MMD_DATA 0x0e /* MMD Access Data Register */
+#define MII_ESTATUS 0x0f /* Extended Status */
+#define MII_DCOUNTER 0x12 /* Disconnect counter */
+#define MII_FCSCOUNTER 0x13 /* False carrier counter */
+#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
+#define MII_RERRCOUNTER 0x15 /* Receive error counter */
+#define MII_SREVISION 0x16 /* Silicon revision */
+#define MII_RESV1 0x17 /* Reserved... */
+#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
+#define MII_PHYADDR 0x19 /* PHY address */
+#define MII_RESV2 0x1a /* Reserved... */
+#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
+#define MII_NCONFIG 0x1c /* Network interface config */
+
+#define TIMEOUT_RESOLUTION 50
+#define PHY_CONNECT_TIMEOUT 5000
+#define USB_BULK_SEND_TIMEOUT 5000
+#define USB_BULK_RECV_TIMEOUT 5000
+#define R8152_WAIT_TIMEOUT 2000
+
+struct rx_desc {
+ __le32 opts1;
+#define RD_CRC BIT(15)
+#define RX_LEN_MASK 0x7fff
+
+ __le32 opts2;
+#define RD_UDP_CS BIT(23)
+#define RD_TCP_CS BIT(22)
+#define RD_IPV6_CS BIT(20)
+#define RD_IPV4_CS BIT(19)
+
+ __le32 opts3;
+#define IPF BIT(23) /* IP checksum fail */
+#define UDPF BIT(22) /* UDP checksum fail */
+#define TCPF BIT(21) /* TCP checksum fail */
+#define RX_VLAN_TAG BIT(16)
+
+ __le32 opts4;
+ __le32 opts5;
+ __le32 opts6;
+};
+
+struct tx_desc {
+ __le32 opts1;
+#define TX_FS BIT(31) /* First segment of a packet */
+#define TX_LS BIT(30) /* Final segment of a packet */
+#define LGSEND BIT(29)
+#define GTSENDV4 BIT(28)
+#define GTSENDV6 BIT(27)
+#define GTTCPHO_SHIFT 18
+#define GTTCPHO_MAX 0x7fU
+#define TX_LEN_MAX 0x3ffffU
+
+ __le32 opts2;
+#define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
+#define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
+#define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
+#define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
+#define MSS_SHIFT 17
+#define MSS_MAX 0x7ffU
+#define TCPHO_SHIFT 17
+#define TCPHO_MAX 0x7ffU
+#define TX_VLAN_TAG BIT(16)
+};
+
+enum rtl_version {
+ RTL_VER_UNKNOWN = 0,
+ RTL_VER_01,
+ RTL_VER_02,
+ RTL_VER_03,
+ RTL_VER_04,
+ RTL_VER_05,
+ RTL_VER_06,
+ RTL_VER_07,
+ RTL_VER_MAX
+};
+
+enum rtl_register_content {
+ _1000bps = 0x10,
+ _100bps = 0x08,
+ _10bps = 0x04,
+ LINK_STATUS = 0x02,
+ FULL_DUP = 0x01,
+};
+
+struct r8152 {
+ struct usb_device *udev;
+ struct usb_interface *intf;
+ bool supports_gmii;
+
+ struct rtl_ops {
+ void (*init)(struct r8152 *);
+ int (*enable)(struct r8152 *);
+ void (*disable)(struct r8152 *);
+ void (*up)(struct r8152 *);
+ void (*down)(struct r8152 *);
+ void (*unload)(struct r8152 *);
+ } rtl_ops;
+
+ u32 coalesce;
+ u16 ocp_base;
+
+ u8 version;
+};
+
+int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
+ u16 size, void *data, u16 type);
+int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
+ void *data, u16 type);
+
+int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data);
+int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
+ u16 size, void *data);
+
+int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data);
+int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
+ u16 size, void *data);
+
+u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index);
+void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data);
+
+u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index);
+void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data);
+
+u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index);
+void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data);
+
+u16 ocp_reg_read(struct r8152 *tp, u16 addr);
+void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data);
+
+void sram_write(struct r8152 *tp, u16 addr, u16 data);
+
+int r8152_wait_for_bit(struct r8152 *tp, bool ocp_reg, u16 type, u16 index,
+ const u32 mask, bool set, unsigned int timeout);
+
+void r8152b_firmware(struct r8152 *tp);
+void r8153_firmware(struct r8152 *tp);
+#endif
diff --git a/drivers/usb/eth/r8152_fw.c b/drivers/usb/eth/r8152_fw.c
new file mode 100644
index 0000000..f820b16
--- /dev/null
+++ b/drivers/usb/eth/r8152_fw.c
@@ -0,0 +1,980 @@
+/*
+ * Copyright (c) 2015 Realtek Semiconductor Corp. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ */
+#include <common.h>
+#include <errno.h>
+#include "r8152.h"
+
+static u8 r8152b_pla_patch_a[] = {
+ 0x08, 0xe0, 0x40, 0xe0, 0x78, 0xe0, 0x85, 0xe0,
+ 0x5d, 0xe1, 0xa1, 0xe1, 0xa3, 0xe1, 0xab, 0xe1,
+ 0x31, 0xc3, 0x60, 0x72, 0xa0, 0x49, 0x10, 0xf0,
+ 0xa4, 0x49, 0x0e, 0xf0, 0x2c, 0xc3, 0x62, 0x72,
+ 0x26, 0x70, 0x80, 0x49, 0x05, 0xf0, 0x2f, 0x48,
+ 0x62, 0x9a, 0x24, 0x70, 0x60, 0x98, 0x24, 0xc3,
+ 0x60, 0x99, 0x23, 0xc3, 0x00, 0xbb, 0x2c, 0x75,
+ 0xdc, 0x21, 0xbc, 0x25, 0x04, 0x13, 0x0a, 0xf0,
+ 0x03, 0x13, 0x08, 0xf0, 0x02, 0x13, 0x06, 0xf0,
+ 0x01, 0x13, 0x04, 0xf0, 0x08, 0x13, 0x02, 0xf0,
+ 0x03, 0xe0, 0xd4, 0x49, 0x04, 0xf1, 0x14, 0xc2,
+ 0x12, 0xc3, 0x00, 0xbb, 0x12, 0xc3, 0x60, 0x75,
+ 0xd0, 0x49, 0x05, 0xf1, 0x50, 0x48, 0x60, 0x9d,
+ 0x09, 0xc6, 0x00, 0xbe, 0xd0, 0x48, 0x60, 0x9d,
+ 0xf3, 0xe7, 0xc2, 0xc0, 0x38, 0xd2, 0xc6, 0xd2,
+ 0x84, 0x17, 0xa2, 0x13, 0x0c, 0x17, 0xbc, 0xc0,
+ 0xa2, 0xd1, 0x33, 0xc5, 0xa0, 0x74, 0xc0, 0x49,
+ 0x1f, 0xf0, 0x30, 0xc5, 0xa0, 0x73, 0x00, 0x13,
+ 0x04, 0xf1, 0xa2, 0x73, 0x00, 0x13, 0x14, 0xf0,
+ 0x28, 0xc5, 0xa0, 0x74, 0xc8, 0x49, 0x1b, 0xf1,
+ 0x26, 0xc5, 0xa0, 0x76, 0xa2, 0x74, 0x01, 0x06,
+ 0x20, 0x37, 0xa0, 0x9e, 0xa2, 0x9c, 0x1e, 0xc5,
+ 0xa2, 0x73, 0x23, 0x40, 0x10, 0xf8, 0x04, 0xf3,
+ 0xa0, 0x73, 0x33, 0x40, 0x0c, 0xf8, 0x15, 0xc5,
+ 0xa0, 0x74, 0x41, 0x48, 0xa0, 0x9c, 0x14, 0xc5,
+ 0xa0, 0x76, 0x62, 0x48, 0xe0, 0x48, 0xa0, 0x9e,
+ 0x10, 0xc6, 0x00, 0xbe, 0x0a, 0xc5, 0xa0, 0x74,
+ 0x48, 0x48, 0xa0, 0x9c, 0x0b, 0xc5, 0x20, 0x1e,
+ 0xa0, 0x9e, 0xe5, 0x48, 0xa0, 0x9e, 0xf0, 0xe7,
+ 0xbc, 0xc0, 0xc8, 0xd2, 0xcc, 0xd2, 0x28, 0xe4,
+ 0x22, 0x02, 0xf0, 0xc0, 0x0b, 0xc0, 0x00, 0x71,
+ 0x0a, 0xc0, 0x00, 0x72, 0xa0, 0x49, 0x04, 0xf0,
+ 0xa4, 0x49, 0x02, 0xf0, 0x93, 0x48, 0x04, 0xc0,
+ 0x00, 0xb8, 0x00, 0xe4, 0xc2, 0xc0, 0x8c, 0x09,
+ 0x14, 0xc2, 0x40, 0x73, 0xba, 0x48, 0x40, 0x9b,
+ 0x11, 0xc2, 0x40, 0x73, 0xb0, 0x49, 0x17, 0xf0,
+ 0xbf, 0x49, 0x03, 0xf1, 0x09, 0xc5, 0x00, 0xbd,
+ 0xb1, 0x49, 0x11, 0xf0, 0xb1, 0x48, 0x40, 0x9b,
+ 0x02, 0xc2, 0x00, 0xba, 0x82, 0x18, 0x00, 0xa0,
+ 0x1e, 0xfc, 0xbc, 0xc0, 0xf0, 0xc0, 0xde, 0xe8,
+ 0x00, 0x80, 0x00, 0x60, 0x2c, 0x75, 0xd4, 0x49,
+ 0x12, 0xf1, 0x29, 0xe0, 0xf8, 0xc2, 0x46, 0x71,
+ 0xf7, 0xc2, 0x40, 0x73, 0xbe, 0x49, 0x03, 0xf1,
+ 0xf5, 0xc7, 0x02, 0xe0, 0xf2, 0xc7, 0x4f, 0x30,
+ 0x26, 0x62, 0xa1, 0x49, 0xf0, 0xf1, 0x22, 0x72,
+ 0xa0, 0x49, 0xed, 0xf1, 0x25, 0x25, 0x18, 0x1f,
+ 0x97, 0x30, 0x91, 0x30, 0x36, 0x9a, 0x2c, 0x75,
+ 0x32, 0xc3, 0x60, 0x73, 0xb1, 0x49, 0x0d, 0xf1,
+ 0xdc, 0x21, 0xbc, 0x25, 0x27, 0xc6, 0xc0, 0x77,
+ 0x04, 0x13, 0x18, 0xf0, 0x03, 0x13, 0x19, 0xf0,
+ 0x02, 0x13, 0x1a, 0xf0, 0x01, 0x13, 0x1b, 0xf0,
+ 0xd4, 0x49, 0x03, 0xf1, 0x1c, 0xc5, 0x00, 0xbd,
+ 0xcd, 0xc6, 0xc6, 0x67, 0x2e, 0x75, 0xd7, 0x22,
+ 0xdd, 0x26, 0x05, 0x15, 0x1a, 0xf0, 0x14, 0xc6,
+ 0x00, 0xbe, 0x13, 0xc5, 0x00, 0xbd, 0x12, 0xc5,
+ 0x00, 0xbd, 0xf1, 0x49, 0xfb, 0xf1, 0xef, 0xe7,
+ 0xf4, 0x49, 0xfa, 0xf1, 0xec, 0xe7, 0xf3, 0x49,
+ 0xf7, 0xf1, 0xe9, 0xe7, 0xf2, 0x49, 0xf4, 0xf1,
+ 0xe6, 0xe7, 0xb6, 0xc0, 0x6a, 0x14, 0xac, 0x13,
+ 0xd6, 0x13, 0xfa, 0x14, 0xa0, 0xd1, 0x00, 0x00,
+ 0xc0, 0x75, 0xd0, 0x49, 0x46, 0xf0, 0x26, 0x72,
+ 0xa7, 0x49, 0x43, 0xf0, 0x22, 0x72, 0x25, 0x25,
+ 0x20, 0x1f, 0x97, 0x30, 0x91, 0x30, 0x40, 0x73,
+ 0xf3, 0xc4, 0x1c, 0x40, 0x04, 0xf0, 0xd7, 0x49,
+ 0x05, 0xf1, 0x37, 0xe0, 0x53, 0x48, 0xc0, 0x9d,
+ 0x08, 0x02, 0x40, 0x66, 0x64, 0x27, 0x06, 0x16,
+ 0x30, 0xf1, 0x46, 0x63, 0x3b, 0x13, 0x2d, 0xf1,
+ 0x34, 0x9b, 0x18, 0x1b, 0x93, 0x30, 0x2b, 0xc3,
+ 0x10, 0x1c, 0x2b, 0xe8, 0x01, 0x14, 0x25, 0xf1,
+ 0x00, 0x1d, 0x26, 0x1a, 0x8a, 0x30, 0x22, 0x73,
+ 0xb5, 0x25, 0x0e, 0x0b, 0x00, 0x1c, 0x2c, 0xe8,
+ 0x1f, 0xc7, 0x27, 0x40, 0x1a, 0xf1, 0x38, 0xe8,
+ 0x32, 0x1f, 0x8f, 0x30, 0x08, 0x1b, 0x24, 0xe8,
+ 0x36, 0x72, 0x46, 0x77, 0x00, 0x17, 0x0d, 0xf0,
+ 0x13, 0xc3, 0x1f, 0x40, 0x03, 0xf1, 0x00, 0x1f,
+ 0x46, 0x9f, 0x44, 0x77, 0x9f, 0x44, 0x5f, 0x44,
+ 0x17, 0xe8, 0x0a, 0xc7, 0x27, 0x40, 0x05, 0xf1,
+ 0x02, 0xc3, 0x00, 0xbb, 0x50, 0x1a, 0x06, 0x1a,
+ 0xff, 0xc7, 0x00, 0xbf, 0xb8, 0xcd, 0xff, 0xff,
+ 0x02, 0x0c, 0x54, 0xa5, 0xdc, 0xa5, 0x2f, 0x40,
+ 0x05, 0xf1, 0x00, 0x14, 0xfa, 0xf1, 0x01, 0x1c,
+ 0x02, 0xe0, 0x00, 0x1c, 0x80, 0xff, 0xb0, 0x49,
+ 0x04, 0xf0, 0x01, 0x0b, 0xd3, 0xa1, 0x03, 0xe0,
+ 0x02, 0x0b, 0xd3, 0xa5, 0x27, 0x31, 0x20, 0x37,
+ 0x02, 0x0b, 0xd3, 0xa5, 0x27, 0x31, 0x20, 0x37,
+ 0x00, 0x13, 0xfb, 0xf1, 0x80, 0xff, 0x22, 0x73,
+ 0xb5, 0x25, 0x18, 0x1e, 0xde, 0x30, 0xd9, 0x30,
+ 0x64, 0x72, 0x11, 0x1e, 0x68, 0x23, 0x16, 0x31,
+ 0x80, 0xff, 0xd4, 0x49, 0x28, 0xf0, 0x02, 0xb4,
+ 0x2a, 0xc4, 0x00, 0x1d, 0x2e, 0xe8, 0xe0, 0x73,
+ 0xb9, 0x21, 0xbd, 0x25, 0x04, 0x13, 0x02, 0xf0,
+ 0x1a, 0xe0, 0x22, 0xc4, 0x23, 0xc3, 0x2f, 0xe8,
+ 0x23, 0xc3, 0x2d, 0xe8, 0x00, 0x1d, 0x21, 0xe8,
+ 0xe2, 0x73, 0xbb, 0x49, 0xfc, 0xf0, 0xe0, 0x73,
+ 0xb7, 0x48, 0x03, 0xb4, 0x81, 0x1d, 0x19, 0xe8,
+ 0x40, 0x1a, 0x84, 0x1d, 0x16, 0xe8, 0x12, 0xc3,
+ 0x1e, 0xe8, 0x03, 0xb0, 0x81, 0x1d, 0x11, 0xe8,
+ 0x0e, 0xc3, 0x19, 0xe8, 0x02, 0xb0, 0x06, 0xc7,
+ 0x04, 0x1e, 0xe0, 0x9e, 0x02, 0xc6, 0x00, 0xbe,
+ 0x22, 0x02, 0x20, 0xe4, 0x04, 0xb8, 0x34, 0xb0,
+ 0x00, 0x02, 0x00, 0x03, 0x00, 0x0e, 0x00, 0x0c,
+ 0x09, 0xc7, 0xe0, 0x9b, 0xe2, 0x9a, 0xe4, 0x9c,
+ 0xe6, 0x8d, 0xe6, 0x76, 0xef, 0x49, 0xfe, 0xf1,
+ 0x80, 0xff, 0x08, 0xea, 0x82, 0x1d, 0xf5, 0xef,
+ 0x00, 0x1a, 0x88, 0x1d, 0xf2, 0xef, 0xed, 0xc2,
+ 0xf0, 0xef, 0x80, 0xff, 0x02, 0xc6, 0x00, 0xbe,
+ 0x46, 0x06, 0x08, 0xc2, 0x40, 0x73, 0x3a, 0x48,
+ 0x40, 0x9b, 0x06, 0xff, 0x02, 0xc6, 0x00, 0xbe,
+ 0x86, 0x17, 0x1e, 0xfc, 0x36, 0xf0, 0x08, 0x1c,
+ 0xea, 0x8c, 0xe3, 0x64, 0xc7, 0x49, 0x25, 0xf1,
+ 0xe0, 0x75, 0xff, 0x1b, 0xeb, 0x47, 0xff, 0x1b,
+ 0x6b, 0x47, 0xe0, 0x9d, 0x15, 0xc3, 0x60, 0x75,
+ 0xd8, 0x49, 0x04, 0xf0, 0x81, 0x1d, 0xe2, 0x8d,
+ 0x05, 0xe0, 0xe2, 0x63, 0x81, 0x1d, 0xdd, 0x47,
+ 0xe2, 0x8b, 0x0b, 0xc3, 0x00, 0x1d, 0x61, 0x8d,
+ 0x3c, 0x03, 0x60, 0x75, 0xd8, 0x49, 0x06, 0xf1,
+ 0xdf, 0x48, 0x61, 0x95, 0x16, 0xe0, 0x4e, 0xe8,
+ 0x12, 0xe8, 0x21, 0xc5, 0xa0, 0x73, 0xb0, 0x49,
+ 0x03, 0xf0, 0x31, 0x48, 0xa0, 0x9b, 0x0d, 0xe0,
+ 0xc0, 0x49, 0x0b, 0xf1, 0xe2, 0x63, 0x7e, 0x1d,
+ 0xdd, 0x46, 0xe2, 0x8b, 0xe0, 0x75, 0x83, 0x1b,
+ 0xeb, 0x46, 0xfe, 0x1b, 0x6b, 0x46, 0xe0, 0x9d,
+ 0xe4, 0x49, 0x11, 0xf0, 0x10, 0x1d, 0xea, 0x8d,
+ 0xe3, 0x64, 0xc6, 0x49, 0x09, 0xf1, 0x07, 0xc5,
+ 0xa0, 0x73, 0xb1, 0x48, 0xa0, 0x9b, 0x02, 0xc5,
+ 0x00, 0xbd, 0xe6, 0x04, 0xa0, 0xd1, 0x02, 0xc5,
+ 0x00, 0xbd, 0xfe, 0x04, 0x02, 0xc5, 0x00, 0xbd,
+ 0x30, 0x05, 0x00, 0x00 };
+
+static u16 r8152b_ram_code1[] = {
+ 0x9700, 0x7fe0, 0x4c00, 0x4007, 0x4400, 0x4800, 0x7c1f, 0x4c00,
+ 0x5310, 0x6000, 0x7c07, 0x6800, 0x673e, 0x0000, 0x0000, 0x571f,
+ 0x5ffb, 0xaa05, 0x5b58, 0x7d80, 0x6100, 0x3019, 0x5b64, 0x7d80,
+ 0x6080, 0xa6f8, 0xdcdb, 0x0015, 0xb915, 0xb511, 0xd16b, 0x000f,
+ 0xb40f, 0xd06b, 0x000d, 0xb206, 0x7c01, 0x5800, 0x7c04, 0x5c00,
+ 0x3011, 0x7c01, 0x5801, 0x7c04, 0x5c04, 0x3019, 0x30a5, 0x3127,
+ 0x31d5, 0x7fe0, 0x4c60, 0x7c07, 0x6803, 0x7d00, 0x6900, 0x65a0,
+ 0x0000, 0x0000, 0xaf03, 0x6015, 0x303e, 0x6017, 0x57e0, 0x580c,
+ 0x588c, 0x7fdd, 0x5fa2, 0x4827, 0x7c1f, 0x4c00, 0x7c1f, 0x4c10,
+ 0x8400, 0x7c30, 0x6020, 0x48bf, 0x7c1f, 0x4c00, 0x7c1f, 0x4c01,
+ 0x7c07, 0x6803, 0xb806, 0x7c08, 0x6800, 0x0000, 0x0000, 0x305c,
+ 0x7c08, 0x6808, 0x0000, 0x0000, 0xae06, 0x7c02, 0x5c02, 0x0000,
+ 0x0000, 0x3067, 0x8e05, 0x7c02, 0x5c00, 0x0000, 0x0000, 0xad06,
+ 0x7c20, 0x5c20, 0x0000, 0x0000, 0x3072, 0x8d05, 0x7c20, 0x5c00,
+ 0x0000, 0x0000, 0xa008, 0x7c07, 0x6800, 0xb8db, 0x7c07, 0x6803,
+ 0xd9b3, 0x00d7, 0x7fe0, 0x4c80, 0x7c08, 0x6800, 0x0000, 0x0000,
+ 0x7c23, 0x5c23, 0x481d, 0x7c1f, 0x4c00, 0x7c1f, 0x4c02, 0x5310,
+ 0x81ff, 0x30f5, 0x7fe0, 0x4d00, 0x4832, 0x7c1f, 0x4c00, 0x7c1f,
+ 0x4c10, 0x7c08, 0x6000, 0xa49e, 0x7c07, 0x6800, 0xb89b, 0x7c07,
+ 0x6803, 0xd9b3, 0x00f9, 0x7fe0, 0x4d20, 0x7e00, 0x6200, 0x3001,
+ 0x7fe0, 0x4dc0, 0xd09d, 0x0002, 0xb4fe, 0x7fe0, 0x4d80, 0x7c04,
+ 0x6004, 0x7c07, 0x6802, 0x6728, 0x0000, 0x0000, 0x7c08, 0x6000,
+ 0x486c, 0x7c1f, 0x4c00, 0x7c1f, 0x4c01, 0x9503, 0x7e00, 0x6200,
+ 0x571f, 0x5fbb, 0xaa05, 0x5b58, 0x7d80, 0x6100, 0x30c2, 0x5b64,
+ 0x7d80, 0x6080, 0xcdab, 0x0063, 0xcd8d, 0x0061, 0xd96b, 0x005f,
+ 0xd0a0, 0x00d7, 0xcba0, 0x0003, 0x80ec, 0x30cf, 0x30dc, 0x7fe0,
+ 0x4ce0, 0x4832, 0x7c1f, 0x4c00, 0x7c1f, 0x4c08, 0x7c08, 0x6008,
+ 0x8300, 0xb902, 0x30a5, 0x308a, 0x7fe0, 0x4da0, 0x65a8, 0x0000,
+ 0x0000, 0x56a0, 0x590c, 0x7ffd, 0x5fa2, 0xae06, 0x7c02, 0x5c02,
+ 0x0000, 0x0000, 0x30f0, 0x8e05, 0x7c02, 0x5c00, 0x0000, 0x0000,
+ 0xcba4, 0x0004, 0xcd8d, 0x0002, 0x80f1, 0x7fe0, 0x4ca0, 0x7c08,
+ 0x6408, 0x0000, 0x0000, 0x7d00, 0x6800, 0xb603, 0x7c10, 0x6010,
+ 0x7d1f, 0x551f, 0x5fb3, 0xaa07, 0x7c80, 0x5800, 0x5b58, 0x7d80,
+ 0x6100, 0x310f, 0x7c80, 0x5800, 0x5b64, 0x7d80, 0x6080, 0x4827,
+ 0x7c1f, 0x4c00, 0x7c1f, 0x4c10, 0x8400, 0x7c10, 0x6000, 0x7fe0,
+ 0x4cc0, 0x5fbb, 0x4824, 0x7c1f, 0x4c00, 0x7c1f, 0x4c04, 0x8200,
+ 0x7ce0, 0x5400, 0x6728, 0x0000, 0x0000, 0x30cf, 0x3001, 0x7fe0,
+ 0x4e00, 0x4007, 0x4400, 0x5310, 0x7c07, 0x6800, 0x673e, 0x0000,
+ 0x0000, 0x570f, 0x5fff, 0xaa05, 0x585b, 0x7d80, 0x6100, 0x313b,
+ 0x5867, 0x7d80, 0x6080, 0x9403, 0x7e00, 0x6200, 0xcda3, 0x00e7,
+ 0xcd85, 0x00e5, 0xd96b, 0x00e3, 0x96e3, 0x7c07, 0x6800, 0x673e,
+ 0x0000, 0x0000, 0x7fe0, 0x4e20, 0x96db, 0x8b04, 0x7c08, 0x5008,
+ 0xab03, 0x7c08, 0x5000, 0x7c07, 0x6801, 0x677e, 0x0000, 0x0000,
+ 0xdb7c, 0x00ec, 0x0000, 0x7fe1, 0x4f40, 0x4837, 0x4418, 0x41c7,
+ 0x7fe0, 0x4e40, 0x7c40, 0x5400, 0x7c1f, 0x4c01, 0x7c1f, 0x4c01,
+ 0x8fbf, 0xd2a0, 0x004b, 0x9204, 0xa042, 0x3168, 0x3127, 0x7fe1,
+ 0x4f60, 0x489c, 0x4628, 0x7fe0, 0x4e60, 0x7e28, 0x4628, 0x7c40,
+ 0x5400, 0x7c01, 0x5800, 0x7c04, 0x5c00, 0x41e8, 0x7c1f, 0x4c01,
+ 0x7c1f, 0x4c01, 0x8fa5, 0xb241, 0xa02a, 0x3182, 0x7fe0, 0x4ea0,
+ 0x7c02, 0x4402, 0x4448, 0x4894, 0x7c1f, 0x4c01, 0x7c1f, 0x4c03,
+ 0x4824, 0x7c1f, 0x4c07, 0x41ef, 0x41ff, 0x4891, 0x7c1f, 0x4c07,
+ 0x7c1f, 0x4c17, 0x8400, 0x8ef8, 0x41c7, 0x8f8a, 0x92d5, 0xa10f,
+ 0xd480, 0x0008, 0xd580, 0x00b8, 0xa202, 0x319d, 0x7c04, 0x4404,
+ 0x319d, 0xd484, 0x00f3, 0xd484, 0x00f1, 0x3127, 0x7fe0, 0x4ee0,
+ 0x7c40, 0x5400, 0x4488, 0x41cf, 0x3127, 0x7fe0, 0x4ec0, 0x48f3,
+ 0x7c1f, 0x4c01, 0x7c1f, 0x4c09, 0x4508, 0x41c7, 0x8fb0, 0xd218,
+ 0x00ae, 0xd2a4, 0x009e, 0x31be, 0x7fe0, 0x4e80, 0x4832, 0x7c1f,
+ 0x4c01, 0x7c1f, 0x4c11, 0x4428, 0x7c40, 0x5440, 0x7c01, 0x5801,
+ 0x7c04, 0x5c04, 0x41e8, 0xa4b3, 0x31d3, 0x7fe0, 0x4f20, 0x7c07,
+ 0x6800, 0x673e, 0x0000, 0x0000, 0x570f, 0x5fff, 0xaa04, 0x585b,
+ 0x6100, 0x31e4, 0x5867, 0x6080, 0xbcf1, 0x3001 };
+
+static u16 r8152b_pla_patch_a_bp[] = {
+ 0xfc26, 0x8000, 0xfc28, 0x170b, 0xfc2a, 0x01e1, 0xfc2c, 0x0989,
+ 0xfc2e, 0x1349, 0xfc30, 0x01b7, 0xfc32, 0x061d, 0xe422, 0x0020,
+ 0xe420, 0x0018, 0xfc34, 0x1785, 0xfc36, 0x047b };
+
+static u8 r8152b_pla_patch_a2[] = {
+ 0x08, 0xe0, 0x1a, 0xe0, 0xf2, 0xe0, 0xfa, 0xe0,
+ 0x32, 0xe1, 0x34, 0xe1, 0x36, 0xe1, 0x38, 0xe1,
+ 0x2c, 0x75, 0xdc, 0x21, 0xbc, 0x25, 0x04, 0x13,
+ 0x0b, 0xf0, 0x03, 0x13, 0x09, 0xf0, 0x02, 0x13,
+ 0x07, 0xf0, 0x01, 0x13, 0x05, 0xf0, 0x08, 0x13,
+ 0x03, 0xf0, 0x04, 0xc3, 0x00, 0xbb, 0x03, 0xc3,
+ 0x00, 0xbb, 0xd2, 0x17, 0xbc, 0x17, 0x14, 0xc2,
+ 0x40, 0x73, 0xba, 0x48, 0x40, 0x9b, 0x11, 0xc2,
+ 0x40, 0x73, 0xb0, 0x49, 0x17, 0xf0, 0xbf, 0x49,
+ 0x03, 0xf1, 0x09, 0xc5, 0x00, 0xbd, 0xb1, 0x49,
+ 0x11, 0xf0, 0xb1, 0x48, 0x40, 0x9b, 0x02, 0xc2,
+ 0x00, 0xba, 0x4e, 0x19, 0x00, 0xa0, 0x1e, 0xfc,
+ 0xbc, 0xc0, 0xf0, 0xc0, 0xde, 0xe8, 0x00, 0x80,
+ 0x00, 0x60, 0x2c, 0x75, 0xd4, 0x49, 0x12, 0xf1,
+ 0x29, 0xe0, 0xf8, 0xc2, 0x46, 0x71, 0xf7, 0xc2,
+ 0x40, 0x73, 0xbe, 0x49, 0x03, 0xf1, 0xf5, 0xc7,
+ 0x02, 0xe0, 0xf2, 0xc7, 0x4f, 0x30, 0x26, 0x62,
+ 0xa1, 0x49, 0xf0, 0xf1, 0x22, 0x72, 0xa0, 0x49,
+ 0xed, 0xf1, 0x25, 0x25, 0x18, 0x1f, 0x97, 0x30,
+ 0x91, 0x30, 0x36, 0x9a, 0x2c, 0x75, 0x32, 0xc3,
+ 0x60, 0x73, 0xb1, 0x49, 0x0d, 0xf1, 0xdc, 0x21,
+ 0xbc, 0x25, 0x27, 0xc6, 0xc0, 0x77, 0x04, 0x13,
+ 0x18, 0xf0, 0x03, 0x13, 0x19, 0xf0, 0x02, 0x13,
+ 0x1a, 0xf0, 0x01, 0x13, 0x1b, 0xf0, 0xd4, 0x49,
+ 0x03, 0xf1, 0x1c, 0xc5, 0x00, 0xbd, 0xcd, 0xc6,
+ 0xc6, 0x67, 0x2e, 0x75, 0xd7, 0x22, 0xdd, 0x26,
+ 0x05, 0x15, 0x1a, 0xf0, 0x14, 0xc6, 0x00, 0xbe,
+ 0x13, 0xc5, 0x00, 0xbd, 0x12, 0xc5, 0x00, 0xbd,
+ 0xf1, 0x49, 0xfb, 0xf1, 0xef, 0xe7, 0xf4, 0x49,
+ 0xfa, 0xf1, 0xec, 0xe7, 0xf3, 0x49, 0xf7, 0xf1,
+ 0xe9, 0xe7, 0xf2, 0x49, 0xf4, 0xf1, 0xe6, 0xe7,
+ 0xb6, 0xc0, 0xf6, 0x14, 0x36, 0x14, 0x62, 0x14,
+ 0x86, 0x15, 0xa0, 0xd1, 0x00, 0x00, 0xc0, 0x75,
+ 0xd0, 0x49, 0x46, 0xf0, 0x26, 0x72, 0xa7, 0x49,
+ 0x43, 0xf0, 0x22, 0x72, 0x25, 0x25, 0x20, 0x1f,
+ 0x97, 0x30, 0x91, 0x30, 0x40, 0x73, 0xf3, 0xc4,
+ 0x1c, 0x40, 0x04, 0xf0, 0xd7, 0x49, 0x05, 0xf1,
+ 0x37, 0xe0, 0x53, 0x48, 0xc0, 0x9d, 0x08, 0x02,
+ 0x40, 0x66, 0x64, 0x27, 0x06, 0x16, 0x30, 0xf1,
+ 0x46, 0x63, 0x3b, 0x13, 0x2d, 0xf1, 0x34, 0x9b,
+ 0x18, 0x1b, 0x93, 0x30, 0x2b, 0xc3, 0x10, 0x1c,
+ 0x2b, 0xe8, 0x01, 0x14, 0x25, 0xf1, 0x00, 0x1d,
+ 0x26, 0x1a, 0x8a, 0x30, 0x22, 0x73, 0xb5, 0x25,
+ 0x0e, 0x0b, 0x00, 0x1c, 0x2c, 0xe8, 0x1f, 0xc7,
+ 0x27, 0x40, 0x1a, 0xf1, 0x38, 0xe8, 0x32, 0x1f,
+ 0x8f, 0x30, 0x08, 0x1b, 0x24, 0xe8, 0x36, 0x72,
+ 0x46, 0x77, 0x00, 0x17, 0x0d, 0xf0, 0x13, 0xc3,
+ 0x1f, 0x40, 0x03, 0xf1, 0x00, 0x1f, 0x46, 0x9f,
+ 0x44, 0x77, 0x9f, 0x44, 0x5f, 0x44, 0x17, 0xe8,
+ 0x0a, 0xc7, 0x27, 0x40, 0x05, 0xf1, 0x02, 0xc3,
+ 0x00, 0xbb, 0x1c, 0x1b, 0xd2, 0x1a, 0xff, 0xc7,
+ 0x00, 0xbf, 0xb8, 0xcd, 0xff, 0xff, 0x02, 0x0c,
+ 0x54, 0xa5, 0xdc, 0xa5, 0x2f, 0x40, 0x05, 0xf1,
+ 0x00, 0x14, 0xfa, 0xf1, 0x01, 0x1c, 0x02, 0xe0,
+ 0x00, 0x1c, 0x80, 0xff, 0xb0, 0x49, 0x04, 0xf0,
+ 0x01, 0x0b, 0xd3, 0xa1, 0x03, 0xe0, 0x02, 0x0b,
+ 0xd3, 0xa5, 0x27, 0x31, 0x20, 0x37, 0x02, 0x0b,
+ 0xd3, 0xa5, 0x27, 0x31, 0x20, 0x37, 0x00, 0x13,
+ 0xfb, 0xf1, 0x80, 0xff, 0x22, 0x73, 0xb5, 0x25,
+ 0x18, 0x1e, 0xde, 0x30, 0xd9, 0x30, 0x64, 0x72,
+ 0x11, 0x1e, 0x68, 0x23, 0x16, 0x31, 0x80, 0xff,
+ 0x08, 0xc2, 0x40, 0x73, 0x3a, 0x48, 0x40, 0x9b,
+ 0x06, 0xff, 0x02, 0xc6, 0x00, 0xbe, 0x4e, 0x18,
+ 0x1e, 0xfc, 0x33, 0xc5, 0xa0, 0x74, 0xc0, 0x49,
+ 0x1f, 0xf0, 0x30, 0xc5, 0xa0, 0x73, 0x00, 0x13,
+ 0x04, 0xf1, 0xa2, 0x73, 0x00, 0x13, 0x14, 0xf0,
+ 0x28, 0xc5, 0xa0, 0x74, 0xc8, 0x49, 0x1b, 0xf1,
+ 0x26, 0xc5, 0xa0, 0x76, 0xa2, 0x74, 0x01, 0x06,
+ 0x20, 0x37, 0xa0, 0x9e, 0xa2, 0x9c, 0x1e, 0xc5,
+ 0xa2, 0x73, 0x23, 0x40, 0x10, 0xf8, 0x04, 0xf3,
+ 0xa0, 0x73, 0x33, 0x40, 0x0c, 0xf8, 0x15, 0xc5,
+ 0xa0, 0x74, 0x41, 0x48, 0xa0, 0x9c, 0x14, 0xc5,
+ 0xa0, 0x76, 0x62, 0x48, 0xe0, 0x48, 0xa0, 0x9e,
+ 0x10, 0xc6, 0x00, 0xbe, 0x0a, 0xc5, 0xa0, 0x74,
+ 0x48, 0x48, 0xa0, 0x9c, 0x0b, 0xc5, 0x20, 0x1e,
+ 0xa0, 0x9e, 0xe5, 0x48, 0xa0, 0x9e, 0xf0, 0xe7,
+ 0xbc, 0xc0, 0xc8, 0xd2, 0xcc, 0xd2, 0x28, 0xe4,
+ 0x22, 0x02, 0xf0, 0xc0, 0x02, 0xc6, 0x00, 0xbe,
+ 0x00, 0x00, 0x02, 0xc6, 0x00, 0xbe, 0x00, 0x00,
+ 0x02, 0xc6, 0x00, 0xbe, 0x00, 0x00, 0x02, 0xc6,
+ 0x00, 0xbe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+
+static u16 r8152b_pla_patch_a2_bp[] = {
+ 0xfc28, 0x8000, 0xfc28, 0x17a5, 0xfc2a, 0x13ad,
+ 0xfc2c, 0x184d, 0xfc2e, 0x01e1 };
+
+static u16 r8153_ram_code_a[] = {
+ 0xE86C, 0xA000, 0xB436, 0xB820, 0xB438, 0x0290, 0xB436, 0xA012,
+ 0xB438, 0x0000, 0xB436, 0xA014, 0xB438, 0x2c04, 0xB438, 0x2c18,
+ 0xB438, 0x2c45, 0xB438, 0x2c45, 0xB438, 0xd502, 0xB438, 0x8301,
+ 0xB438, 0x8306, 0xB438, 0xd500, 0xB438, 0x8208, 0xB438, 0xd501,
+ 0xB438, 0xe018, 0xB438, 0x0308, 0xB438, 0x60f2, 0xB438, 0x8404,
+ 0xB438, 0x607d, 0xB438, 0xc117, 0xB438, 0x2c16, 0xB438, 0xc116,
+ 0xB438, 0x2c16, 0xB438, 0x607d, 0xB438, 0xc117, 0xB438, 0xa404,
+ 0xB438, 0xd500, 0xB438, 0x0800, 0xB438, 0xd501, 0xB438, 0x62d2,
+ 0xB438, 0x615d, 0xB438, 0xc115, 0xB438, 0xa404, 0xB438, 0xc307,
+ 0xB438, 0xd502, 0xB438, 0x8301, 0xB438, 0x8306, 0xB438, 0xd500,
+ 0xB438, 0x8208, 0xB438, 0x2c42, 0xB438, 0xc114, 0xB438, 0x8404,
+ 0xB438, 0xc317, 0xB438, 0xd701, 0xB438, 0x435d, 0xB438, 0xd500,
+ 0xB438, 0xa208, 0xB438, 0xd502, 0xB438, 0xa306, 0xB438, 0xa301,
+ 0xB438, 0x2c42, 0xB438, 0x8404, 0xB438, 0x613d, 0xB438, 0xc115,
+ 0xB438, 0xc307, 0xB438, 0xd502, 0xB438, 0x8301, 0xB438, 0x8306,
+ 0xB438, 0xd500, 0xB438, 0x8208, 0xB438, 0x2c42, 0xB438, 0xc114,
+ 0xB438, 0xc317, 0xB438, 0xd701, 0xB438, 0x40dd, 0xB438, 0xd500,
+ 0xB438, 0xa208, 0xB438, 0xd502, 0xB438, 0xa306, 0xB438, 0xa301,
+ 0xB438, 0xd500, 0xB438, 0xd702, 0xB438, 0x0800, 0xB436, 0xA01A,
+ 0xB438, 0x0000, 0xB436, 0xA006, 0xB438, 0x0fff, 0xB436, 0xA004,
+ 0xB438, 0x0fff, 0xB436, 0xA002, 0xB438, 0x05a3, 0xB436, 0xA000,
+ 0xB438, 0x3591, 0xB436, 0xB820, 0xB438, 0x0210 };
+
+static u8 r8153_usb_patch_c[] = {
+ 0x08, 0xe0, 0x0a, 0xe0, 0x14, 0xe0, 0x2e, 0xe0,
+ 0x37, 0xe0, 0x3e, 0xe0, 0x6d, 0xe0, 0x78, 0xe0,
+ 0x02, 0xc5, 0x00, 0xbd, 0x38, 0x3b, 0xdb, 0x49,
+ 0x04, 0xf1, 0x06, 0xc3, 0x00, 0xbb, 0x5a, 0x02,
+ 0x05, 0xc4, 0x03, 0xc3, 0x00, 0xbb, 0xa4, 0x04,
+ 0x7e, 0x02, 0x30, 0xd4, 0x30, 0x18, 0x18, 0xc1,
+ 0x0c, 0xe8, 0x17, 0xc6, 0xc7, 0x65, 0xd0, 0x49,
+ 0x05, 0xf0, 0x32, 0x48, 0x02, 0xc2, 0x00, 0xba,
+ 0x3e, 0x16, 0x02, 0xc2, 0x00, 0xba, 0x48, 0x16,
+ 0x02, 0xb4, 0x09, 0xc2, 0x40, 0x99, 0x0e, 0x48,
+ 0x42, 0x98, 0x42, 0x70, 0x8e, 0x49, 0xfe, 0xf1,
+ 0x02, 0xb0, 0x80, 0xff, 0xc0, 0xd4, 0xe4, 0x40,
+ 0x20, 0xd4, 0xb0, 0x49, 0x04, 0xf0, 0x30, 0x18,
+ 0x06, 0xc1, 0xef, 0xef, 0xfa, 0xc7, 0x02, 0xc0,
+ 0x00, 0xb8, 0xd0, 0x10, 0xe4, 0x4b, 0x07, 0xc3,
+ 0x70, 0x61, 0x12, 0x48, 0x70, 0x89, 0x02, 0xc3,
+ 0x00, 0xbb, 0x9c, 0x15, 0x20, 0xd4, 0x2b, 0xc5,
+ 0xa0, 0x77, 0x00, 0x1c, 0xa0, 0x9c, 0x28, 0xc5,
+ 0xa0, 0x64, 0xc0, 0x48, 0xc1, 0x48, 0xc2, 0x48,
+ 0xa0, 0x8c, 0xb1, 0x64, 0xc0, 0x48, 0xb1, 0x8c,
+ 0x20, 0xc5, 0xa0, 0x64, 0x40, 0x48, 0x41, 0x48,
+ 0xc2, 0x48, 0xa0, 0x8c, 0x19, 0xc5, 0xa4, 0x64,
+ 0x44, 0x48, 0xa4, 0x8c, 0xb1, 0x64, 0x40, 0x48,
+ 0xb1, 0x8c, 0x14, 0xc4, 0x80, 0x73, 0x13, 0xc4,
+ 0x82, 0x9b, 0x11, 0x1b, 0x80, 0x9b, 0x0c, 0xc5,
+ 0xa0, 0x64, 0x40, 0x48, 0x41, 0x48, 0x42, 0x48,
+ 0xa0, 0x8c, 0x05, 0xc5, 0xa0, 0x9f, 0x02, 0xc5,
+ 0x00, 0xbd, 0x6c, 0x3a, 0x1e, 0xfc, 0x10, 0xd8,
+ 0x86, 0xd4, 0xf8, 0xcb, 0x20, 0xe4, 0x0a, 0xc0,
+ 0x16, 0x61, 0x91, 0x48, 0x16, 0x89, 0x07, 0xc0,
+ 0x11, 0x19, 0x0c, 0x89, 0x02, 0xc1, 0x00, 0xb9,
+ 0x02, 0x06, 0x00, 0xd4, 0x40, 0xb4, 0xfe, 0xc0,
+ 0x16, 0x61, 0x91, 0x48, 0x16, 0x89, 0xfb, 0xc0,
+ 0x11, 0x19, 0x0c, 0x89, 0x02, 0xc1, 0x00, 0xb9,
+ 0xd2, 0x05, 0x00, 0x00 };
+
+static u16 r8153_usb_patch_c_bp[] = {
+ 0xfc26, 0xa000, 0xfc28, 0x3b34, 0xfc2a, 0x027c, 0xfc2c, 0x162c,
+ 0xfc2e, 0x10ce, 0xfc30, 0x0000, 0xfc32, 0x3a28, 0xfc34, 0x05f8,
+ 0xfc36, 0x05c8 };
+
+static u8 r8153_pla_patch_c[] = {
+ 0x08, 0xe0, 0xea, 0xe0, 0xf2, 0xe0, 0x04, 0xe1,
+ 0x06, 0xe1, 0x08, 0xe1, 0x40, 0xe1, 0xf1, 0xe1,
+ 0x14, 0xc2, 0x40, 0x73, 0xba, 0x48, 0x40, 0x9b,
+ 0x11, 0xc2, 0x40, 0x73, 0xb0, 0x49, 0x17, 0xf0,
+ 0xbf, 0x49, 0x03, 0xf1, 0x09, 0xc5, 0x00, 0xbd,
+ 0xb1, 0x49, 0x11, 0xf0, 0xb1, 0x48, 0x40, 0x9b,
+ 0x02, 0xc2, 0x00, 0xba, 0xde, 0x18, 0x00, 0xe0,
+ 0x1e, 0xfc, 0xbc, 0xc0, 0xf0, 0xc0, 0xde, 0xe8,
+ 0x00, 0x80, 0x00, 0x20, 0x2c, 0x75, 0xd4, 0x49,
+ 0x12, 0xf1, 0x32, 0xe0, 0xf8, 0xc2, 0x46, 0x71,
+ 0xf7, 0xc2, 0x40, 0x73, 0xbe, 0x49, 0x03, 0xf1,
+ 0xf5, 0xc7, 0x02, 0xe0, 0xf2, 0xc7, 0x4f, 0x30,
+ 0x26, 0x62, 0xa1, 0x49, 0xf0, 0xf1, 0x22, 0x72,
+ 0xa0, 0x49, 0xed, 0xf1, 0x25, 0x25, 0x18, 0x1f,
+ 0x97, 0x30, 0x91, 0x30, 0x36, 0x9a, 0x2c, 0x75,
+ 0x3c, 0xc3, 0x60, 0x73, 0xb1, 0x49, 0x0d, 0xf1,
+ 0xdc, 0x21, 0xbc, 0x25, 0x30, 0xc6, 0xc0, 0x77,
+ 0x04, 0x13, 0x21, 0xf0, 0x03, 0x13, 0x22, 0xf0,
+ 0x02, 0x13, 0x23, 0xf0, 0x01, 0x13, 0x24, 0xf0,
+ 0x08, 0x13, 0x08, 0xf1, 0x2e, 0x73, 0xba, 0x21,
+ 0xbd, 0x25, 0x05, 0x13, 0x03, 0xf1, 0x24, 0xc5,
+ 0x00, 0xbd, 0xd4, 0x49, 0x03, 0xf1, 0x1c, 0xc5,
+ 0x00, 0xbd, 0xc4, 0xc6, 0xc6, 0x67, 0x2e, 0x75,
+ 0xd7, 0x22, 0xdd, 0x26, 0x05, 0x15, 0x1b, 0xf0,
+ 0x14, 0xc6, 0x00, 0xbe, 0x13, 0xc5, 0x00, 0xbd,
+ 0x12, 0xc5, 0x00, 0xbd, 0xf1, 0x49, 0xfb, 0xf1,
+ 0xef, 0xe7, 0xf4, 0x49, 0xfa, 0xf1, 0xec, 0xe7,
+ 0xf3, 0x49, 0xf7, 0xf1, 0xe9, 0xe7, 0xf2, 0x49,
+ 0xf4, 0xf1, 0xe6, 0xe7, 0xb6, 0xc0, 0x50, 0x14,
+ 0x90, 0x13, 0xbc, 0x13, 0xf2, 0x14, 0x00, 0xa0,
+ 0xa0, 0xd1, 0x00, 0x00, 0xc0, 0x75, 0xd0, 0x49,
+ 0x46, 0xf0, 0x26, 0x72, 0xa7, 0x49, 0x43, 0xf0,
+ 0x22, 0x72, 0x25, 0x25, 0x20, 0x1f, 0x97, 0x30,
+ 0x91, 0x30, 0x40, 0x73, 0xf3, 0xc4, 0x1c, 0x40,
+ 0x04, 0xf0, 0xd7, 0x49, 0x05, 0xf1, 0x37, 0xe0,
+ 0x53, 0x48, 0xc0, 0x9d, 0x08, 0x02, 0x40, 0x66,
+ 0x64, 0x27, 0x06, 0x16, 0x30, 0xf1, 0x46, 0x63,
+ 0x3b, 0x13, 0x2d, 0xf1, 0x34, 0x9b, 0x18, 0x1b,
+ 0x93, 0x30, 0x2b, 0xc3, 0x10, 0x1c, 0x2b, 0xe8,
+ 0x01, 0x14, 0x25, 0xf1, 0x00, 0x1d, 0x26, 0x1a,
+ 0x8a, 0x30, 0x22, 0x73, 0xb5, 0x25, 0x0e, 0x0b,
+ 0x00, 0x1c, 0x2c, 0xe8, 0x1f, 0xc7, 0x27, 0x40,
+ 0x1a, 0xf1, 0x38, 0xe8, 0x32, 0x1f, 0x8f, 0x30,
+ 0x08, 0x1b, 0x24, 0xe8, 0x36, 0x72, 0x46, 0x77,
+ 0x00, 0x17, 0x0d, 0xf0, 0x13, 0xc3, 0x1f, 0x40,
+ 0x03, 0xf1, 0x00, 0x1f, 0x46, 0x9f, 0x44, 0x77,
+ 0x9f, 0x44, 0x5f, 0x44, 0x17, 0xe8, 0x0a, 0xc7,
+ 0x27, 0x40, 0x05, 0xf1, 0x02, 0xc3, 0x00, 0xbb,
+ 0xbe, 0x1a, 0x74, 0x14, 0xff, 0xc7, 0x00, 0xbf,
+ 0xb8, 0xcd, 0xff, 0xff, 0x02, 0x0c, 0x54, 0xa5,
+ 0xdc, 0xa5, 0x2f, 0x40, 0x05, 0xf1, 0x00, 0x14,
+ 0xfa, 0xf1, 0x01, 0x1c, 0x02, 0xe0, 0x00, 0x1c,
+ 0x80, 0xff, 0xb0, 0x49, 0x04, 0xf0, 0x01, 0x0b,
+ 0xd3, 0xa1, 0x03, 0xe0, 0x02, 0x0b, 0xd3, 0xa5,
+ 0x27, 0x31, 0x20, 0x37, 0x02, 0x0b, 0xd3, 0xa5,
+ 0x27, 0x31, 0x20, 0x37, 0x00, 0x13, 0xfb, 0xf1,
+ 0x80, 0xff, 0x22, 0x73, 0xb5, 0x25, 0x18, 0x1e,
+ 0xde, 0x30, 0xd9, 0x30, 0x64, 0x72, 0x11, 0x1e,
+ 0x68, 0x23, 0x16, 0x31, 0x80, 0xff, 0x08, 0xc2,
+ 0x40, 0x73, 0x3a, 0x48, 0x40, 0x9b, 0x06, 0xff,
+ 0x02, 0xc6, 0x00, 0xbe, 0xcc, 0x17, 0x1e, 0xfc,
+ 0x2c, 0x75, 0xdc, 0x21, 0xbc, 0x25, 0x04, 0x13,
+ 0x0b, 0xf0, 0x03, 0x13, 0x09, 0xf0, 0x02, 0x13,
+ 0x07, 0xf0, 0x01, 0x13, 0x05, 0xf0, 0x08, 0x13,
+ 0x03, 0xf0, 0x04, 0xc3, 0x00, 0xbb, 0x03, 0xc3,
+ 0x00, 0xbb, 0x50, 0x17, 0x3a, 0x17, 0x02, 0xc6,
+ 0x00, 0xbe, 0x00, 0x00, 0x02, 0xc6, 0x00, 0xbe,
+ 0x00, 0x00, 0x33, 0xc5, 0xa0, 0x74, 0xc0, 0x49,
+ 0x1f, 0xf0, 0x30, 0xc5, 0xa0, 0x73, 0x00, 0x13,
+ 0x04, 0xf1, 0xa2, 0x73, 0x00, 0x13, 0x14, 0xf0,
+ 0x28, 0xc5, 0xa0, 0x74, 0xc8, 0x49, 0x1b, 0xf1,
+ 0x26, 0xc5, 0xa0, 0x76, 0xa2, 0x74, 0x01, 0x06,
+ 0x20, 0x37, 0xa0, 0x9e, 0xa2, 0x9c, 0x1e, 0xc5,
+ 0xa2, 0x73, 0x23, 0x40, 0x10, 0xf8, 0x04, 0xf3,
+ 0xa0, 0x73, 0x33, 0x40, 0x0c, 0xf8, 0x15, 0xc5,
+ 0xa0, 0x74, 0x41, 0x48, 0xa0, 0x9c, 0x14, 0xc5,
+ 0xa0, 0x76, 0x62, 0x48, 0xe0, 0x48, 0xa0, 0x9e,
+ 0x10, 0xc6, 0x00, 0xbe, 0x0a, 0xc5, 0xa0, 0x74,
+ 0x48, 0x48, 0xa0, 0x9c, 0x0b, 0xc5, 0x20, 0x1e,
+ 0xa0, 0x9e, 0xe5, 0x48, 0xa0, 0x9e, 0xf0, 0xe7,
+ 0xbc, 0xc0, 0xc8, 0xd2, 0xcc, 0xd2, 0x28, 0xe4,
+ 0xfa, 0x01, 0xf0, 0xc0, 0x18, 0x89, 0x00, 0x1d,
+ 0x43, 0xc3, 0x62, 0x62, 0xa0, 0x49, 0x06, 0xf0,
+ 0x41, 0xc0, 0x02, 0x71, 0x60, 0x99, 0x3f, 0xc1,
+ 0x03, 0xe0, 0x3c, 0xc0, 0x3d, 0xc1, 0x02, 0x99,
+ 0x00, 0x61, 0x67, 0x11, 0x3d, 0xf1, 0x69, 0x33,
+ 0x34, 0xc0, 0x28, 0x40, 0xf7, 0xf1, 0x35, 0xc0,
+ 0x00, 0x19, 0x81, 0x1b, 0x89, 0xe8, 0x32, 0xc0,
+ 0x04, 0x1a, 0x84, 0x1b, 0x85, 0xe8, 0x7a, 0xe8,
+ 0xa3, 0x49, 0xfe, 0xf0, 0x2c, 0xc0, 0x76, 0xe8,
+ 0xa1, 0x48, 0x29, 0xc0, 0x84, 0x1b, 0x7c, 0xe8,
+ 0x00, 0x1d, 0x69, 0x33, 0x00, 0x1e, 0x01, 0x06,
+ 0xff, 0x18, 0x30, 0x40, 0xfd, 0xf1, 0x7f, 0xc0,
+ 0x00, 0x76, 0x2e, 0x40, 0xf7, 0xf1, 0x21, 0x48,
+ 0x1a, 0xc0, 0x84, 0x1b, 0x6d, 0xe8, 0x76, 0xc0,
+ 0x61, 0xe8, 0xa1, 0x49, 0xfd, 0xf0, 0x12, 0xc0,
+ 0x00, 0x1a, 0x84, 0x1b, 0x65, 0xe8, 0x5a, 0xe8,
+ 0xa5, 0x49, 0xfe, 0xf0, 0x0a, 0xc0, 0x01, 0x19,
+ 0x81, 0x1b, 0x5e, 0xe8, 0x48, 0xe0, 0x8c, 0xd3,
+ 0xb8, 0x0b, 0x50, 0xe8, 0x83, 0x00, 0x82, 0x00,
+ 0x20, 0xb4, 0x10, 0xd8, 0x84, 0xd4, 0xfa, 0xc0,
+ 0x00, 0x61, 0x9c, 0x20, 0x9c, 0x24, 0x06, 0x11,
+ 0x06, 0xf1, 0x5d, 0xc0, 0x00, 0x61, 0x11, 0x48,
+ 0x00, 0x89, 0x35, 0xe0, 0x00, 0x11, 0x02, 0xf1,
+ 0x03, 0xe0, 0x04, 0x11, 0x06, 0xf1, 0x53, 0xc0,
+ 0x00, 0x61, 0x92, 0x48, 0x00, 0x89, 0x2b, 0xe0,
+ 0x05, 0x11, 0x08, 0xf1, 0x4c, 0xc0, 0x00, 0x61,
+ 0x91, 0x49, 0x04, 0xf0, 0x91, 0x48, 0x00, 0x89,
+ 0x11, 0xe0, 0xdc, 0xc0, 0x00, 0x61, 0x98, 0x20,
+ 0x98, 0x24, 0x25, 0x11, 0x1c, 0xf1, 0x40, 0xc0,
+ 0x25, 0xe8, 0x95, 0x49, 0x18, 0xf0, 0xd2, 0xc0,
+ 0x00, 0x61, 0x98, 0x20, 0x98, 0x24, 0x25, 0x11,
+ 0x12, 0xf1, 0x35, 0xc0, 0x00, 0x61, 0x92, 0x49,
+ 0x0e, 0xf1, 0x12, 0x48, 0x00, 0x89, 0x2d, 0xc0,
+ 0x00, 0x19, 0x00, 0x89, 0x2b, 0xc0, 0x01, 0x89,
+ 0x27, 0xc0, 0x10, 0xe8, 0x25, 0xc0, 0x12, 0x48,
+ 0x81, 0x1b, 0x16, 0xe8, 0xb9, 0xc3, 0x62, 0x62,
+ 0xa0, 0x49, 0x05, 0xf0, 0xb5, 0xc3, 0x60, 0x71,
+ 0xb5, 0xc0, 0x02, 0x99, 0x02, 0xc0, 0x00, 0xb8,
+ 0xd6, 0x07, 0x13, 0xc4, 0x84, 0x98, 0x00, 0x1b,
+ 0x86, 0x8b, 0x86, 0x73, 0xbf, 0x49, 0xfe, 0xf1,
+ 0x80, 0x71, 0x82, 0x72, 0x80, 0xff, 0x09, 0xc4,
+ 0x84, 0x98, 0x80, 0x99, 0x82, 0x9a, 0x86, 0x8b,
+ 0x86, 0x73, 0xbf, 0x49, 0xfe, 0xf1, 0x80, 0xff,
+ 0x08, 0xea, 0x10, 0xd4, 0x88, 0xd3, 0x30, 0xd4,
+ 0x10, 0xc0, 0x12, 0xe8, 0x8a, 0xd3, 0x00, 0xd8,
+ 0x02, 0xc0, 0x00, 0xb8, 0xe0, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+
+static u16 r8153_pla_patch_c_bp[] = {
+ 0xfc26, 0x8000, 0xfc28, 0x1306, 0xfc2a, 0x17ca, 0xfc2c, 0x171e,
+ 0xfc2e, 0x0000, 0xfc30, 0x0000, 0xfc32, 0x01b4, 0xfc34, 0x07d4,
+ 0xfc36, 0x0894, 0xfc38, 0x00e7 };
+
+static u16 r8153_ram_code_bc[] = {
+ 0xB436, 0xB820, 0xB438, 0x0290, 0xB436, 0xA012, 0xB438, 0x0000,
+ 0xB436, 0xA014, 0xB438, 0x2c04, 0xB438, 0x2c07, 0xB438, 0x2c0a,
+ 0xB438, 0x2c0d, 0xB438, 0xa240, 0xB438, 0xa104, 0xB438, 0x292d,
+ 0xB438, 0x8620, 0xB438, 0xa480, 0xB438, 0x2a2c, 0xB438, 0x8480,
+ 0xB438, 0xa101, 0xB438, 0x2a36, 0xB438, 0xd056, 0xB438, 0x2223,
+ 0xB436, 0xA01A, 0xB438, 0x0000, 0xB436, 0xA006, 0xB438, 0x0222,
+ 0xB436, 0xA004, 0xB438, 0x0a35, 0xB436, 0xA002, 0xB438, 0x0a2b,
+ 0xB436, 0xA000, 0xB438, 0xf92c, 0xB436, 0xB820, 0xB438, 0x0210 };
+
+static u8 r8153_usb_patch_b[] = {
+ 0x08, 0xe0, 0x0f, 0xe0, 0x18, 0xe0, 0x24, 0xe0,
+ 0x26, 0xe0, 0x3a, 0xe0, 0x84, 0xe0, 0x9c, 0xe0,
+ 0xc2, 0x49, 0x04, 0xf0, 0x02, 0xc0, 0x00, 0xb8,
+ 0x14, 0x18, 0x02, 0xc0, 0x00, 0xb8, 0x2e, 0x18,
+ 0x06, 0x89, 0x08, 0xc0, 0x0c, 0x61, 0x92, 0x48,
+ 0x93, 0x48, 0x0c, 0x89, 0x02, 0xc0, 0x00, 0xb8,
+ 0x08, 0x05, 0x40, 0xb4, 0x16, 0x89, 0x6d, 0xc0,
+ 0x00, 0x61, 0x95, 0x49, 0x06, 0xf0, 0xfa, 0xc0,
+ 0x0c, 0x61, 0x92, 0x48, 0x93, 0x48, 0x0c, 0x89,
+ 0x02, 0xc0, 0x00, 0xb8, 0xe2, 0x04, 0x02, 0xc2,
+ 0x00, 0xba, 0xec, 0x11, 0x60, 0x60, 0x85, 0x49,
+ 0x0d, 0xf1, 0x11, 0xc6, 0xd2, 0x61, 0x91, 0x49,
+ 0xfd, 0xf0, 0x74, 0x60, 0x04, 0x48, 0x74, 0x88,
+ 0x08, 0xc6, 0x08, 0xc0, 0xc4, 0x98, 0x01, 0x18,
+ 0xc0, 0x88, 0x02, 0xc0, 0x00, 0xb8, 0x6e, 0x12,
+ 0x04, 0xe4, 0x0d, 0x00, 0x00, 0xd4, 0xd1, 0x49,
+ 0x3c, 0xf1, 0xd2, 0x49, 0x16, 0xf1, 0xd3, 0x49,
+ 0x18, 0xf1, 0xd4, 0x49, 0x19, 0xf1, 0xd5, 0x49,
+ 0x1a, 0xf1, 0xd6, 0x49, 0x1b, 0xf1, 0xd7, 0x49,
+ 0x1c, 0xf1, 0xd8, 0x49, 0x1d, 0xf1, 0xd9, 0x49,
+ 0x20, 0xf1, 0xda, 0x49, 0x23, 0xf1, 0xdb, 0x49,
+ 0x24, 0xf1, 0x02, 0xc4, 0x00, 0xbc, 0x20, 0x04,
+ 0xe5, 0x8e, 0x02, 0xc4, 0x00, 0xbc, 0x14, 0x02,
+ 0x02, 0xc4, 0x00, 0xbc, 0x16, 0x02, 0x02, 0xc4,
+ 0x00, 0xbc, 0x18, 0x02, 0x02, 0xc4, 0x00, 0xbc,
+ 0x1a, 0x02, 0x02, 0xc4, 0x00, 0xbc, 0x1c, 0x02,
+ 0x02, 0xc4, 0x00, 0xbc, 0x94, 0x02, 0x10, 0xc7,
+ 0xe0, 0x8e, 0x02, 0xc4, 0x00, 0xbc, 0x8a, 0x02,
+ 0x0b, 0xc7, 0xe4, 0x8e, 0x02, 0xc4, 0x00, 0xbc,
+ 0x88, 0x02, 0x02, 0xc4, 0x00, 0xbc, 0x6e, 0x02,
+ 0x02, 0xc4, 0x00, 0xbc, 0x5a, 0x02, 0x30, 0xe4,
+ 0x0c, 0xc3, 0x60, 0x64, 0xc5, 0x49, 0x04, 0xf1,
+ 0x74, 0x64, 0xc4, 0x48, 0x74, 0x8c, 0x06, 0xc3,
+ 0x64, 0x8e, 0x02, 0xc4, 0x00, 0xbc, 0x20, 0x04,
+ 0x00, 0xd8, 0x00, 0xe4, 0xb2, 0xc0, 0x00, 0x61,
+ 0x90, 0x49, 0x09, 0xf1, 0x8b, 0xc6, 0xca, 0x61,
+ 0x94, 0x49, 0x0e, 0xf1, 0xf6, 0xc6, 0xda, 0x60,
+ 0x81, 0x49, 0x0a, 0xf0, 0x65, 0x60, 0x03, 0x48,
+ 0x65, 0x88, 0xef, 0xc6, 0xdc, 0x60, 0x80, 0x48,
+ 0xdc, 0x88, 0x05, 0xc6, 0x00, 0xbe, 0x02, 0xc6,
+ 0x00, 0xbe, 0x36, 0x13, 0x4c, 0x17, 0x99, 0xc4,
+ 0x80, 0x65, 0xd0, 0x49, 0x04, 0xf1, 0xfa, 0x75,
+ 0x04, 0xc4, 0x00, 0xbc, 0x03, 0xc4, 0x00, 0xbc,
+ 0x9a, 0x00, 0xee, 0x01 };
+
+static u16 r8153_usb_patch_b_bp[] = {
+ 0xfc26, 0xa000, 0xfc28, 0x180c, 0xfc2a, 0x0506, 0xfc2c, 0x04E0,
+ 0xfc2e, 0x11E4, 0xfc30, 0x125C, 0xfc32, 0x0232, 0xfc34, 0x131E,
+ 0xfc36, 0x0098, 0xfc38, 0x00FF };
+
+static u8 r8153_pla_patch_b[] = {
+ 0x08, 0xe0, 0xea, 0xe0, 0xf2, 0xe0, 0x04, 0xe1,
+ 0x09, 0xe1, 0x0e, 0xe1, 0x46, 0xe1, 0xf3, 0xe1,
+ 0x14, 0xc2, 0x40, 0x73, 0xba, 0x48, 0x40, 0x9b,
+ 0x11, 0xc2, 0x40, 0x73, 0xb0, 0x49, 0x17, 0xf0,
+ 0xbf, 0x49, 0x03, 0xf1, 0x09, 0xc5, 0x00, 0xbd,
+ 0xb1, 0x49, 0x11, 0xf0, 0xb1, 0x48, 0x40, 0x9b,
+ 0x02, 0xc2, 0x00, 0xba, 0x1a, 0x17, 0x00, 0xe0,
+ 0x1e, 0xfc, 0xbc, 0xc0, 0xf0, 0xc0, 0xde, 0xe8,
+ 0x00, 0x80, 0x00, 0x20, 0x2c, 0x75, 0xd4, 0x49,
+ 0x12, 0xf1, 0x32, 0xe0, 0xf8, 0xc2, 0x46, 0x71,
+ 0xf7, 0xc2, 0x40, 0x73, 0xbe, 0x49, 0x03, 0xf1,
+ 0xf5, 0xc7, 0x02, 0xe0, 0xf2, 0xc7, 0x4f, 0x30,
+ 0x26, 0x62, 0xa1, 0x49, 0xf0, 0xf1, 0x22, 0x72,
+ 0xa0, 0x49, 0xed, 0xf1, 0x25, 0x25, 0x18, 0x1f,
+ 0x97, 0x30, 0x91, 0x30, 0x36, 0x9a, 0x2c, 0x75,
+ 0x3c, 0xc3, 0x60, 0x73, 0xb1, 0x49, 0x0d, 0xf1,
+ 0xdc, 0x21, 0xbc, 0x25, 0x30, 0xc6, 0xc0, 0x77,
+ 0x04, 0x13, 0x21, 0xf0, 0x03, 0x13, 0x22, 0xf0,
+ 0x02, 0x13, 0x23, 0xf0, 0x01, 0x13, 0x24, 0xf0,
+ 0x08, 0x13, 0x08, 0xf1, 0x2e, 0x73, 0xba, 0x21,
+ 0xbd, 0x25, 0x05, 0x13, 0x03, 0xf1, 0x24, 0xc5,
+ 0x00, 0xbd, 0xd4, 0x49, 0x03, 0xf1, 0x1c, 0xc5,
+ 0x00, 0xbd, 0xc4, 0xc6, 0xc6, 0x67, 0x2e, 0x75,
+ 0xd7, 0x22, 0xdd, 0x26, 0x05, 0x15, 0x1b, 0xf0,
+ 0x14, 0xc6, 0x00, 0xbe, 0x13, 0xc5, 0x00, 0xbd,
+ 0x12, 0xc5, 0x00, 0xbd, 0xf1, 0x49, 0xfb, 0xf1,
+ 0xef, 0xe7, 0xf4, 0x49, 0xfa, 0xf1, 0xec, 0xe7,
+ 0xf3, 0x49, 0xf7, 0xf1, 0xe9, 0xe7, 0xf2, 0x49,
+ 0xf4, 0xf1, 0xe6, 0xe7, 0xb6, 0xc0, 0x9e, 0x12,
+ 0xde, 0x11, 0x0a, 0x12, 0x3c, 0x13, 0x00, 0xa0,
+ 0xa0, 0xd1, 0x00, 0x00, 0xc0, 0x75, 0xd0, 0x49,
+ 0x46, 0xf0, 0x26, 0x72, 0xa7, 0x49, 0x43, 0xf0,
+ 0x22, 0x72, 0x25, 0x25, 0x20, 0x1f, 0x97, 0x30,
+ 0x91, 0x30, 0x40, 0x73, 0xf3, 0xc4, 0x1c, 0x40,
+ 0x04, 0xf0, 0xd7, 0x49, 0x05, 0xf1, 0x37, 0xe0,
+ 0x53, 0x48, 0xc0, 0x9d, 0x08, 0x02, 0x40, 0x66,
+ 0x64, 0x27, 0x06, 0x16, 0x30, 0xf1, 0x46, 0x63,
+ 0x3b, 0x13, 0x2d, 0xf1, 0x34, 0x9b, 0x18, 0x1b,
+ 0x93, 0x30, 0x2b, 0xc3, 0x10, 0x1c, 0x2b, 0xe8,
+ 0x01, 0x14, 0x25, 0xf1, 0x00, 0x1d, 0x26, 0x1a,
+ 0x8a, 0x30, 0x22, 0x73, 0xb5, 0x25, 0x0e, 0x0b,
+ 0x00, 0x1c, 0x2c, 0xe8, 0x1f, 0xc7, 0x27, 0x40,
+ 0x1a, 0xf1, 0x38, 0xe8, 0x32, 0x1f, 0x8f, 0x30,
+ 0x08, 0x1b, 0x24, 0xe8, 0x36, 0x72, 0x46, 0x77,
+ 0x00, 0x17, 0x0d, 0xf0, 0x13, 0xc3, 0x1f, 0x40,
+ 0x03, 0xf1, 0x00, 0x1f, 0x46, 0x9f, 0x44, 0x77,
+ 0x9f, 0x44, 0x5f, 0x44, 0x17, 0xe8, 0x0a, 0xc7,
+ 0x27, 0x40, 0x05, 0xf1, 0x02, 0xc3, 0x00, 0xbb,
+ 0xfa, 0x18, 0xb0, 0x18, 0xff, 0xc7, 0x00, 0xbf,
+ 0xb8, 0xcd, 0xff, 0xff, 0x02, 0x0c, 0x54, 0xa5,
+ 0xdc, 0xa5, 0x2f, 0x40, 0x05, 0xf1, 0x00, 0x14,
+ 0xfa, 0xf1, 0x01, 0x1c, 0x02, 0xe0, 0x00, 0x1c,
+ 0x80, 0xff, 0xb0, 0x49, 0x04, 0xf0, 0x01, 0x0b,
+ 0xd3, 0xa1, 0x03, 0xe0, 0x02, 0x0b, 0xd3, 0xa5,
+ 0x27, 0x31, 0x20, 0x37, 0x02, 0x0b, 0xd3, 0xa5,
+ 0x27, 0x31, 0x20, 0x37, 0x00, 0x13, 0xfb, 0xf1,
+ 0x80, 0xff, 0x22, 0x73, 0xb5, 0x25, 0x18, 0x1e,
+ 0xde, 0x30, 0xd9, 0x30, 0x64, 0x72, 0x11, 0x1e,
+ 0x68, 0x23, 0x16, 0x31, 0x80, 0xff, 0x08, 0xc2,
+ 0x40, 0x73, 0x3a, 0x48, 0x40, 0x9b, 0x06, 0xff,
+ 0x02, 0xc6, 0x00, 0xbe, 0x08, 0x16, 0x1e, 0xfc,
+ 0x2c, 0x75, 0xdc, 0x21, 0xbc, 0x25, 0x04, 0x13,
+ 0x0b, 0xf0, 0x03, 0x13, 0x09, 0xf0, 0x02, 0x13,
+ 0x07, 0xf0, 0x01, 0x13, 0x05, 0xf0, 0x08, 0x13,
+ 0x03, 0xf0, 0x04, 0xc3, 0x00, 0xbb, 0x03, 0xc3,
+ 0x00, 0xbb, 0x8c, 0x15, 0x76, 0x15, 0xa0, 0x64,
+ 0x40, 0x48, 0xa0, 0x8c, 0x02, 0xc4, 0x00, 0xbc,
+ 0x82, 0x00, 0xa0, 0x62, 0x21, 0x48, 0xa0, 0x8a,
+ 0x02, 0xc2, 0x00, 0xba, 0x40, 0x03, 0x33, 0xc5,
+ 0xa0, 0x74, 0xc0, 0x49, 0x1f, 0xf0, 0x30, 0xc5,
+ 0xa0, 0x73, 0x00, 0x13, 0x04, 0xf1, 0xa2, 0x73,
+ 0x00, 0x13, 0x14, 0xf0, 0x28, 0xc5, 0xa0, 0x74,
+ 0xc8, 0x49, 0x1b, 0xf1, 0x26, 0xc5, 0xa0, 0x76,
+ 0xa2, 0x74, 0x01, 0x06, 0x20, 0x37, 0xa0, 0x9e,
+ 0xa2, 0x9c, 0x1e, 0xc5, 0xa2, 0x73, 0x23, 0x40,
+ 0x10, 0xf8, 0x04, 0xf3, 0xa0, 0x73, 0x33, 0x40,
+ 0x0c, 0xf8, 0x15, 0xc5, 0xa0, 0x74, 0x41, 0x48,
+ 0xa0, 0x9c, 0x14, 0xc5, 0xa0, 0x76, 0x62, 0x48,
+ 0xe0, 0x48, 0xa0, 0x9e, 0x10, 0xc6, 0x00, 0xbe,
+ 0x0a, 0xc5, 0xa0, 0x74, 0x48, 0x48, 0xa0, 0x9c,
+ 0x0b, 0xc5, 0x20, 0x1e, 0xa0, 0x9e, 0xe5, 0x48,
+ 0xa0, 0x9e, 0xf0, 0xe7, 0xbc, 0xc0, 0xc8, 0xd2,
+ 0xcc, 0xd2, 0x28, 0xe4, 0xe6, 0x01, 0xf0, 0xc0,
+ 0x18, 0x89, 0x00, 0x1d, 0x3c, 0xc3, 0x60, 0x71,
+ 0x3c, 0xc0, 0x02, 0x99, 0x00, 0x61, 0x67, 0x11,
+ 0x3c, 0xf1, 0x69, 0x33, 0x35, 0xc0, 0x28, 0x40,
+ 0xf6, 0xf1, 0x34, 0xc0, 0x00, 0x19, 0x81, 0x1b,
+ 0x8c, 0xe8, 0x31, 0xc0, 0x04, 0x1a, 0x84, 0x1b,
+ 0x88, 0xe8, 0x7d, 0xe8, 0xa3, 0x49, 0xfe, 0xf0,
+ 0x2b, 0xc0, 0x79, 0xe8, 0xa1, 0x48, 0x28, 0xc0,
+ 0x84, 0x1b, 0x7f, 0xe8, 0x00, 0x1d, 0x69, 0x33,
+ 0x00, 0x1e, 0x01, 0x06, 0xff, 0x18, 0x30, 0x40,
+ 0xfd, 0xf1, 0x18, 0xc0, 0x00, 0x76, 0x2e, 0x40,
+ 0xf7, 0xf1, 0x21, 0x48, 0x19, 0xc0, 0x84, 0x1b,
+ 0x70, 0xe8, 0x79, 0xc0, 0x64, 0xe8, 0xa1, 0x49,
+ 0xfd, 0xf0, 0x11, 0xc0, 0x00, 0x1a, 0x84, 0x1b,
+ 0x68, 0xe8, 0x5d, 0xe8, 0xa5, 0x49, 0xfe, 0xf0,
+ 0x09, 0xc0, 0x01, 0x19, 0x81, 0x1b, 0x61, 0xe8,
+ 0x4f, 0xe0, 0x88, 0xd3, 0x8c, 0xd3, 0xb8, 0x0b,
+ 0x50, 0xe8, 0x20, 0xb4, 0x10, 0xd8, 0x84, 0xd4,
+ 0xfc, 0xc0, 0x00, 0x61, 0x9c, 0x20, 0x9c, 0x24,
+ 0x06, 0x11, 0x06, 0xf1, 0x60, 0xc0, 0x00, 0x61,
+ 0x11, 0x48, 0x00, 0x89, 0x3d, 0xe0, 0x00, 0x11,
+ 0x02, 0xf1, 0x03, 0xe0, 0x04, 0x11, 0x06, 0xf1,
+ 0x56, 0xc0, 0x00, 0x61, 0x92, 0x48, 0x00, 0x89,
+ 0x33, 0xe0, 0x05, 0x11, 0x08, 0xf1, 0x4f, 0xc0,
+ 0x00, 0x61, 0x91, 0x49, 0x04, 0xf0, 0x91, 0x48,
+ 0x00, 0x89, 0x11, 0xe0, 0xde, 0xc0, 0x00, 0x61,
+ 0x98, 0x20, 0x98, 0x24, 0x25, 0x11, 0x24, 0xf1,
+ 0x45, 0xc0, 0x29, 0xe8, 0x95, 0x49, 0x20, 0xf0,
+ 0xd4, 0xc0, 0x00, 0x61, 0x98, 0x20, 0x98, 0x24,
+ 0x25, 0x11, 0x1a, 0xf1, 0x38, 0xc0, 0x00, 0x61,
+ 0x92, 0x49, 0x16, 0xf1, 0x12, 0x48, 0x00, 0x89,
+ 0x30, 0xc0, 0x00, 0x19, 0x00, 0x89, 0x2e, 0xc0,
+ 0x01, 0x89, 0x2e, 0xc0, 0x04, 0x19, 0x81, 0x1b,
+ 0x1c, 0xe8, 0x2b, 0xc0, 0x14, 0x19, 0x81, 0x1b,
+ 0x18, 0xe8, 0x22, 0xc0, 0x0c, 0xe8, 0x20, 0xc0,
+ 0x12, 0x48, 0x81, 0x1b, 0x12, 0xe8, 0xb3, 0xc3,
+ 0x62, 0x71, 0xb3, 0xc0, 0x02, 0x99, 0x02, 0xc0,
+ 0x00, 0xb8, 0x96, 0x07, 0x13, 0xc4, 0x84, 0x98,
+ 0x00, 0x1b, 0x86, 0x8b, 0x86, 0x73, 0xbf, 0x49,
+ 0xfe, 0xf1, 0x80, 0x71, 0x82, 0x72, 0x80, 0xff,
+ 0x09, 0xc4, 0x84, 0x98, 0x80, 0x99, 0x82, 0x9a,
+ 0x86, 0x8b, 0x86, 0x73, 0xbf, 0x49, 0xfe, 0xf1,
+ 0x80, 0xff, 0x08, 0xea, 0x10, 0xd4, 0x30, 0xd4,
+ 0x10, 0xc0, 0x12, 0xe8, 0x8a, 0xd3, 0x28, 0xe4,
+ 0x2c, 0xe4, 0x00, 0xd8, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+
+static u16 r8153_pla_patch_b_bp[] = {
+ 0xfc26, 0x8000, 0xfc28, 0x1154, 0xfc2a, 0x1606, 0xfc2c, 0x155a,
+ 0xfc2e, 0x0080, 0xfc30, 0x033c, 0xfc32, 0x01a0, 0xfc34, 0x0794,
+ 0xfc36, 0x0000, 0xfc38, 0x007f };
+
+static u16 r8153_ram_code_d[] = {
+ 0xa436, 0xb820, 0xa438, 0x0290, 0xa436, 0xa012, 0xa438, 0x0000,
+ 0xa436, 0xa014, 0xa438, 0x2c04, 0xb438, 0x2c07, 0xb438, 0x2c07,
+ 0xb438, 0x2c07, 0xb438, 0xa240, 0xb438, 0xa104, 0xb438, 0x2944,
+ 0xa436, 0xa01a, 0xa438, 0x0000, 0xa436, 0xa006, 0xa438, 0x0fff,
+ 0xa436, 0xa004, 0xa438, 0x0fff, 0xa436, 0xa002, 0xa438, 0x0fff,
+ 0xa436, 0xa000, 0xa438, 0x1943, 0xa436, 0xb820, 0xa438, 0x0210 };
+
+static u8 usb_patch_d[] = {
+ 0x08, 0xe0, 0x0a, 0xe0, 0x0c, 0xe0, 0x1f, 0xe0,
+ 0x28, 0xe0, 0x2a, 0xe0, 0x2c, 0xe0, 0x2e, 0xe0,
+ 0x02, 0xc5, 0x00, 0xbd, 0x00, 0x00, 0x02, 0xc3,
+ 0x00, 0xbb, 0x00, 0x00, 0x30, 0x18, 0x11, 0xc1,
+ 0x05, 0xe8, 0x10, 0xc6, 0x02, 0xc2, 0x00, 0xba,
+ 0x94, 0x17, 0x02, 0xb4, 0x09, 0xc2, 0x40, 0x99,
+ 0x0e, 0x48, 0x42, 0x98, 0x42, 0x70, 0x8e, 0x49,
+ 0xfe, 0xf1, 0x02, 0xb0, 0x80, 0xff, 0xc0, 0xd4,
+ 0xe4, 0x40, 0x20, 0xd4, 0xb0, 0x49, 0x04, 0xf0,
+ 0x30, 0x18, 0x06, 0xc1, 0xef, 0xef, 0xfa, 0xc7,
+ 0x02, 0xc0, 0x00, 0xb8, 0x38, 0x12, 0xe4, 0x4b,
+ 0x02, 0xc3, 0x00, 0xbb, 0x00, 0x00, 0x02, 0xc5,
+ 0x00, 0xbd, 0x00, 0x00, 0x02, 0xc1, 0x00, 0xb9,
+ 0x00, 0x00, 0x02, 0xc1, 0x00, 0xb9, 0x00, 0x00 };
+
+static u16 r8153_usb_patch_d_bp[] = {
+ 0xfc26, 0xa000, 0xfc28, 0x0000, 0xfc2a, 0x0000, 0xfc2c, 0x1792,
+ 0xfc2e, 0x1236, 0xfc30, 0x0000, 0xfc32, 0x0000, 0xfc34, 0x0000,
+ 0xfc36, 0x0000, 0xfc38, 0x000c };
+
+static void rtl_clear_bp(struct r8152 *tp)
+{
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0);
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0);
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0);
+ ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0);
+ ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0);
+ ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0);
+ ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0);
+ ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0);
+
+ mdelay(6);
+
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0);
+ ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0);
+}
+
+static void r8153_clear_bp(struct r8152 *tp)
+{
+ ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0);
+ ocp_write_byte(tp, MCU_TYPE_USB, USB_BP_EN, 0);
+ rtl_clear_bp(tp);
+}
+
+static void r8152b_set_dq_desc(struct r8152 *tp)
+{
+ u8 data;
+
+ data = ocp_read_byte(tp, MCU_TYPE_USB, 0xd429);
+ data |= 0x80;
+ ocp_write_byte(tp, MCU_TYPE_USB, 0xd429, data);
+ ocp_write_word(tp, MCU_TYPE_USB, 0xc0ce, 0x0210);
+ data = ocp_read_byte(tp, MCU_TYPE_USB, 0xd429);
+ data &= ~0x80;
+ ocp_write_byte(tp, MCU_TYPE_USB, 0xd429, data);
+}
+
+static int r8153_pre_ram_code(struct r8152 *tp, u16 patch_key)
+{
+ u16 data;
+ int i;
+
+ data = ocp_reg_read(tp, 0xb820);
+ data |= 0x0010;
+ ocp_reg_write(tp, 0xb820, data);
+
+ for (i = 0, data = 0; !data && i < 5000; i++) {
+ mdelay(2);
+ data = ocp_reg_read(tp, 0xb800) & 0x0040;
+ }
+
+ sram_write(tp, 0x8146, patch_key);
+ sram_write(tp, 0xb82e, 0x0001);
+
+ return -EBUSY;
+}
+
+static int r8153_post_ram_code(struct r8152 *tp)
+{
+ u16 data;
+
+ sram_write(tp, 0x0000, 0x0000);
+
+ data = ocp_reg_read(tp, 0xb82e);
+ data &= ~0x0001;
+ ocp_reg_write(tp, 0xb82e, data);
+
+ sram_write(tp, 0x8146, 0x0000);
+
+ data = ocp_reg_read(tp, 0xb820);
+ data &= ~0x0010;
+ ocp_reg_write(tp, 0xb820, data);
+
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, tp->ocp_base);
+
+ return 0;
+}
+
+static void r8153_wdt1_end(struct r8152 *tp)
+{
+ int i;
+
+ for (i = 0; i < 104; i++) {
+ if (!(ocp_read_byte(tp, MCU_TYPE_USB, 0xe404) & 1))
+ break;
+ mdelay(2);
+ }
+}
+
+void r8152b_firmware(struct r8152 *tp)
+{
+ int i;
+
+ if (tp->version == RTL_VER_01) {
+ int i;
+
+ r8152b_set_dq_desc(tp);
+ rtl_clear_bp(tp);
+
+ generic_ocp_write(tp, 0xf800, 0x3f,
+ sizeof(r8152b_pla_patch_a),
+ r8152b_pla_patch_a, MCU_TYPE_PLA);
+
+ for (i = 0; i < ARRAY_SIZE(r8152b_pla_patch_a_bp); i += 2)
+ ocp_write_word(tp, MCU_TYPE_PLA,
+ r8152b_pla_patch_a_bp[i],
+ r8152b_pla_patch_a_bp[i+1]);
+
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
+ ocp_write_word(tp, MCU_TYPE_PLA, 0xb092, 0x7070);
+ ocp_write_word(tp, MCU_TYPE_PLA, 0xb098, 0x0600);
+ for (i = 0; i < ARRAY_SIZE(r8152b_ram_code1); i++)
+ ocp_write_word(tp, MCU_TYPE_PLA, 0xb09a,
+ r8152b_ram_code1[i]);
+
+ ocp_write_word(tp, MCU_TYPE_PLA, 0xb098, 0x0200);
+ ocp_write_word(tp, MCU_TYPE_PLA, 0xb092, 0x7030);
+ } else if (tp->version == RTL_VER_02) {
+ rtl_clear_bp(tp);
+
+ generic_ocp_write(tp, 0xf800, 0xff,
+ sizeof(r8152b_pla_patch_a2),
+ r8152b_pla_patch_a2, MCU_TYPE_PLA);
+
+ for (i = 0; i < ARRAY_SIZE(r8152b_pla_patch_a2_bp);
+ i += 2)
+ ocp_write_word(tp, MCU_TYPE_PLA,
+ r8152b_pla_patch_a2_bp[i],
+ r8152b_pla_patch_a2_bp[i+1]);
+ }
+}
+
+void r8153_firmware(struct r8152 *tp)
+{
+ int i;
+
+ if (tp->version == RTL_VER_03) {
+ r8153_clear_bp(tp);
+
+ r8153_pre_ram_code(tp, 0x7000);
+
+ for (i = 0; i < ARRAY_SIZE(r8153_ram_code_a); i += 2)
+ ocp_write_word(tp, MCU_TYPE_PLA,
+ r8153_ram_code_a[i],
+ r8153_ram_code_a[i+1]);
+
+ r8153_post_ram_code(tp);
+ } else if (tp->version == RTL_VER_04) {
+ r8153_pre_ram_code(tp, 0x7001);
+
+ for (i = 0; i < ARRAY_SIZE(r8153_ram_code_bc); i += 2)
+ ocp_write_word(tp, MCU_TYPE_PLA,
+ r8153_ram_code_bc[i],
+ r8153_ram_code_bc[i+1]);
+
+ r8153_post_ram_code(tp);
+
+ r8153_wdt1_end(tp);
+ r8153_clear_bp(tp);
+
+ ocp_write_word(tp, MCU_TYPE_USB, USB_BP_EN, 0x0000);
+ generic_ocp_write(tp, 0xf800, 0xff,
+ sizeof(r8153_usb_patch_b),
+ r8153_usb_patch_b, MCU_TYPE_USB);
+
+ for (i = 0; i < ARRAY_SIZE(r8153_usb_patch_b_bp); i += 2)
+ ocp_write_word(tp, MCU_TYPE_USB,
+ r8153_usb_patch_b_bp[i],
+ r8153_usb_patch_b_bp[i+1]);
+
+ if (!(ocp_read_word(tp, MCU_TYPE_PLA, 0xd38e) & BIT(0))) {
+ ocp_write_word(tp, MCU_TYPE_PLA, 0xd38c, 0x0082);
+ ocp_write_word(tp, MCU_TYPE_PLA, 0xd38e, 0x0082);
+ }
+
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, 0x0000);
+ generic_ocp_write(tp, 0xf800, 0xff,
+ sizeof(r8153_pla_patch_b),
+ r8153_pla_patch_b, MCU_TYPE_PLA);
+
+ for (i = 0; i < ARRAY_SIZE(r8153_pla_patch_b_bp); i += 2)
+ ocp_write_word(tp, MCU_TYPE_PLA,
+ r8153_pla_patch_b_bp[i],
+ r8153_pla_patch_b_bp[i+1]);
+
+ ocp_write_word(tp, MCU_TYPE_PLA, 0xd388, 0x08ca);
+ } else if (tp->version == RTL_VER_05) {
+ u32 ocp_data;
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, 0xcfca);
+ ocp_data &= ~0x4000;
+ ocp_write_word(tp, MCU_TYPE_USB, 0xcfca, ocp_data);
+
+ r8153_pre_ram_code(tp, 0x7001);
+
+ for (i = 0; i < ARRAY_SIZE(r8153_ram_code_bc); i += 2)
+ ocp_write_word(tp, MCU_TYPE_PLA,
+ r8153_ram_code_bc[i],
+ r8153_ram_code_bc[i+1]);
+
+ r8153_post_ram_code(tp);
+
+ r8153_wdt1_end(tp);
+ r8153_clear_bp(tp);
+
+ ocp_write_word(tp, MCU_TYPE_USB, USB_BP_EN, 0x0000);
+ generic_ocp_write(tp, 0xf800, 0xff,
+ sizeof(r8153_usb_patch_c),
+ r8153_usb_patch_c, MCU_TYPE_USB);
+
+ for (i = 0; i < ARRAY_SIZE(r8153_usb_patch_c_bp); i += 2)
+ ocp_write_word(tp, MCU_TYPE_USB,
+ r8153_usb_patch_c_bp[i],
+ r8153_usb_patch_c_bp[i+1]);
+
+ if (ocp_read_byte(tp, MCU_TYPE_USB, 0xcfef) & 1) {
+ ocp_write_word(tp, MCU_TYPE_USB, 0xfc30, 0x1578);
+ ocp_write_word(tp, MCU_TYPE_USB, USB_BP_EN, 0x00ff);
+ } else {
+ ocp_write_word(tp, MCU_TYPE_USB, USB_BP_EN, 0x00ef);
+ }
+
+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, 0x0000);
+ generic_ocp_write(tp, 0xf800, 0xff,
+ sizeof(r8153_pla_patch_c),
+ r8153_pla_patch_c, MCU_TYPE_PLA);
+
+ for (i = 0; i < ARRAY_SIZE(r8153_pla_patch_c_bp); i += 2)
+ ocp_write_word(tp, MCU_TYPE_PLA,
+ r8153_pla_patch_c_bp[i],
+ r8153_pla_patch_c_bp[i+1]);
+
+ ocp_write_word(tp, MCU_TYPE_PLA, 0xd388, 0x08ca);
+
+ ocp_data = ocp_read_word(tp, MCU_TYPE_USB, 0xcfca);
+ ocp_data |= 0x4000;
+ ocp_write_word(tp, MCU_TYPE_USB, 0xcfca, ocp_data);
+ } else if (tp->version == RTL_VER_06) {
+ r8153_pre_ram_code(tp, 0x7002);
+
+ for (i = 0; i < ARRAY_SIZE(r8153_ram_code_d); i += 2)
+ ocp_write_word(tp, MCU_TYPE_PLA,
+ r8153_ram_code_d[i],
+ r8153_ram_code_d[i+1]);
+
+ r8153_post_ram_code(tp);
+
+ r8153_clear_bp(tp);
+
+ ocp_write_word(tp, MCU_TYPE_USB, USB_BP_EN, 0x0000);
+ generic_ocp_write(tp, 0xf800, 0xff, sizeof(usb_patch_d),
+ usb_patch_d, MCU_TYPE_USB);
+
+ for (i = 0; i < ARRAY_SIZE(r8153_usb_patch_d_bp); i += 2)
+ ocp_write_word(tp, MCU_TYPE_USB,
+ r8153_usb_patch_d_bp[i],
+ r8153_usb_patch_d_bp[i+1]);
+ }
+}
diff --git a/drivers/usb/eth/usb_ether.c b/drivers/usb/eth/usb_ether.c
index 62d20f0..b9c9a84 100644
--- a/drivers/usb/eth/usb_ether.c
+++ b/drivers/usb/eth/usb_ether.c
@@ -180,6 +180,13 @@
.get_info = smsc95xx_eth_get_info,
},
#endif
+#ifdef CONFIG_USB_ETHER_RTL8152
+ {
+ .before_probe = r8152_eth_before_probe,
+ .probe = r8152_eth_probe,
+ .get_info = r8152_eth_get_info,
+ },
+#endif
{ }, /* END */
};
diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index 9e95ecb..c6727c3 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -35,7 +35,8 @@
uint8_t *aligned_buffer;
uint8_t *status_buffer;
#endif
- int bulk_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
+ u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
+ u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
struct dwc2_core_regs *regs;
int root_hub_devnum;
};
@@ -410,19 +411,29 @@
if (dev->speed == USB_SPEED_LOW)
hcchar |= DWC2_HCCHAR_LSPDDEV;
- /* Clear old interrupt conditions for this host channel. */
- writel(0x3fff, &hc_regs->hcint);
-
/*
* Program the HCCHARn register with the endpoint characteristics
* for the current transfer.
*/
writel(hcchar, &hc_regs->hcchar);
- /* Program the HCSPLIT register for SPLITs */
+ /* Program the HCSPLIT register, default to no SPLIT */
writel(0, &hc_regs->hcsplt);
}
+static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs,
+ uint8_t hub_devnum, uint8_t hub_port)
+{
+ uint32_t hcsplt = 0;
+
+ hcsplt = DWC2_HCSPLT_SPLTENA;
+ hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET;
+ hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET;
+
+ /* Program the HCSPLIT register for SPLITs */
+ writel(hcsplt, &hc_regs->hcsplt);
+}
+
/*
* DWC2 to USB API interface
*/
@@ -713,11 +724,8 @@
return stat;
}
-int wait_for_chhltd(struct dwc2_core_regs *regs, uint32_t *sub, int *toggle,
- bool ignore_ack)
+int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle)
{
- uint32_t hcint_comp_hlt_ack = DWC2_HCINT_XFERCOMP | DWC2_HCINT_CHHLTD;
- struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL];
int ret;
uint32_t hcint, hctsiz;
@@ -727,25 +735,22 @@
return ret;
hcint = readl(&hc_regs->hcint);
- if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
- return -EAGAIN;
- if (ignore_ack)
- hcint &= ~DWC2_HCINT_ACK;
- else
- hcint_comp_hlt_ack |= DWC2_HCINT_ACK;
- if (hcint != hcint_comp_hlt_ack) {
- debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
- return -EINVAL;
- }
-
hctsiz = readl(&hc_regs->hctsiz);
*sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
DWC2_HCTSIZ_XFERSIZE_OFFSET;
*toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
- debug("%s: sub=%u toggle=%d\n", __func__, *sub, *toggle);
+ debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub,
+ *toggle);
- return 0;
+ if (hcint & DWC2_HCINT_XFERCOMP)
+ return 0;
+
+ if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
+ return -EAGAIN;
+
+ debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
+ return -EINVAL;
}
static int dwc2_eptype[] = {
@@ -755,96 +760,176 @@
DWC2_HCCHAR_EPTYPE_BULK,
};
+static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
+ u8 *pid, int in, void *buffer, int num_packets,
+ int xfer_len, int *actual_len, int odd_frame)
+{
+ int ret = 0;
+ uint32_t sub;
+
+ debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
+ *pid, xfer_len, num_packets);
+
+ writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
+ (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
+ (*pid << DWC2_HCTSIZ_PID_OFFSET),
+ &hc_regs->hctsiz);
+
+ if (!in && xfer_len) {
+ memcpy(aligned_buffer, buffer, xfer_len);
+
+ flush_dcache_range((unsigned long)aligned_buffer,
+ (unsigned long)aligned_buffer +
+ roundup(xfer_len, ARCH_DMA_MINALIGN));
+ }
+
+ writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma);
+
+ /* Clear old interrupt conditions for this host channel. */
+ writel(0x3fff, &hc_regs->hcint);
+
+ /* Set host channel enable after all other setup is complete. */
+ clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
+ DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS |
+ DWC2_HCCHAR_ODDFRM,
+ (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
+ (odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) |
+ DWC2_HCCHAR_CHEN);
+
+ ret = wait_for_chhltd(hc_regs, &sub, pid);
+ if (ret < 0)
+ return ret;
+
+ if (in) {
+ xfer_len -= sub;
+
+ invalidate_dcache_range((unsigned long)aligned_buffer,
+ (unsigned long)aligned_buffer +
+ roundup(xfer_len, ARCH_DMA_MINALIGN));
+
+ memcpy(buffer, aligned_buffer, xfer_len);
+ }
+ *actual_len = xfer_len;
+
+ return ret;
+}
+
int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
- unsigned long pipe, int *pid, int in, void *buffer, int len,
- bool ignore_ack)
+ unsigned long pipe, u8 *pid, int in, void *buffer, int len)
{
struct dwc2_core_regs *regs = priv->regs;
struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL];
+ struct dwc2_host_regs *host_regs = ®s->host_regs;
int devnum = usb_pipedevice(pipe);
int ep = usb_pipeendpoint(pipe);
int max = usb_maxpacket(dev, pipe);
int eptype = dwc2_eptype[usb_pipetype(pipe)];
int done = 0;
int ret = 0;
- uint32_t sub;
+ int do_split = 0;
+ int complete_split = 0;
uint32_t xfer_len;
uint32_t num_packets;
int stop_transfer = 0;
+ uint32_t max_xfer_len;
+ int ssplit_frame_num = 0;
debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
in, len);
- do {
- /* Initialize channel */
- dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
- eptype, max);
+ max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max;
+ if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
+ max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE;
+ if (max_xfer_len > DWC2_DATA_BUF_SIZE)
+ max_xfer_len = DWC2_DATA_BUF_SIZE;
- xfer_len = len - done;
- if (xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
- xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE - max + 1;
- if (xfer_len > DWC2_DATA_BUF_SIZE)
- xfer_len = DWC2_DATA_BUF_SIZE - max + 1;
+ /* Make sure that max_xfer_len is a multiple of max packet size. */
+ num_packets = max_xfer_len / max;
+ max_xfer_len = num_packets * max;
- /* Make sure that xfer_len is a multiple of max packet size. */
- if (xfer_len > 0) {
- num_packets = (xfer_len + max - 1) / max;
- if (num_packets > CONFIG_DWC2_MAX_PACKET_COUNT) {
- num_packets = CONFIG_DWC2_MAX_PACKET_COUNT;
- xfer_len = num_packets * max;
- }
- } else {
+ /* Initialize channel */
+ dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
+ eptype, max);
+
+ /* Check if the target is a FS/LS device behind a HS hub */
+ if (dev->speed != USB_SPEED_HIGH) {
+ uint8_t hub_addr;
+ uint8_t hub_port;
+ uint32_t hprt0 = readl(®s->hprt0);
+ if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
+ DWC2_HPRT0_PRTSPD_HIGH) {
+ usb_find_usb2_hub_address_port(dev, &hub_addr,
+ &hub_port);
+ dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port);
+
+ do_split = 1;
num_packets = 1;
+ max_xfer_len = max;
+ }
+ }
+
+ do {
+ int actual_len = 0;
+ uint32_t hcint;
+ int odd_frame = 0;
+ xfer_len = len - done;
+
+ if (xfer_len > max_xfer_len)
+ xfer_len = max_xfer_len;
+ else if (xfer_len > max)
+ num_packets = (xfer_len + max - 1) / max;
+ else
+ num_packets = 1;
+
+ if (complete_split)
+ setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
+ else if (do_split)
+ clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
+
+ if (eptype == DWC2_HCCHAR_EPTYPE_INTR) {
+ int uframe_num = readl(&host_regs->hfnum);
+ if (!(uframe_num & 0x1))
+ odd_frame = 1;
}
- if (in)
- xfer_len = num_packets * max;
+ ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid,
+ in, (char *)buffer + done, num_packets,
+ xfer_len, &actual_len, odd_frame);
- debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
- *pid, xfer_len, num_packets);
-
- writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
- (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
- (*pid << DWC2_HCTSIZ_PID_OFFSET),
- &hc_regs->hctsiz);
-
- if (!in && xfer_len) {
- memcpy(priv->aligned_buffer, (char *)buffer + done,
- xfer_len);
-
- flush_dcache_range((unsigned long)priv->aligned_buffer,
- (unsigned long)((void *)priv->aligned_buffer +
- roundup(xfer_len, ARCH_DMA_MINALIGN)));
+ hcint = readl(&hc_regs->hcint);
+ if (complete_split) {
+ stop_transfer = 0;
+ if (hcint & DWC2_HCINT_NYET) {
+ ret = 0;
+ int frame_num = DWC2_HFNUM_MAX_FRNUM &
+ readl(&host_regs->hfnum);
+ if (((frame_num - ssplit_frame_num) &
+ DWC2_HFNUM_MAX_FRNUM) > 4)
+ ret = -EAGAIN;
+ } else
+ complete_split = 0;
+ } else if (do_split) {
+ if (hcint & DWC2_HCINT_ACK) {
+ ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM &
+ readl(&host_regs->hfnum);
+ ret = 0;
+ complete_split = 1;
+ }
}
- writel(phys_to_bus((unsigned long)priv->aligned_buffer),
- &hc_regs->hcdma);
-
- /* Set host channel enable after all other setup is complete. */
- clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
- DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS,
- (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
- DWC2_HCCHAR_CHEN);
-
- ret = wait_for_chhltd(regs, &sub, pid, ignore_ack);
if (ret)
break;
- if (in) {
- xfer_len -= sub;
+ if (actual_len < xfer_len)
+ stop_transfer = 1;
- invalidate_dcache_range((unsigned long)priv->aligned_buffer,
- (unsigned long)((void *)priv->aligned_buffer +
- roundup(xfer_len, ARCH_DMA_MINALIGN)));
+ done += actual_len;
- memcpy(buffer + done, priv->aligned_buffer, xfer_len);
- if (sub)
- stop_transfer = 1;
- }
-
- done += xfer_len;
-
- } while ((done < len) && !stop_transfer);
+ /* Transactions are done when when either all data is transferred or
+ * there is a short transfer. In case of a SPLIT make sure the CSPLIT
+ * is executed.
+ */
+ } while (((done < len) && !stop_transfer) || complete_split);
writel(0, &hc_regs->hcintmsk);
writel(0xFFFFFFFF, &hc_regs->hcint);
@@ -861,14 +946,19 @@
{
int devnum = usb_pipedevice(pipe);
int ep = usb_pipeendpoint(pipe);
+ u8* pid;
- if (devnum == priv->root_hub_devnum) {
+ if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) {
dev->status = 0;
return -EINVAL;
}
- return chunk_msg(priv, dev, pipe, &priv->bulk_data_toggle[devnum][ep],
- usb_pipein(pipe), buffer, len, true);
+ if (usb_pipein(pipe))
+ pid = &priv->in_data_toggle[devnum][ep];
+ else
+ pid = &priv->out_data_toggle[devnum][ep];
+
+ return chunk_msg(priv, dev, pipe, pid, usb_pipein(pipe), buffer, len);
}
static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
@@ -876,7 +966,8 @@
struct devrequest *setup)
{
int devnum = usb_pipedevice(pipe);
- int pid, ret, act_len;
+ int ret, act_len;
+ u8 pid;
/* For CONTROL endpoint pid should start with DATA1 */
int status_direction;
@@ -887,31 +978,39 @@
setup);
}
+ /* SETUP stage */
pid = DWC2_HC_PID_SETUP;
- ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8, true);
+ do {
+ ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8);
+ } while (ret == -EAGAIN);
if (ret)
return ret;
+ /* DATA stage */
+ act_len = 0;
if (buffer) {
pid = DWC2_HC_PID_DATA1;
- ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe), buffer,
- len, false);
+ do {
+ ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe),
+ buffer, len);
+ act_len += dev->act_len;
+ buffer += dev->act_len;
+ len -= dev->act_len;
+ } while (ret == -EAGAIN);
if (ret)
return ret;
- act_len = dev->act_len;
- } /* End of DATA stage */
- else
- act_len = 0;
+ status_direction = usb_pipeout(pipe);
+ } else {
+ /* No-data CONTROL always ends with an IN transaction */
+ status_direction = 1;
+ }
/* STATUS stage */
- if ((len == 0) || usb_pipeout(pipe))
- status_direction = 1;
- else
- status_direction = 0;
-
pid = DWC2_HC_PID_DATA1;
- ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
- priv->status_buffer, 0, false);
+ do {
+ ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
+ priv->status_buffer, 0);
+ } while (ret == -EAGAIN);
if (ret)
return ret;
@@ -968,8 +1067,10 @@
DWC2_HPRT0_PRTRST);
for (i = 0; i < MAX_DEVICE; i++) {
- for (j = 0; j < MAX_ENDPOINT; j++)
- priv->bulk_data_toggle[i][j] = DWC2_HC_PID_DATA0;
+ for (j = 0; j < MAX_ENDPOINT; j++) {
+ priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0;
+ priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0;
+ }
}
return 0;
diff --git a/drivers/usb/host/dwc2.h b/drivers/usb/host/dwc2.h
index f69372e..594757b 100644
--- a/drivers/usb/host/dwc2.h
+++ b/drivers/usb/host/dwc2.h
@@ -500,6 +500,7 @@
#define DWC2_HFNUM_FRNUM_OFFSET 0
#define DWC2_HFNUM_FRREM_MASK (0xFFFF << 16)
#define DWC2_HFNUM_FRREM_OFFSET 16
+#define DWC2_HFNUM_MAX_FRNUM 0x3FFF
#define DWC2_HPTXSTS_PTXFSPCAVAIL_MASK (0xFFFF << 0)
#define DWC2_HPTXSTS_PTXFSPCAVAIL_OFFSET 0
#define DWC2_HPTXSTS_PTXQSPCAVAIL_MASK (0xFF << 16)
diff --git a/drivers/usb/host/ehci-generic.c b/drivers/usb/host/ehci-generic.c
index 1292caa..84114c5 100644
--- a/drivers/usb/host/ehci-generic.c
+++ b/drivers/usb/host/ehci-generic.c
@@ -5,6 +5,7 @@
*/
#include <common.h>
+#include <clk.h>
#include <dm.h>
#include "ehci.h"
@@ -21,6 +22,19 @@
{
struct ehci_hccr *hccr = (struct ehci_hccr *)dev_get_addr(dev);
struct ehci_hcor *hcor;
+ int i;
+
+ for (i = 0; ; i++) {
+ struct udevice *clk_dev;
+ int clk_id;
+
+ clk_id = clk_get_by_index(dev, i, &clk_dev);
+ if (clk_id < 0)
+ break;
+ if (clk_enable(clk_dev, clk_id))
+ printf("failed to enable clock (dev=%s, id=%d)\n",
+ clk_dev->name, clk_id);
+ }
hcor = (struct ehci_hcor *)((uintptr_t)hccr +
HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 912e397..f54631c 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -293,10 +293,25 @@
option takes a string in the format understood by 'name_to_gpio'
function, e.g. PH1 for pin 1 of port H.
+config VIDEO_MVEBU
+ bool "Armada XP LCD controller"
+ default n
+ ---help---
+ Support for the LCD controller integrated in the Marvell
+ Armada XP SoC.
+
+config I2C_EDID
+ bool "Enable EDID library"
+ depends on DM_I2C
+ default n
+ help
+ This enables library for accessing EDID data from an LCD panel.
+
config DISPLAY
bool "Enable Display support"
depends on DM
- default y
+ default n
+ select I2C_EDID
help
This supports drivers that provide a display, such as eDP (Embedded
DisplayPort) and HDMI (High Definition Multimedia Interface).
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 0910510..be908f6 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -47,6 +47,7 @@
obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
+obj-$(CONFIG_VIDEO_MVEBU) += mvebu_lcd.o
obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o
obj-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o
obj-$(CONFIG_VIDEO_SANDBOX_SDL) += sandbox_sdl.o
diff --git a/drivers/video/mvebu_lcd.c b/drivers/video/mvebu_lcd.c
new file mode 100644
index 0000000..86dae52
--- /dev/null
+++ b/drivers/video/mvebu_lcd.c
@@ -0,0 +1,532 @@
+/*
+ * Video driver for Marvell Armada XP SoC
+ *
+ * Initialization of LCD interface and setup of SPLASH screen image
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <video_fb.h>
+#include <linux/mbus.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+#define MVEBU_LCD_WIN_CONTROL(w) (MVEBU_LCD_BASE + 0xf000 + ((w) << 4))
+#define MVEBU_LCD_WIN_BASE(w) (MVEBU_LCD_BASE + 0xf004 + ((w) << 4))
+#define MVEBU_LCD_WIN_REMAP(w) (MVEBU_LCD_BASE + 0xf00c + ((w) << 4))
+
+#define MVEBU_LCD_CFG_DMA_START_ADDR_0 (MVEBU_LCD_BASE + 0x00cc)
+#define MVEBU_LCD_CFG_DMA_START_ADDR_1 (MVEBU_LCD_BASE + 0x00dc)
+
+#define MVEBU_LCD_CFG_GRA_START_ADDR0 (MVEBU_LCD_BASE + 0x00f4)
+#define MVEBU_LCD_CFG_GRA_START_ADDR1 (MVEBU_LCD_BASE + 0x00f8)
+#define MVEBU_LCD_CFG_GRA_PITCH (MVEBU_LCD_BASE + 0x00fc)
+#define MVEBU_LCD_SPU_GRA_OVSA_HPXL_VLN (MVEBU_LCD_BASE + 0x0100)
+#define MVEBU_LCD_SPU_GRA_HPXL_VLN (MVEBU_LCD_BASE + 0x0104)
+#define MVEBU_LCD_SPU_GZM_HPXL_VLN (MVEBU_LCD_BASE + 0x0108)
+#define MVEBU_LCD_SPU_HWC_OVSA_HPXL_VLN (MVEBU_LCD_BASE + 0x010c)
+#define MVEBU_LCD_SPU_HWC_HPXL_VLN (MVEBU_LCD_BASE + 0x0110)
+#define MVEBU_LCD_SPUT_V_H_TOTAL (MVEBU_LCD_BASE + 0x0114)
+#define MVEBU_LCD_SPU_V_H_ACTIVE (MVEBU_LCD_BASE + 0x0118)
+#define MVEBU_LCD_SPU_H_PORCH (MVEBU_LCD_BASE + 0x011c)
+#define MVEBU_LCD_SPU_V_PORCH (MVEBU_LCD_BASE + 0x0120)
+#define MVEBU_LCD_SPU_BLANKCOLOR (MVEBU_LCD_BASE + 0x0124)
+#define MVEBU_LCD_SPU_ALPHA_COLOR1 (MVEBU_LCD_BASE + 0x0128)
+#define MVEBU_LCD_SPU_ALPHA_COLOR2 (MVEBU_LCD_BASE + 0x012c)
+#define MVEBU_LCD_SPU_COLORKEY_Y (MVEBU_LCD_BASE + 0x0130)
+#define MVEBU_LCD_SPU_COLORKEY_U (MVEBU_LCD_BASE + 0x0134)
+#define MVEBU_LCD_SPU_COLORKEY_V (MVEBU_LCD_BASE + 0x0138)
+#define MVEBU_LCD_CFG_RDREG4F (MVEBU_LCD_BASE + 0x013c)
+#define MVEBU_LCD_SPU_SPI_RXDATA (MVEBU_LCD_BASE + 0x0140)
+#define MVEBU_LCD_SPU_ISA_RXDATA (MVEBU_LCD_BASE + 0x0144)
+#define MVEBU_LCD_SPU_DBG_ISA (MVEBU_LCD_BASE + 0x0148)
+
+#define MVEBU_LCD_SPU_HWC_RDDAT (MVEBU_LCD_BASE + 0x0158)
+#define MVEBU_LCD_SPU_GAMMA_RDDAT (MVEBU_LCD_BASE + 0x015c)
+#define MVEBU_LCD_SPU_PALETTE_RDDAT (MVEBU_LCD_BASE + 0x0160)
+#define MVEBU_LCD_SPU_IOPAD_IN (MVEBU_LCD_BASE + 0x0178)
+#define MVEBU_LCD_FRAME_COUNT (MVEBU_LCD_BASE + 0x017c)
+#define MVEBU_LCD_SPU_DMA_CTRL0 (MVEBU_LCD_BASE + 0x0190)
+#define MVEBU_LCD_SPU_DMA_CTRL1 (MVEBU_LCD_BASE + 0x0194)
+#define MVEBU_LCD_SPU_SRAM_CTRL (MVEBU_LCD_BASE + 0x0198)
+#define MVEBU_LCD_SPU_SRAM_WRDAT (MVEBU_LCD_BASE + 0x019c)
+#define MVEBU_LCD_SPU_SRAM_PARA0 (MVEBU_LCD_BASE + 0x01a0)
+#define MVEBU_LCD_SPU_SRAM_PARA1 (MVEBU_LCD_BASE + 0x01a4)
+#define MVEBU_LCD_CFG_SCLK_DIV (MVEBU_LCD_BASE + 0x01a8)
+#define MVEBU_LCD_SPU_CONTRAST (MVEBU_LCD_BASE + 0x01ac)
+#define MVEBU_LCD_SPU_SATURATION (MVEBU_LCD_BASE + 0x01b0)
+#define MVEBU_LCD_SPU_CBSH_HUE (MVEBU_LCD_BASE + 0x01b4)
+#define MVEBU_LCD_SPU_DUMB_CTRL (MVEBU_LCD_BASE + 0x01b8)
+#define MVEBU_LCD_SPU_IOPAD_CONTROL (MVEBU_LCD_BASE + 0x01bc)
+#define MVEBU_LCD_SPU_IRQ_ENA_2 (MVEBU_LCD_BASE + 0x01d8)
+#define MVEBU_LCD_SPU_IRQ_ISR_2 (MVEBU_LCD_BASE + 0x01dc)
+#define MVEBU_LCD_SPU_IRQ_ENA (MVEBU_LCD_BASE + 0x01c0)
+#define MVEBU_LCD_SPU_IRQ_ISR (MVEBU_LCD_BASE + 0x01c4)
+#define MVEBU_LCD_ADLL_CTRL (MVEBU_LCD_BASE + 0x01c8)
+#define MVEBU_LCD_CLK_DIS (MVEBU_LCD_BASE + 0x01cc)
+#define MVEBU_LCD_VGA_HVSYNC_DELAY (MVEBU_LCD_BASE + 0x01d4)
+#define MVEBU_LCD_CLK_CFG_0 (MVEBU_LCD_BASE + 0xf0a0)
+#define MVEBU_LCD_CLK_CFG_1 (MVEBU_LCD_BASE + 0xf0a4)
+#define MVEBU_LCD_LVDS_CLK_CFG (MVEBU_LCD_BASE + 0xf0ac)
+
+#define MVEBU_LVDS_PADS_REG (MVEBU_SYSTEM_REG_BASE + 0xf0)
+
+/* Setup Mbus Bridge Windows for LCD */
+static void mvebu_lcd_conf_mbus_registers(void)
+{
+ const struct mbus_dram_target_info *dram;
+ int i;
+
+ dram = mvebu_mbus_dram_info();
+
+ /* Disable windows, set size/base/remap to 0 */
+ for (i = 0; i < 6; i++) {
+ writel(0, MVEBU_LCD_WIN_CONTROL(i));
+ writel(0, MVEBU_LCD_WIN_BASE(i));
+ writel(0, MVEBU_LCD_WIN_REMAP(i));
+ }
+
+ /* Write LCD bridge window registers */
+ for (i = 0; i < dram->num_cs; i++) {
+ const struct mbus_dram_window *cs = dram->cs + i;
+ writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
+ (dram->mbus_dram_target_id << 4) | 1,
+ MVEBU_LCD_WIN_CONTROL(i));
+
+ writel(cs->base & 0xffff0000, MVEBU_LCD_WIN_BASE(i));
+ }
+}
+
+/* Initialize LCD registers */
+int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info)
+{
+ /* Local variable for easier handling */
+ int x = lcd_info->x_res;
+ int y = lcd_info->y_res;
+ u32 val;
+
+ /* Setup Mbus Bridge Windows */
+ mvebu_lcd_conf_mbus_registers();
+
+ /*
+ * Set LVDS Pads Control Register
+ * wr 0 182F0 FFE00000
+ */
+ clrbits_le32(MVEBU_LVDS_PADS_REG, 0x1f << 16);
+
+ /*
+ * Set the LCD_CFG_GRA_START_ADDR0/1 Registers
+ * This is supposed to point to the "physical" memory at memory
+ * end (currently 1GB-64MB but also may be 2GB-64MB).
+ * See also the Window 0 settings!
+ */
+ writel(lcd_info->fb_base, MVEBU_LCD_CFG_GRA_START_ADDR0);
+ writel(lcd_info->fb_base, MVEBU_LCD_CFG_GRA_START_ADDR1);
+
+ /*
+ * Set the LCD_CFG_GRA_PITCH Register
+ * Bits 31-28: Duty Cycle of Backlight. value/16=High (0x8=Mid Setting)
+ * Bits 25-16: Backlight divider from 32kHz Clock
+ * (here 16=0x10 for 1kHz)
+ * Bits 15-00: Line Length in Bytes
+ * 240*2 (for RGB1555)=480=0x1E0
+ */
+ writel(0x80100000 + 2 * x, MVEBU_LCD_CFG_GRA_PITCH);
+
+ /*
+ * Set the LCD_SPU_GRA_OVSA_HPXL_VLN Register
+ * Bits 31-16: Vertical start of graphical overlay on screen
+ * Bits 15-00: Horizontal start of graphical overlay on screen
+ */
+ writel(0x00000000, MVEBU_LCD_SPU_GRA_OVSA_HPXL_VLN);
+
+ /*
+ * Set the LCD_SPU_GRA_HPXL_VLN Register
+ * Bits 31-16: Vertical size of graphical overlay 320=0x140
+ * Bits 15-00: Horizontal size of graphical overlay 240=0xF0
+ * Values before zooming
+ */
+ writel((y << 16) | x, MVEBU_LCD_SPU_GRA_HPXL_VLN);
+
+ /*
+ * Set the LCD_SPU_GZM_HPXL_VLN Register
+ * Bits 31-16: Vertical size of graphical overlay 320=0x140
+ * Bits 15-00: Horizontal size of graphical overlay 240=0xF0
+ * Values after zooming
+ */
+ writel((y << 16) | x, MVEBU_LCD_SPU_GZM_HPXL_VLN);
+
+ /*
+ * Set the LCD_SPU_HWC_OVSA_HPXL_VLN Register
+ * Bits 31-16: Vertical position of HW Cursor 320=0x140
+ * Bits 15-00: Horizontal position of HW Cursor 240=0xF0
+ */
+ writel((y << 16) | x, MVEBU_LCD_SPU_HWC_OVSA_HPXL_VLN);
+
+ /*
+ * Set the LCD_SPU_HWC_OVSA_HPXL_VLN Register
+ * Bits 31-16: Vertical size of HW Cursor
+ * Bits 15-00: Horizontal size of HW Cursor
+ */
+ writel(0x00000000, MVEBU_LCD_SPU_HWC_HPXL_VLN);
+
+ /*
+ * Set the LCD_SPU_HWC_OVSA_HPXL_VLN Register
+ * Bits 31-16: Screen total vertical lines:
+ * VSYNC = 1
+ * Vertical Front Porch = 2
+ * Vertical Lines = 320
+ * Vertical Back Porch = 2
+ * SUM = 325 = 0x0145
+ * Bits 15-00: Screen total horizontal pixels:
+ * HSYNC = 1
+ * Horizontal Front Porch = 44
+ * Horizontal Lines = 240
+ * Horizontal Back Porch = 2
+ * SUM = 287 = 0x011F
+ * Note: For the display the backporch is between SYNC and
+ * the start of the pixels.
+ * This is not certain for the Marvell (!?)
+ */
+ val = ((y + lcd_info->y_fp + lcd_info->y_bp + 1) << 16) |
+ (x + lcd_info->x_fp + lcd_info->x_bp + 1);
+ writel(val, MVEBU_LCD_SPUT_V_H_TOTAL);
+
+ /*
+ * Set the LCD_SPU_V_H_ACTIVE Register
+ * Bits 31-16: Screen active vertical lines 320=0x140
+ * Bits 15-00: Screen active horizontakl pixels 240=0x00F0
+ */
+ writel((y << 16) | x, MVEBU_LCD_SPU_V_H_ACTIVE);
+
+ /*
+ * Set the LCD_SPU_H_PORCH Register
+ * Bits 31-16: Screen horizontal backporch 44=0x2c
+ * Bits 15-00: Screen horizontal frontporch 2=0x02
+ * Note: The terms "front" and "back" for the Marvell seem to be
+ * exactly opposite to the display.
+ */
+ writel((lcd_info->x_fp << 16) | lcd_info->x_bp, MVEBU_LCD_SPU_H_PORCH);
+
+ /*
+ * Set the LCD_SPU_V_PORCH Register
+ * Bits 31-16: Screen vertical backporch 2=0x02
+ * Bits 15-00: Screen vertical frontporch 2=0x02
+ * Note: The terms "front" and "back" for the Marvell seem to be exactly
+ * opposite to the display.
+ */
+ writel((lcd_info->y_fp << 16) | lcd_info->y_bp, MVEBU_LCD_SPU_V_PORCH);
+
+ /*
+ * Set the LCD_SPU_BLANKCOLOR Register
+ * This should be black = 0
+ * For tests this is magenta=00FF00FF
+ */
+ writel(0x00FF00FF, MVEBU_LCD_SPU_BLANKCOLOR);
+
+ /*
+ * Registers in the range of 0x0128 to 0x012C are colors for the cursor
+ * Registers in the range of 0x0130 to 0x0138 are colors for video
+ * color keying
+ */
+
+ /*
+ * Set the LCD_SPU_RDREG4F Register
+ * Bits 31-12: Reservd
+ * Bit 11: SRAM Wait
+ * Bit 10: Smart display fast TX (must be 1)
+ * Bit 9: DMA Arbitration Video/Graphics overlay: 0=interleaved
+ * Bit 8: FIFO watermark for DMA: 0=disable
+ * Bits 07-00: Empty 8B FIFO entries to trigger DMA, default=0x80
+ */
+ writel(0x00000780, MVEBU_LCD_CFG_RDREG4F);
+
+ /*
+ * Set the LCD_SPU_DMACTRL 0 Register
+ * Bit 31: Disable overlay blending 1=disable
+ * Bit 30: Gamma correction enable, 0=disable
+ * Bit 29: Video Contrast/Saturation/Hue Adjust enable, 0=disable
+ * Bit 28: Color palette enable, 0=disable
+ * Bit 27: DMA AXI Arbiter, 1=default
+ * Bit 26: HW Cursor 1-bit mode
+ * Bit 25: HW Cursor or 1- or 2-bit mode
+ * Bit 24: HW Cursor enabled, 0=disable
+ * Bits 23-20: Graphics Memory Color Format: 0x1=RGB1555
+ * Bits 19-16: Video Memory Color Format: 0x1=RGB1555
+ * Bit 15: Memory Toggle between frame 0 and 1: 0=disable
+ * Bit 14: Graphics horizontal scaling enable: 0=disable
+ * Bit 13: Graphics test mode: 0=disable
+ * Bit 12: Graphics SWAP R and B: 0=disable
+ * Bit 11: Graphics SWAP U and V: 0=disable
+ * Bit 10: Graphics SWAP Y and U/V: 0=disable
+ * Bit 09: Graphic YUV to RGB Conversion: 0=disable
+ * Bit 08: Graphic Transfer: 1=enable
+ * Bit 07: Memory Toggle: 0=disable
+ * Bit 06: Video horizontal scaling enable: 0=disable
+ * Bit 05: Video test mode: 0=disable
+ * Bit 04: Video SWAP R and B: 0=disable
+ * Bit 03: Video SWAP U and V: 0=disable
+ * Bit 02: Video SWAP Y and U/V: 0=disable
+ * Bit 01: Video YUV to RGB Conversion: 0=disable
+ * Bit 00: Video Transfer: 0=disable
+ */
+ writel(0x88111100, MVEBU_LCD_SPU_DMA_CTRL0);
+
+ /*
+ * Set the LCD_SPU_DMA_CTRL1 Register
+ * Bit 31: Manual DMA Trigger = 0
+ * Bits 30-28: DMA Trigger Source: 0x2 VSYNC
+ * Bit 28: VSYNC_INV: 0=Rising Edge, 1=Falling Edge
+ * Bits 26-24: Color Key Mode: 0=disable
+ * Bit 23: Fill low bits: 0=fill with zeroes
+ * Bit 22: Reserved
+ * Bit 21: Gated Clock: 0=disable
+ * Bit 20: Power Save enable: 0=disable
+ * Bits 19-18: Reserved
+ * Bits 17-16: Configure Video/Graphic Path: 0x1: Graphic path alpha.
+ * Bits 15-08: Configure Alpha: 0x00.
+ * Bits 07-00: Reserved.
+ */
+ writel(0x20010000, MVEBU_LCD_SPU_DMA_CTRL1);
+
+ /*
+ * Set the LCD_SPU_SRAM_CTRL Register
+ * Reset to default = 0000C000
+ * Bits 15-14: SRAM control: init=0x3, Read=0, Write=2
+ * Bits 11-08: SRAM address ID: 0=gamma_yr, 1=gammy_ug, 2=gamma_vb,
+ * 3=palette, 15=cursor
+ */
+ writel(0x0000C000, MVEBU_LCD_SPU_SRAM_CTRL);
+
+ /*
+ * LCD_SPU_SRAM_WRDAT register: 019C
+ * LCD_SPU_SRAM_PARA0 register: 01A0
+ * LCD_SPU_SRAM_PARA1 register: 01A4 - Cursor control/Power settings
+ */
+ writel(0x00000000, MVEBU_LCD_SPU_SRAM_PARA1);
+
+
+ /* Clock settings in the at 01A8 and in the range F0A0 see below */
+
+ /*
+ * Set LCD_SPU_CONTRAST
+ * Bits 31-16: Brightness sign ext. 8-bit value +255 to -255: default=0
+ * Bits 15-00: Contrast sign ext. 8-bit value +255 to -255: default=0
+ */
+ writel(0x00000000, MVEBU_LCD_SPU_CONTRAST);
+
+ /*
+ * Set LCD_SPU_SATURATION
+ * Bits 31-16: Multiplier signed 4.12 fixed point value
+ * Bits 15-00: Saturation signed 4.12 fixed point value
+ */
+ writel(0x10001000, MVEBU_LCD_SPU_SATURATION);
+
+ /*
+ * Set LCD_SPU_HUE
+ * Bits 31-16: Sine signed 2.14 fixed point value
+ * Bits 15-00: Cosine signed 2.14 fixed point value
+ */
+ writel(0x00000000, MVEBU_LCD_SPU_CBSH_HUE);
+
+ /*
+ * Set LCD_SPU_DUMB_CTRL
+ * Bits 31-28: LCD Type: 3=18 bit RGB | 6=24 bit RGB888
+ * Bits 27-12: Reserved
+ * Bit 11: LCD DMA Pipeline Enable: 1=Enable
+ * Bits 10-09: Reserved
+ * Bit 8: LCD GPIO pin (??)
+ * Bit 7: Reverse RGB
+ * Bit 6: Invert composite blank signal DE/EN (??)
+ * Bit 5: Invert composite sync signal
+ * Bit 4: Invert Pixel Valid Enable DE/EN (??)
+ * Bit 3: Invert VSYNC
+ * Bit 2: Invert HSYNC
+ * Bit 1: Invert Pixel Clock
+ * Bit 0: Enable LCD Panel: 1=Enable
+ * Question: Do we have to disable Smart and Dumb LCD
+ * and separately enable LVDS?
+ */
+ writel(0x6000080F, MVEBU_LCD_SPU_DUMB_CTRL);
+
+ /*
+ * Set LCD_SPU_IOPAD_CTRL
+ * Bits 31-20: Reserved
+ * Bits 19-18: Vertical Interpolation: 0=Disable
+ * Bits 17-16: Reserved
+ * Bit 15: Graphics Vertical Mirror enable: 0=disable
+ * Bit 14: Reserved
+ * Bit 13: Video Vertical Mirror enable: 0=disable
+ * Bit 12: Reserved
+ * Bit 11: Command Vertical Mirror enable: 0=disable
+ * Bit 10: Reserved
+ * Bits 09-08: YUV to RGB Color space conversion: 0 (Not used)
+ * Bits 07-04: AXI Bus Master: 0x4: no crossing of 4k boundary,
+ * 128 Bytes burst
+ * Bits 03-00: LCD pins: ??? 0=24-bit Dump panel ??
+ */
+ writel(0x000000C0, MVEBU_LCD_SPU_IOPAD_CONTROL);
+
+ /*
+ * Set SUP_IRQ_ENA_2: Disable all interrupts
+ */
+ writel(0x00000000, MVEBU_LCD_SPU_IRQ_ENA_2);
+
+ /*
+ * Set SUP_IRQ_ENA: Disable all interrupts.
+ */
+ writel(0x00000000, MVEBU_LCD_SPU_IRQ_ENA);
+
+ /*
+ * Set up ADDL Control Register
+ * Bits 31-29: 0x0 = Fastest Delay Line (default)
+ * 0x3 = Slowest Delay Line (default)
+ * Bit 28: Calibration done status.
+ * Bit 27: Reserved
+ * Bit 26: Set Pixel Clock to ADDL output
+ * Bit 25: Reduce CAL Enable
+ * Bits 24-22: Manual calibration value.
+ * Bit 21: Manual calibration enable.
+ * Bit 20: Restart Auto Cal
+ * Bits 19-16: Calibration Threshold voltage, default= 0x2
+ * Bite 15-14: Reserved
+ * Bits 13-11: Divisor for ADDL Clock: 0x1=/2, 0x3=/8, 0x5=/16
+ * Bit 10: Power Down ADDL module, default = 1!
+ * Bits 09-08: Test point configuration: 0x2=Bias, 0x3=High-z
+ * Bit 07: Reset ADDL
+ * Bit 06: Invert ADLL Clock
+ * Bits 05-00: Delay taps, 0x3F=Half Cycle, 0x00=No delay
+ * Note: ADLL is used for a VGA interface with DAC - not used here
+ */
+ writel(0x00000000, MVEBU_LCD_ADLL_CTRL);
+
+ /*
+ * Set the LCD_CLK_DIS Register:
+ * Bits 3 and 4 must be 1
+ */
+ writel(0x00000018, MVEBU_LCD_CLK_DIS);
+
+ /*
+ * Set the LCD_VGA_HSYNC/VSYNC Delay Register:
+ * Bits 03-00: Sets the delay for the HSYNC and VSYNC signals
+ */
+ writel(0x00000000, MVEBU_LCD_VGA_HVSYNC_DELAY);
+
+ /*
+ * Clock registers
+ * See page 475 in the functional spec.
+ */
+
+ /* Step 1 and 2: Disable the PLL */
+
+ /*
+ * Disable PLL, see "LCD Clock Configuration 1 Register" below
+ */
+ writel(0x8FF40007, MVEBU_LCD_CLK_CFG_1);
+
+ /*
+ * Powerdown, see "LCD Clock Configuration 0 Register" below
+ */
+ writel(0x94000174, MVEBU_LCD_CLK_CFG_0);
+
+ /*
+ * Set the LCD_CFG_SCLK_DIV Register
+ * This is set fix to 0x40000001 for the LVDS output:
+ * Bits 31-30: SCLCK Source: 0=AXIBus, 1=AHBus, 2=PLLDivider0
+ * Bits 15-01: Clock Divider: Bypass for LVDS=0x0001
+ * See page 475 in section 28.5.
+ */
+ writel(0x80000001, MVEBU_LCD_CFG_SCLK_DIV);
+
+ /*
+ * Set the LCD Clock Configuration 0 Register:
+ * Bit 31: Powerdown: 0=Power up
+ * Bits 30-29: Reserved
+ * Bits 28-26: PLL_KDIV: This encodes K
+ * K=16 => 0x5
+ * Bits 25-17: PLL_MDIV: This is M-1:
+ * M=1 => 0x0
+ * Bits 16-13: VCO band: 0x1 for 700-920MHz
+ * Bits 12-04: PLL_NDIV: This is N-1 and corresponds to R1_CTRL!
+ * N=28=0x1C => 0x1B
+ * Bits 03-00: R1_CTRL (for N=28 => 0x4)
+ */
+ writel(0x940021B4, MVEBU_LCD_CLK_CFG_0);
+
+ /*
+ * Set the LCD Clock Configuration 1 Register:
+ * Bits 31-19: Reserved
+ * Bit 18: Select PLL: Core PLL, 1=Dedicated PPL
+ * Bit 17: Clock Output Enable: 0=disable, 1=enable
+ * Bit 16: Select RefClk: 0=RefClk (25MHz), 1=External
+ * Bit 15: Half-Div, Device Clock by DIV+0.5*Half-Dev
+ * Bits 14-13: Reserved
+ * Bits 12-00: PLL Full Divider [Note: Assumed to be the Post-Divider
+ * M' for LVDS=7!]
+ */
+ writel(0x8FF40007, MVEBU_LCD_CLK_CFG_1);
+
+ /*
+ * Set the LVDS Clock Configuration Register:
+ * Bit 31: Clock Gating for the input clock to the LVDS
+ * Bit 30: LVDS Serializer enable: 1=Enabled
+ * Bits 29-11: Reserved
+ * Bit 11-08: LVDS Clock delay: 0x02 (default): by 2 pixel clock/7
+ * Bits 07-02: Reserved
+ * Bit 01: 24bbp Option: 0=Option_1,1=Option2
+ * Bit 00: 1=24bbp Panel: 0=18bpp Panel
+ * Note: Bits 0 and must be verified with the help of the
+ * Interface/display
+ */
+ writel(0xC0000201, MVEBU_LCD_LVDS_CLK_CFG);
+
+ /*
+ * Power up PLL (Clock Config 0)
+ */
+ writel(0x140021B4, MVEBU_LCD_CLK_CFG_0);
+
+ /* wait 10 ms */
+ mdelay(10);
+
+ /*
+ * Enable PLL (Clock Config 1)
+ */
+ writel(0x8FF60007, MVEBU_LCD_CLK_CFG_1);
+
+ return 0;
+}
+
+int __weak board_video_init(void)
+{
+ return -1;
+}
+
+void *video_hw_init(void)
+{
+ static GraphicDevice mvebufb;
+ GraphicDevice *pGD = &mvebufb;
+ u32 val;
+
+ /*
+ * The board code needs to call mvebu_lcd_register_init()
+ * in its board_video_init() implementation, with the board
+ * specific parameters for its LCD.
+ */
+ if (board_video_init() || !readl(MVEBU_LCD_CFG_GRA_START_ADDR0))
+ return NULL;
+
+ /* Provide the necessary values for the U-Boot video IF */
+ val = readl(MVEBU_LCD_SPU_V_H_ACTIVE);
+ pGD->winSizeY = val >> 16;
+ pGD->winSizeX = val & 0x0000ffff;
+ pGD->gdfBytesPP = 2;
+ pGD->gdfIndex = GDF_15BIT_555RGB;
+ pGD->frameAdrs = readl(MVEBU_LCD_CFG_GRA_START_ADDR0);
+
+ debug("LCD: buffer at 0x%08x resolution %dx%d\n", pGD->frameAdrs,
+ pGD->winSizeX, pGD->winSizeY);
+
+ return pGD;
+}
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index 73279c8..4a17f41 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -606,6 +606,16 @@
#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
+#define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv"
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_VID
+#endif
+#define CONFIG_VOL_MONITOR_IR36021_SET
+#define CONFIG_VOL_MONITOR_IR36021_READ
+/* The lowest and highest voltage allowed for T4240RDB */
+#define VDD_MV_MIN 819
+#define VDD_MV_MAX 1212
+
/*
* eSPI - Enhanced SPI
*/
diff --git a/include/configs/chromebook_jerry.h b/include/configs/chromebook_jerry.h
index 150e876..67f45c0 100644
--- a/include/configs/chromebook_jerry.h
+++ b/include/configs/chromebook_jerry.h
@@ -30,7 +30,6 @@
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_I2C_EDID
#define CONFIG_SYS_WHITE_ON_BLACK
#define CONFIG_CONSOLE_SCROLL_LINES 10
diff --git a/include/configs/firefly-rk3288.h b/include/configs/firefly-rk3288.h
index d6423e7..a29f557 100644
--- a/include/configs/firefly-rk3288.h
+++ b/include/configs/firefly-rk3288.h
@@ -24,7 +24,6 @@
*/
#define CONFIG_ENV_OFFSET (96 * 1024)
-#define CONFIG_I2C_EDID
#define CONFIG_SYS_WHITE_ON_BLACK
#define CONFIG_CONSOLE_SCROLL_LINES 10
diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h
index 9464153..176f6e9 100644
--- a/include/configs/nyan-big.h
+++ b/include/configs/nyan-big.h
@@ -37,8 +37,6 @@
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
-#define CONFIG_I2C_EDID
-
/* LCD support */
#define CONFIG_LCD
#define CONFIG_PWM_TEGRA
diff --git a/include/configs/rock2.h b/include/configs/rock2.h
index d6423e7..a29f557 100644
--- a/include/configs/rock2.h
+++ b/include/configs/rock2.h
@@ -24,7 +24,6 @@
*/
#define CONFIG_ENV_OFFSET (96 * 1024)
-#define CONFIG_I2C_EDID
#define CONFIG_SYS_WHITE_ON_BLACK
#define CONFIG_CONSOLE_SCROLL_LINES 10
diff --git a/include/configs/rpi-common.h b/include/configs/rpi-common.h
index 1b83eb3..927bae7 100644
--- a/include/configs/rpi-common.h
+++ b/include/configs/rpi-common.h
@@ -88,6 +88,9 @@
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_SMSC95XX
#define CONFIG_MISC_INIT_R
+#define CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_USB_EVENT_POLL
+#define CONFIG_SYS_STDIO_DEREGISTER
#endif
/* Console UART */
@@ -111,6 +114,7 @@
#define CONFIG_SYS_LOAD_ADDR 0x1000000
#define CONFIG_CONSOLE_MUX
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_PREBOOT "usb start"
/* Shell */
#define CONFIG_SYS_MAXARGS 8
@@ -133,7 +137,7 @@
/* Environment */
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define ENV_DEVICE_SETTINGS \
- "stdin=serial,lcd\0" \
+ "stdin=serial,usbkbd\0" \
"stdout=serial,lcd\0" \
"stderr=serial,lcd\0"
diff --git a/include/lcd.h b/include/lcd.h
index d7651a8..f76fca7 100644
--- a/include/lcd.h
+++ b/include/lcd.h
@@ -195,8 +195,15 @@
#define CONSOLE_COLOR_WHITE 0x00ffffff /* Must remain last / highest */
#define NBYTES(bit_code) (NBITS(bit_code) >> 3)
#else /* 16bpp color definitions */
-#define CONSOLE_COLOR_BLACK 0x0000
-#define CONSOLE_COLOR_WHITE 0xffff /* Must remain last / highest */
+# define CONSOLE_COLOR_BLACK 0x0000
+# define CONSOLE_COLOR_RED 0xF800
+# define CONSOLE_COLOR_GREEN 0x07E0
+# define CONSOLE_COLOR_YELLOW 0xFFE0
+# define CONSOLE_COLOR_BLUE 0x001F
+# define CONSOLE_COLOR_MAGENTA 0xF81F
+# define CONSOLE_COLOR_CYAN 0x07FF
+# define CONSOLE_COLOR_GREY 0xC618
+# define CONSOLE_COLOR_WHITE 0xffff /* Must remain last / highest */
#endif /* color definitions */
#if LCD_BPP == LCD_COLOR16
diff --git a/include/usb_ether.h b/include/usb_ether.h
index c6d1416..51fce4e 100644
--- a/include/usb_ether.h
+++ b/include/usb_ether.h
@@ -131,6 +131,12 @@
struct ueth_data *ss);
int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
struct eth_device *eth);
+
+void r8152_eth_before_probe(void);
+int r8152_eth_probe(struct usb_device *dev, unsigned int ifnum,
+ struct ueth_data *ss);
+int r8152_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
+ struct eth_device *eth);
#endif
#endif /* __USB_ETHER_H__ */