riscv: cache: Add CBO instructions
Define CBO inval and flush instructions and use those for the
dcache inval and flush operations respectively.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index f4384d1..043d963 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -319,6 +319,10 @@
help
Adds "A" to the ISA string passed to the compiler.
+config RISCV_ISA_ZICBOM
+ bool "Zicbom support"
+ depends on !SYS_DISABLE_DCACHE_OPS
+
config DMA_ADDR_T_64BIT
bool
default y if 64BIT