Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-riscv into next
CI result shows no issue:
https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/22315
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- Aspeed: Add AST2700 board (Ibex RISC-V core) support
- Add timer, dram controller, network support
- Sophgo: Add clock controller support for Milk-V Duo
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index f30178a..986687e 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -32,6 +32,7 @@
#include <imx_sip.h>
#include <linux/bitops.h>
#include <linux/bitfield.h>
+#include <linux/sizes.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -206,6 +207,14 @@
int entry = imx8m_find_dram_entry_in_mem_map();
u64 attrs = imx8m_mem_map[entry].attrs;
+ /* Deactivate the data cache, possibly enabled in arch_cpu_init() */
+ dcache_disable();
+ /*
+ * Force the call of setup_all_pgtables() in mmu_setup() by clearing tlb_fillptr
+ * to update the TLB location udpated in board_f.c::reserve_mmu
+ */
+ gd->arch.tlb_fillptr = 0;
+
while (i < CONFIG_NR_DRAM_BANKS &&
entry < ARRAY_SIZE(imx8m_mem_map)) {
if (gd->bd->bi_dram[i].start == 0)
@@ -587,12 +596,50 @@
}
}
+/*
+ * Place early TLB into the .data section so that it will not
+ * get cleared, use 16 kiB alignment.
+ */
+#define EARLY_TLB_SIZE SZ_64K
+u8 early_tlb[EARLY_TLB_SIZE] __section(".data") __aligned(0x4000);
+
+/*
+ * Initialize the MMU and activate cache in U-Boot pre-reloc stage
+ * MMU/TLB is updated in enable_caches() for U-Boot after relocation
+ */
+static void early_enable_caches(void)
+{
+ phys_size_t sdram_size;
+ int entry, ret;
+
+ if (IS_ENABLED(CONFIG_SPL_BUILD))
+ return;
+
+ if (CONFIG_IS_ENABLED(SYS_ICACHE_OFF) || CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+ return;
+
+ /* Use maximum available DRAM size in first bank. */
+ ret = board_phys_sdram_size(&sdram_size);
+ if (ret)
+ return;
+
+ entry = imx8m_find_dram_entry_in_mem_map();
+ imx8m_mem_map[entry].size = max(sdram_size, (phys_size_t)0xc0000000);
+
+ gd->arch.tlb_size = EARLY_TLB_SIZE;
+ gd->arch.tlb_addr = (unsigned long)&early_tlb;
+
+ /* Enable MMU (default configuration) */
+ dcache_enable();
+}
+
int arch_cpu_init(void)
{
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
icache_enable();
+ early_enable_caches();
#endif
/*
diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig
index fc3e3ec..3633401 100644
--- a/configs/imx8mm_venice_defconfig
+++ b/configs/imx8mm_venice_defconfig
@@ -139,7 +139,6 @@
CONFIG_SPL_DM_PMIC_MP5416=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
-# CONFIG_DM_RNG is not set
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig
index 93e6a28..d2925f2 100644
--- a/configs/imx8mn_venice_defconfig
+++ b/configs/imx8mn_venice_defconfig
@@ -134,7 +134,6 @@
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
-# CONFIG_DM_RNG is not set
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig
index b08e4ae..09a8841 100644
--- a/configs/imx8mp_venice_defconfig
+++ b/configs/imx8mp_venice_defconfig
@@ -139,7 +139,6 @@
CONFIG_SPL_DM_PMIC_MP5416=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
-# CONFIG_DM_RNG is not set
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index 320ea7c..bb37b39 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -20,10 +20,11 @@
u32 cr;
writel(0, &pwm->ir);
- cr = PWMCR_PRESCALER(prescale) |
+
+ cr = readl(&pwm->cr) & PWMCR_EN;
+ cr |= PWMCR_PRESCALER(prescale) |
PWMCR_DOZEEN | PWMCR_WAITEN |
PWMCR_DBGEN | PWMCR_CLKSRC_IPG_HIGH;
-
writel(cr, &pwm->cr);
/* set duty cycles */
writel(duty_cycles, &pwm->sar);