commit 9f751551456828b2d0ff417f10959fb0c7110bd0
author TsiChung Liew <Tsi-Chung.Liew@freescale.com> Wed Jul 23 20:38:53 2008 -0500
committer John Rigby <jrigby@freescale.com> Thu Aug 14 12:31:55 2008 -0600
tree 9400ee01bbef8c6d3dde6249bda85e6fc8405c4f
parent a7323bba229203aae2604afde131ab47bad4eadc

ColdFire: Implement SBF feature for M5445EVB

Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>

cpu/mcf5445x/cpu_init.c

diff --git a/cpu/mcf5445x/cpu_init.c b/cpu/mcf5445x/cpu_init.c
index e07748b..51a9e90 100644
--- a/cpu/mcf5445x/cpu_init.c
+++ b/cpu/mcf5445x/cpu_init.c
@@ -61,11 +61,13 @@
 	    GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | GPIO_PAR_FBCTL_RW_RW |
 	    GPIO_PAR_FBCTL_TS_TS;
 
+#if !defined(CONFIG_CF_SBF)
 #if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL))
 	fbcs->csar0 = CFG_CS0_BASE;
 	fbcs->cscr0 = CFG_CS0_CTRL;
 	fbcs->csmr0 = CFG_CS0_MASK;
 #endif
+#endif
 
 #if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL))
 	/* Latch chipselect */