x86: ivybridge: Move GPIO init to the LPC init() method

This init can happen in the driver also. Move it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index c3626c4..6d3f477 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -278,10 +278,6 @@
 
 	gd->arch.pei_boot_mode = boot_mode;
 
-	/* TODO: Move this to the board or driver */
-	x86_pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
-	x86_pci_write_config32(PCH_LPC_DEV, GPIO_CNTL, 0x10);
-
 	/* Print processor name */
 	name = cpu_get_name(processor_name);
 	printf("CPU:   %s\n", name);
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index c88733d..0d85de2 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -623,6 +623,9 @@
 	setbits_le32(RCB_REG(GCS), 1 >> 5);	/* No reset */
 	outw(1 << 11, DEFAULT_PMBASE | 0x60 | 0x08);	/* halt timer */
 
+	dm_pci_write_config32(dev->parent, GPIO_BASE, DEFAULT_GPIOBASE | 1);
+	dm_pci_write_config32(dev->parent, GPIO_CNTL, 0x10);
+
 	return 0;
 }