Merge remote-tracking branch 'u-boot-sh/rmobile'
Conflicts:
boards.cfg
Trivial conflict, maintainer change plus board addition
diff --git a/arch/arm/cpu/armv7/rmobile/Makefile b/arch/arm/cpu/armv7/rmobile/Makefile
index 2221999..fad004c 100644
--- a/arch/arm/cpu/armv7/rmobile/Makefile
+++ b/arch/arm/cpu/armv7/rmobile/Makefile
@@ -11,7 +11,7 @@
obj-$(CONFIG_DISPLAY_BOARDINFO) += board.o
obj-$(CONFIG_GLOBAL_TIMER) += timer.o
obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
-obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-r8a7790.o pfc-r8a7790.o
-obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-r8a7791.o pfc-r8a7791.o
+obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7790.o
+obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7791.o
obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
obj-$(CONFIG_TMU_TIMER) += ../../../../sh/lib/time.o
diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c b/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c
deleted file mode 100644
index 7232e23..0000000
--- a/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c
- * This file is r8a7790 processor support.
- *
- * Copyright (C) 2013 Renesas Electronics Corporation
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-#include <common.h>
-#include <asm/io.h>
-
-#define PRR 0xFF000044
-
-u32 rmobile_get_cpu_type(void)
-{
- return (readl(PRR) & 0x00007F00) >> 8;
-}
-
-u32 rmobile_get_cpu_rev_integer(void)
-{
- return (readl(PRR) & 0x000000F0) >> 4;
-}
diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c b/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c
deleted file mode 100644
index 2de58ed..0000000
--- a/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c
- *
- * Copyright (C) 2013 Renesas Electronics Corporation
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-#include <common.h>
-#include <asm/io.h>
-
-#define PRR 0xFF000044
-
-u32 rmobile_get_cpu_type(void)
-{
- u32 product;
-
- product = readl(PRR);
-
- return (u32)((product & 0x00007F00) >> 8);
-}
-
-u32 rmobile_get_cpu_rev_integer(void)
-{
- u32 product;
-
- product = readl(PRR);
-
- return (u32)((product & 0x000000F0) >> 4);
-}
diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info-rcar.c b/arch/arm/cpu/armv7/rmobile/cpu_info-rcar.c
new file mode 100644
index 0000000..42ee30f
--- /dev/null
+++ b/arch/arm/cpu/armv7/rmobile/cpu_info-rcar.c
@@ -0,0 +1,26 @@
+/*
+ * arch/arm/cpu/armv7/rmobile/cpu_info-rcar.c
+ *
+ * Copyright (C) 2013,2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#include <common.h>
+#include <asm/io.h>
+
+#define PRR 0xFF000044
+
+u32 rmobile_get_cpu_type(void)
+{
+ return (readl(PRR) & 0x00007F00) >> 8;
+}
+
+u32 rmobile_get_cpu_rev_integer(void)
+{
+ return ((readl(PRR) & 0x000000F0) >> 4) + 1;
+}
+
+u32 rmobile_get_cpu_rev_fraction(void)
+{
+ return readl(PRR) & 0x0000000F;
+}
diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info.c b/arch/arm/cpu/armv7/rmobile/cpu_info.c
index 83d5282..7a7c97d 100644
--- a/arch/arm/cpu/armv7/rmobile/cpu_info.c
+++ b/arch/arm/cpu/armv7/rmobile/cpu_info.c
@@ -44,35 +44,30 @@
u32 rmobile_get_cpu_rev_fraction(void)
__attribute__((weak, alias("__rmobile_get_cpu_rev_fraction")));
+/* CPU infomation table */
+static const struct {
+ u16 cpu_type;
+ u8 cpu_name[10];
+} rmobile_cpuinfo[] = {
+ { 0x37, "SH73A0" },
+ { 0x40, "R8A7740" },
+ { 0x45, "R8A7790" },
+ { 0x47, "R8A7791" },
+ { 0x0, "CPU" },
+};
+
int print_cpuinfo(void)
{
- switch (rmobile_get_cpu_type()) {
- case 0x37:
- printf("CPU: Renesas Electronics SH73A0 rev %d.%d\n",
- rmobile_get_cpu_rev_integer(),
- rmobile_get_cpu_rev_fraction());
- break;
- case 0x40:
- printf("CPU: Renesas Electronics R8A7740 rev %d.%d\n",
- rmobile_get_cpu_rev_integer(),
- rmobile_get_cpu_rev_fraction());
- break;
-
- case 0x45:
- printf("CPU: Renesas Electronics R8A7790 rev %d\n",
- rmobile_get_cpu_rev_integer());
- break;
-
- case 0x47:
- printf("CPU: Renesas Electronics R8A7791 rev %d\n",
- rmobile_get_cpu_rev_integer());
- break;
-
- default:
- printf("CPU: Renesas Electronics CPU rev %d.%d\n",
- rmobile_get_cpu_rev_integer(),
- rmobile_get_cpu_rev_fraction());
- break;
+ int i = 0;
+ u32 cpu_type = rmobile_get_cpu_type();
+ for (; i < ARRAY_SIZE(rmobile_cpuinfo); i++) {
+ if (rmobile_cpuinfo[i].cpu_type == cpu_type) {
+ printf("CPU: Renesas Electronics %s rev %d.%d\n",
+ rmobile_cpuinfo[i].cpu_name,
+ rmobile_get_cpu_rev_integer(),
+ rmobile_get_cpu_rev_fraction());
+ break;
+ }
}
return 0;
}
diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
index e07cc80..287f8d7 100644
--- a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
+++ b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
@@ -2,7 +2,7 @@
* arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
* This file is lager low level initialize.
*
- * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013, 2014 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
@@ -36,16 +36,32 @@
.align 4
do_lowlevel_init:
/* surpress wfe if ca15 */
- tst r4, #4
+ tst r4, #4
mrceq p15, 0, r0, c1, c0, 1 /* actlr */
orreq r0, r0, #(1<<7)
mcreq p15, 0, r0, c1, c0, 1
+
/* and set l2 latency */
mrceq p15, 1, r0, c9, c0, 2 /* l2ctlr */
orreq r0, r0, #0x00000800
orreq r0, r0, #0x00000003
mcreq p15, 1, r0, c9, c0, 2
+ mrc p15, 0, r0, c0, c0, 5 /* r0 = MPIDR */
+ and r0, r0, #0xf00
+ lsr r0, r0, #8
+ tst r0, #1 /* only need for cluster 0 */
+ bne _exit_init_l2_a15
+
+ mrc p15, 1, r0, c9, c0, 2 /* r0 = L2CTLR */
+ and r1, r0, #7
+ cmp r1, #3 /* has already been set up */
+ bicne r0, r0, #0xe7
+ orrne r0, r0, #0x83 /* L2CTLR[7:6] + L2CTLR[2:0] */
+ orrne r0, r0, #0x20 /* L2CTLR[5] */
+ mcrne p15, 1, r0, c9, c0, 2
+
+_exit_init_l2_a15:
ldr r3, =(CONFIG_SYS_INIT_SP_ADDR)
sub sp, r3, #4
str lr, [sp]
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7790.h b/arch/arm/include/asm/arch-rmobile/r8a7790.h
index d9ea71f..6ef665d 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7790.h
+++ b/arch/arm/include/asm/arch-rmobile/r8a7790.h
@@ -1,615 +1,18 @@
/*
* arch/arm/include/asm/arch-rmobile/r8a7790.h
*
- * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013,2014 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
- */
+*/
#ifndef __ASM_ARCH_R8A7790_H
#define __ASM_ARCH_R8A7790_H
-/*
- * R8A7790 I/O Addresses
- */
-#define RWDT_BASE 0xE6020000
-#define SWDT_BASE 0xE6030000
-#define LBSC_BASE 0xFEC00200
-#define DBSC3_0_BASE 0xE6790000
-#define DBSC3_1_BASE 0xE67A0000
-#define TMU_BASE 0xE61E0000
-#define GPIO5_BASE 0xE6055000
-#define SH_QSPI_BASE 0xE6B10000
+#include "rcar-base.h"
-#define S3C_BASE 0xE6784000
-#define S3C_INT_BASE 0xE6784A00
-#define S3C_MEDIA_BASE 0xE6784B00
-
-#define S3C_QOS_DCACHE_BASE 0xE6784BDC
-#define S3C_QOS_CCI0_BASE 0xE6784C00
-#define S3C_QOS_CCI1_BASE 0xE6784C24
-#define S3C_QOS_MXI_BASE 0xE6784C48
-#define S3C_QOS_AXI_BASE 0xE6784C6C
-
-#define DBSC3_0_QOS_R0_BASE 0xE6791000
-#define DBSC3_0_QOS_R1_BASE 0xE6791100
-#define DBSC3_0_QOS_R2_BASE 0xE6791200
-#define DBSC3_0_QOS_R3_BASE 0xE6791300
-#define DBSC3_0_QOS_R4_BASE 0xE6791400
-#define DBSC3_0_QOS_R5_BASE 0xE6791500
-#define DBSC3_0_QOS_R6_BASE 0xE6791600
-#define DBSC3_0_QOS_R7_BASE 0xE6791700
-#define DBSC3_0_QOS_R8_BASE 0xE6791800
-#define DBSC3_0_QOS_R9_BASE 0xE6791900
-#define DBSC3_0_QOS_R10_BASE 0xE6791A00
-#define DBSC3_0_QOS_R11_BASE 0xE6791B00
-#define DBSC3_0_QOS_R12_BASE 0xE6791C00
-#define DBSC3_0_QOS_R13_BASE 0xE6791D00
-#define DBSC3_0_QOS_R14_BASE 0xE6791E00
-#define DBSC3_0_QOS_R15_BASE 0xE6791F00
-#define DBSC3_0_QOS_W0_BASE 0xE6792000
-#define DBSC3_0_QOS_W1_BASE 0xE6792100
-#define DBSC3_0_QOS_W2_BASE 0xE6792200
-#define DBSC3_0_QOS_W3_BASE 0xE6792300
-#define DBSC3_0_QOS_W4_BASE 0xE6792400
-#define DBSC3_0_QOS_W5_BASE 0xE6792500
-#define DBSC3_0_QOS_W6_BASE 0xE6792600
-#define DBSC3_0_QOS_W7_BASE 0xE6792700
-#define DBSC3_0_QOS_W8_BASE 0xE6792800
-#define DBSC3_0_QOS_W9_BASE 0xE6792900
-#define DBSC3_0_QOS_W10_BASE 0xE6792A00
-#define DBSC3_0_QOS_W11_BASE 0xE6792B00
-#define DBSC3_0_QOS_W12_BASE 0xE6792C00
-#define DBSC3_0_QOS_W13_BASE 0xE6792D00
-#define DBSC3_0_QOS_W14_BASE 0xE6792E00
-#define DBSC3_0_QOS_W15_BASE 0xE6792F00
-
-#define DBSC3_0_DBADJ2 0xE67900C8
-
-#define CCI_400_MAXOT_1 0xF0091110
-#define CCI_400_MAXOT_2 0xF0092110
-#define CCI_400_QOSCNTL_1 0xF009110C
-#define CCI_400_QOSCNTL_2 0xF009210C
-
-#define MXI_BASE 0xFE960000
-#define MXI_QOS_BASE 0xFE960300
-
-#define SYS_AXI_SYX64TO128_BASE 0xFF800300
-#define SYS_AXI_AVB_BASE 0xFF800340
-#define SYS_AXI_G2D_BASE 0xFF800540
-#define SYS_AXI_IMP0_BASE 0xFF800580
-#define SYS_AXI_IMP1_BASE 0xFF8005C0
-#define SYS_AXI_IMUX0_BASE 0xFF800600
-#define SYS_AXI_IMUX1_BASE 0xFF800640
-#define SYS_AXI_IMUX2_BASE 0xFF800680
-#define SYS_AXI_LBS_BASE 0xFF8006C0
-#define SYS_AXI_MMUDS_BASE 0xFF800700
-#define SYS_AXI_MMUM_BASE 0xFF800740
-#define SYS_AXI_MMUR_BASE 0xFF800780
-#define SYS_AXI_MMUS0_BASE 0xFF8007C0
-#define SYS_AXI_MMUS1_BASE 0xFF800800
-#define SYS_AXI_MTSB0_BASE 0xFF800880
-#define SYS_AXI_MTSB1_BASE 0xFF8008C0
-#define SYS_AXI_PCI_BASE 0xFF800900
-#define SYS_AXI_RTX_BASE 0xFF800940
-#define SYS_AXI_SDS0_BASE 0xFF800A80
-#define SYS_AXI_SDS1_BASE 0xFF800AC0
-#define SYS_AXI_USB20_BASE 0xFF800C00
-#define SYS_AXI_USB21_BASE 0xFF800C40
-#define SYS_AXI_USB22_BASE 0xFF800C80
-#define SYS_AXI_USB30_BASE 0xFF800CC0
-
-#define RT_AXI_SHX_BASE 0xFF810100
-#define RT_AXI_RDS_BASE 0xFF8101C0
-#define RT_AXI_RTX64TO128_BASE 0xFF810200
-#define RT_AXI_STPRO_BASE 0xFF810240
-
-#define MP_AXI_ADSP_BASE 0xFF820100
-#define MP_AXI_ASDS0_BASE 0xFF8201C0
-#define MP_AXI_ASDS1_BASE 0xFF820200
-#define MP_AXI_MLP_BASE 0xFF820240
-#define MP_AXI_MMUMP_BASE 0xFF820280
-#define MP_AXI_SPU_BASE 0xFF8202C0
-#define MP_AXI_SPUC_BASE 0xFF820300
-
-#define SYS_AXI256_AXI128TO256_BASE 0xFF860100
-#define SYS_AXI256_SYX_BASE 0xFF860140
-#define SYS_AXI256_MPX_BASE 0xFF860180
-#define SYS_AXI256_MXI_BASE 0xFF8601C0
-
-#define CCI_AXI_MMUS0_BASE 0xFF880100
-#define CCI_AXI_SYX2_BASE 0xFF880140
-#define CCI_AXI_MMUR_BASE 0xFF880180
-#define CCI_AXI_MMUDS_BASE 0xFF8801C0
-#define CCI_AXI_MMUM_BASE 0xFF880200
-#define CCI_AXI_MXI_BASE 0xFF880240
-#define CCI_AXI_MMUS1_BASE 0xFF880280
-#define CCI_AXI_MMUMP_BASE 0xFF8802C0
-
-#define MEDIA_AXI_JPR_BASE 0xFE964100
-#define MEDIA_AXI_JPW_BASE 0xFE966100
-#define MEDIA_AXI_GCU0R_BASE 0xFE964140
-#define MEDIA_AXI_GCU0W_BASE 0xFE966140
-#define MEDIA_AXI_GCU1R_BASE 0xFE964180
-#define MEDIA_AXI_GCU1W_BASE 0xFE966180
-#define MEDIA_AXI_TDMR_BASE 0xFE964500
-#define MEDIA_AXI_TDMW_BASE 0xFE966500
-#define MEDIA_AXI_VSP0CR_BASE 0xFE964540
-#define MEDIA_AXI_VSP0CW_BASE 0xFE966540
-#define MEDIA_AXI_VSP1CR_BASE 0xFE964580
-#define MEDIA_AXI_VSP1CW_BASE 0xFE966580
-#define MEDIA_AXI_VSPDU0CR_BASE 0xFE9645C0
-#define MEDIA_AXI_VSPDU0CW_BASE 0xFE9665C0
-#define MEDIA_AXI_VSPDU1CR_BASE 0xFE964600
-#define MEDIA_AXI_VSPDU1CW_BASE 0xFE966600
-#define MEDIA_AXI_VIN0W_BASE 0xFE966900
-#define MEDIA_AXI_VSP0R_BASE 0xFE964D00
-#define MEDIA_AXI_VSP0W_BASE 0xFE966D00
-#define MEDIA_AXI_FDP0R_BASE 0xFE964D40
-#define MEDIA_AXI_FDP0W_BASE 0xFE966D40
-#define MEDIA_AXI_IMSR_BASE 0xFE964D80
-#define MEDIA_AXI_IMSW_BASE 0xFE966D80
-#define MEDIA_AXI_VSP1R_BASE 0xFE965100
-#define MEDIA_AXI_VSP1W_BASE 0xFE967100
-#define MEDIA_AXI_FDP1R_BASE 0xFE965140
-#define MEDIA_AXI_FDP1W_BASE 0xFE967140
-#define MEDIA_AXI_IMRR_BASE 0xFE965180
-#define MEDIA_AXI_IMRW_BASE 0xFE967180
-#define MEDIA_AXI_FDP2R_BASE 0xFE9651C0
-#define MEDIA_AXI_FDP2W_BASE 0xFE966DC0
-#define MEDIA_AXI_VSPD0R_BASE 0xFE965500
-#define MEDIA_AXI_VSPD0W_BASE 0xFE967500
-#define MEDIA_AXI_VSPD1R_BASE 0xFE965540
-#define MEDIA_AXI_VSPD1W_BASE 0xFE967540
-#define MEDIA_AXI_DU0R_BASE 0xFE965580
-#define MEDIA_AXI_DU0W_BASE 0xFE967580
-#define MEDIA_AXI_DU1R_BASE 0xFE9655C0
-#define MEDIA_AXI_DU1W_BASE 0xFE9675C0
-#define MEDIA_AXI_VCP0CR_BASE 0xFE965900
-#define MEDIA_AXI_VCP0CW_BASE 0xFE967900
-#define MEDIA_AXI_VCP0VR_BASE 0xFE965940
-#define MEDIA_AXI_VCP0VW_BASE 0xFE967940
-#define MEDIA_AXI_VPC0R_BASE 0xFE965980
-#define MEDIA_AXI_VCP1CR_BASE 0xFE965D00
-#define MEDIA_AXI_VCP1CW_BASE 0xFE967D00
-#define MEDIA_AXI_VCP1VR_BASE 0xFE965D40
-#define MEDIA_AXI_VCP1VW_BASE 0xFE967D40
-#define MEDIA_AXI_VPC1R_BASE 0xFE965D80
-
-#define SYS_AXI_AVBDMSCR 0xFF802000
-#define SYS_AXI_SYX2DMSCR 0xFF802004
-#define SYS_AXI_CC50DMSCR 0xFF802008
-#define SYS_AXI_CC51DMSCR 0xFF80200C
-#define SYS_AXI_CCIDMSCR 0xFF802010
-#define SYS_AXI_CSDMSCR 0xFF802014
-#define SYS_AXI_DDMDMSCR 0xFF802018
-#define SYS_AXI_ETHDMSCR 0xFF80201C
-#define SYS_AXI_G2DDMSCR 0xFF802020
-#define SYS_AXI_IMP0DMSCR 0xFF802024
-#define SYS_AXI_IMP1DMSCR 0xFF802028
-#define SYS_AXI_LBSDMSCR 0xFF80202C
-#define SYS_AXI_MMUDSDMSCR 0xFF802030
-#define SYS_AXI_MMUMXDMSCR 0xFF802034
-#define SYS_AXI_MMURDDMSCR 0xFF802038
-#define SYS_AXI_MMUS0DMSCR 0xFF80203C
-#define SYS_AXI_MMUS1DMSCR 0xFF802040
-#define SYS_AXI_MPXDMSCR 0xFF802044
-#define SYS_AXI_MTSB0DMSCR 0xFF802048
-#define SYS_AXI_MTSB1DMSCR 0xFF80204C
-#define SYS_AXI_PCIDMSCR 0xFF802050
-#define SYS_AXI_RTXDMSCR 0xFF802054
-#define SYS_AXI_SAT0DMSCR 0xFF802058
-#define SYS_AXI_SAT1DMSCR 0xFF80205C
-#define SYS_AXI_SDM0DMSCR 0xFF802060
-#define SYS_AXI_SDM1DMSCR 0xFF802064
-#define SYS_AXI_SDS0DMSCR 0xFF802068
-#define SYS_AXI_SDS1DMSCR 0xFF80206C
-#define SYS_AXI_ETRABDMSCR 0xFF802070
-#define SYS_AXI_ETRKFDMSCR 0xFF802074
-#define SYS_AXI_UDM0DMSCR 0xFF802078
-#define SYS_AXI_UDM1DMSCR 0xFF80207C
-#define SYS_AXI_USB20DMSCR 0xFF802080
-#define SYS_AXI_USB21DMSCR 0xFF802084
-#define SYS_AXI_USB22DMSCR 0xFF802088
-#define SYS_AXI_USB30DMSCR 0xFF80208C
-#define SYS_AXI_X128TO64SLVDMSCR 0xFF802100
-#define SYS_AXI_X64TO128SLVDMSCR 0xFF802104
-#define SYS_AXI_AVBSLVDMSCR 0xFF802108
-#define SYS_AXI_SYX2SLVDMSCR 0xFF80210C
-#define SYS_AXI_ETHSLVDMSCR 0xFF802110
-#define SYS_AXI_GICSLVDMSCR 0xFF802114
-#define SYS_AXI_IMPSLVDMSCR 0xFF802118
-#define SYS_AXI_IMX0SLVDMSCR 0xFF80211C
-#define SYS_AXI_IMX1SLVDMSCR 0xFF802120
-#define SYS_AXI_IMX2SLVDMSCR 0xFF802124
-#define SYS_AXI_LBSSLVDMSCR 0xFF802128
-#define SYS_AXI_MMC0SLVDMSCR 0xFF80212C
-#define SYS_AXI_MMC1SLVDMSCR 0xFF802130
-#define SYS_AXI_MPXSLVDMSCR 0xFF802134
-#define SYS_AXI_MTSB0SLVDMSCR 0xFF802138
-#define SYS_AXI_MTSB1SLVDMSCR 0xFF80213C
-#define SYS_AXI_MXTSLVDMSCR 0xFF802140
-#define SYS_AXI_PCISLVDMSCR 0xFF802144
-#define SYS_AXI_SYAPBSLVDMSCR 0xFF802148
-#define SYS_AXI_QSAPBSLVDMSCR 0xFF80214C
-#define SYS_AXI_RTXSLVDMSCR 0xFF802150
-#define SYS_AXI_SAT0SLVDMSCR 0xFF802168
-#define SYS_AXI_SAT1SLVDMSCR 0xFF80216C
-#define SYS_AXI_SDAP0SLVDMSCR 0xFF802170
-#define SYS_AXI_SDAP1SLVDMSCR 0xFF802174
-#define SYS_AXI_SDAP2SLVDMSCR 0xFF802178
-#define SYS_AXI_SDAP3SLVDMSCR 0xFF80217C
-#define SYS_AXI_SGXSLVDMSCR 0xFF802180
-#define SYS_AXI_STBSLVDMSCR 0xFF802188
-#define SYS_AXI_STMSLVDMSCR 0xFF80218C
-#define SYS_AXI_TSPL0SLVDMSCR 0xFF802194
-#define SYS_AXI_TSPL1SLVDMSCR 0xFF802198
-#define SYS_AXI_TSPL2SLVDMSCR 0xFF80219C
-#define SYS_AXI_USB20SLVDMSCR 0xFF8021A0
-#define SYS_AXI_USB21SLVDMSCR 0xFF8021A4
-#define SYS_AXI_USB22SLVDMSCR 0xFF8021A8
-#define SYS_AXI_USB30SLVDMSCR 0xFF8021AC
-
-#define RT_AXI_CBMDMSCR 0xFF812000
-#define RT_AXI_DBDMSCR 0xFF812004
-#define RT_AXI_RDMDMSCR 0xFF812008
-#define RT_AXI_RDSDMSCR 0xFF81200C
-#define RT_AXI_STRDMSCR 0xFF812010
-#define RT_AXI_SY2RTDMSCR 0xFF812014
-#define RT_AXI_CBSSLVDMSCR 0xFF812100
-#define RT_AXI_DBSSLVDMSCR 0xFF812104
-#define RT_AXI_RTAP1SLVDMSCR 0xFF812108
-#define RT_AXI_RTAP2SLVDMSCR 0xFF81210C
-#define RT_AXI_RTAP3SLVDMSCR 0xFF812110
-#define RT_AXI_RT2SYSLVDMSCR 0xFF812114
-#define RT_AXI_A128TO64SLVDMSCR 0xFF812118
-#define RT_AXI_A64TO128SLVDMSCR 0xFF81211C
-#define RT_AXI_A64TO128CSLVDMSCR 0xFF812120
-#define RT_AXI_UTLBRSLVDMSCR 0xFF812128
-
-#define MP_AXI_ADSPDMSCR 0xFF822000
-#define MP_AXI_ASDM0DMSCR 0xFF822004
-#define MP_AXI_ASDM1DMSCR 0xFF822008
-#define MP_AXI_ASDS0DMSCR 0xFF82200C
-#define MP_AXI_ASDS1DMSCR 0xFF822010
-#define MP_AXI_MLPDMSCR 0xFF822014
-#define MP_AXI_MMUMPDMSCR 0xFF822018
-#define MP_AXI_SPUDMSCR 0xFF82201C
-#define MP_AXI_SPUCDMSCR 0xFF822020
-#define MP_AXI_SY2MPDMSCR 0xFF822024
-#define MP_AXI_ADSPSLVDMSCR 0xFF822100
-#define MP_AXI_MLMSLVDMSCR 0xFF822104
-#define MP_AXI_MPAP4SLVDMSCR 0xFF822108
-#define MP_AXI_MPAP5SLVDMSCR 0xFF82210C
-#define MP_AXI_MPAP6SLVDMSCR 0xFF822110
-#define MP_AXI_MPAP7SLVDMSCR 0xFF822114
-#define MP_AXI_MP2SYSLVDMSCR 0xFF822118
-#define MP_AXI_MP2SY2SLVDMSCR 0xFF82211C
-#define MP_AXI_MPXAPSLVDMSCR 0xFF822124
-#define MP_AXI_SPUSLVDMSCR 0xFF822128
-#define MP_AXI_UTLBMPSLVDMSCR 0xFF82212C
-
-#define ADM_AXI_ASDM0DMSCR 0xFF842000
-#define ADM_AXI_ASDM1DMSCR 0xFF842004
-#define ADM_AXI_MPAP1SLVDMSCR 0xFF842104
-#define ADM_AXI_MPAP2SLVDMSCR 0xFF842108
-#define ADM_AXI_MPAP3SLVDMSCR 0xFF84210C
-
-#define DM_AXI_RDMDMSCR 0xFF852000
-#define DM_AXI_SDM0DMSCR 0xFF852004
-#define DM_AXI_SDM1DMSCR 0xFF852008
-#define DM_AXI_MMAP0SLVDMSCR 0xFF852100
-#define DM_AXI_MMAP1SLVDMSCR 0xFF852104
-#define DM_AXI_QSPAPSLVDMSCR 0xFF852108
-#define DM_AXI_RAP4SLVDMSCR 0xFF85210C
-#define DM_AXI_RAP5SLVDMSCR 0xFF852110
-#define DM_AXI_SAP4SLVDMSCR 0xFF852114
-#define DM_AXI_SAP5SLVDMSCR 0xFF852118
-#define DM_AXI_SAP6SLVDMSCR 0xFF85211C
-#define DM_AXI_SAP65SLVDMSCR 0xFF852120
-#define DM_AXI_SDAP0SLVDMSCR 0xFF852124
-#define DM_AXI_SDAP1SLVDMSCR 0xFF852128
-#define DM_AXI_SDAP2SLVDMSCR 0xFF85212C
-#define DM_AXI_SDAP3SLVDMSCR 0xFF852130
-
-#define SYS_AXI256_SYXDMSCR 0xFF862000
-#define SYS_AXI256_MPXDMSCR 0xFF862004
-#define SYS_AXI256_MXIDMSCR 0xFF862008
-#define SYS_AXI256_X128TO256SLVDMSCR 0xFF862100
-#define SYS_AXI256_X256TO128SLVDMSCR 0xFF862104
-#define SYS_AXI256_SYXSLVDMSCR 0xFF862108
-#define SYS_AXI256_CCXSLVDMSCR 0xFF86210C
-#define SYS_AXI256_S3CSLVDMSCR 0xFF862110
-
-#define MXT_SYXDMSCR 0xFF872000
-#define MXT_CMM0SLVDMSCR 0xFF872100
-#define MXT_CMM1SLVDMSCR 0xFF872104
-#define MXT_CMM2SLVDMSCR 0xFF872108
-#define MXT_FDPSLVDMSCR 0xFF87210C
-#define MXT_IMRSLVDMSCR 0xFF872110
-#define MXT_VINSLVDMSCR 0xFF872114
-#define MXT_VPC0SLVDMSCR 0xFF872118
-#define MXT_VPC1SLVDMSCR 0xFF87211C
-#define MXT_VSP0SLVDMSCR 0xFF872120
-#define MXT_VSP1SLVDMSCR 0xFF872124
-#define MXT_VSPD0SLVDMSCR 0xFF872128
-#define MXT_VSPD1SLVDMSCR 0xFF87212C
-#define MXT_MAP1SLVDMSCR 0xFF872130
-#define MXT_MAP2SLVDMSCR 0xFF872134
-
-#define CCI_AXI_MMUS0DMSCR 0xFF882000
-#define CCI_AXI_SYX2DMSCR 0xFF882004
-#define CCI_AXI_MMURDMSCR 0xFF882008
-#define CCI_AXI_MMUDSDMSCR 0xFF88200C
-#define CCI_AXI_MMUMDMSCR 0xFF882010
-#define CCI_AXI_MXIDMSCR 0xFF882014
-#define CCI_AXI_MMUS1DMSCR 0xFF882018
-#define CCI_AXI_MMUMPDMSCR 0xFF88201C
-#define CCI_AXI_DVMDMSCR 0xFF882020
-#define CCI_AXI_CCISLVDMSCR 0xFF882100
-
-#define CCI_AXI_IPMMUIDVMCR 0xFF880400
-#define CCI_AXI_IPMMURDVMCR 0xFF880404
-#define CCI_AXI_IPMMUS0DVMCR 0xFF880408
-#define CCI_AXI_IPMMUS1DVMCR 0xFF88040C
-#define CCI_AXI_IPMMUMPDVMCR 0xFF880410
-#define CCI_AXI_IPMMUDSDVMCR 0xFF880414
-#define CCI_AXI_AX2ADDRMASK 0xFF88041C
-
-#ifndef __ASSEMBLY__
-#include <asm/types.h>
-
-/* RWDT */
-struct r8a7790_rwdt {
- u32 rwtcnt; /* 0x00 */
- u32 rwtcsra; /* 0x04 */
- u16 rwtcsrb; /* 0x08 */
-};
-
-/* SWDT */
-struct r8a7790_swdt {
- u32 swtcnt; /* 0x00 */
- u32 swtcsra; /* 0x04 */
- u16 swtcsrb; /* 0x08 */
-};
-
-/* LBSC */
-struct r8a7790_lbsc {
- u32 cs0ctrl;
- u32 cs1ctrl;
- u32 ecs0ctrl;
- u32 ecs1ctrl;
- u32 ecs2ctrl;
- u32 ecs3ctrl;
- u32 ecs4ctrl;
- u32 ecs5ctrl;
- u32 dummy0[4]; /* 0x20 .. 0x2C */
- u32 cswcr0;
- u32 cswcr1;
- u32 ecswcr0;
- u32 ecswcr1;
- u32 ecswcr2;
- u32 ecswcr3;
- u32 ecswcr4;
- u32 ecswcr5;
- u32 exdmawcr0;
- u32 exdmawcr1;
- u32 exdmawcr2;
- u32 dummy1[9]; /* 0x5C .. 0x7C */
- u32 cspwcr0;
- u32 cspwcr1;
- u32 ecspwcr0;
- u32 ecspwcr1;
- u32 ecspwcr2;
- u32 ecspwcr3;
- u32 ecspwcr4;
- u32 ecspwcr5;
- u32 exwtsync;
- u32 dummy2[3]; /* 0xA4 .. 0xAC */
- u32 cs0bstctl;
- u32 cs0btph;
- u32 dummy3[2]; /* 0xB8 .. 0xBC */
- u32 cs1gdst;
- u32 ecs0gdst;
- u32 ecs1gdst;
- u32 ecs2gdst;
- u32 ecs3gdst;
- u32 ecs4gdst;
- u32 ecs5gdst;
- u32 dummy4[5]; /* 0xDC .. 0xEC */
- u32 exdmaset0;
- u32 exdmaset1;
- u32 exdmaset2;
- u32 dummy5[5]; /* 0xFC .. 0x10C */
- u32 exdmcr0;
- u32 exdmcr1;
- u32 exdmcr2;
- u32 dummy6[5]; /* 0x11C .. 0x12C */
- u32 bcintsr;
- u32 bcintcr;
- u32 bcintmr;
- u32 dummy7; /* 0x13C */
- u32 exbatlv;
- u32 exwtsts;
- u32 dummy8[14]; /* 0x148 .. 0x17C */
- u32 atacsctrl;
- u32 dummy9[15]; /* 0x184 .. 0x1BC */
- u32 exbct;
- u32 extct;
-};
-
-/* DBSC3 */
-struct r8a7790_dbsc3 {
- u32 dummy0[3]; /* 0x00 .. 0x08 */
- u32 dbstate1;
- u32 dbacen;
- u32 dbrfen;
- u32 dbcmd;
- u32 dbwait;
- u32 dbkind;
- u32 dbconf0;
- u32 dummy1[2]; /* 0x28 .. 0x2C */
- u32 dbphytype;
- u32 dummy2[3]; /* 0x34 .. 0x3C */
- u32 dbtr0;
- u32 dbtr1;
- u32 dbtr2;
- u32 dummy3; /* 0x4C */
- u32 dbtr3;
- u32 dbtr4;
- u32 dbtr5;
- u32 dbtr6;
- u32 dbtr7;
- u32 dbtr8;
- u32 dbtr9;
- u32 dbtr10;
- u32 dbtr11;
- u32 dbtr12;
- u32 dbtr13;
- u32 dbtr14;
- u32 dbtr15;
- u32 dbtr16;
- u32 dbtr17;
- u32 dbtr18;
- u32 dbtr19;
- u32 dummy4[7]; /* 0x94 .. 0xAC */
- u32 dbbl;
- u32 dummy5[3]; /* 0xB4 .. 0xBC */
- u32 dbadj0;
- u32 dummy6; /* 0xC4 */
- u32 dbadj2;
- u32 dummy7[5]; /* 0xCC .. 0xDC */
- u32 dbrfcnf0;
- u32 dbrfcnf1;
- u32 dbrfcnf2;
- u32 dummy8[2]; /* 0xEC .. 0xF0 */
- u32 dbcalcnf;
- u32 dbcaltr;
- u32 dummy9; /* 0xFC */
- u32 dbrnk0;
- u32 dummy10[31]; /* 0x104 .. 0x17C */
- u32 dbpdncnf;
- u32 dummy11[47]; /* 0x184 ..0x23C */
- u32 dbdfistat;
- u32 dbdficnt;
- u32 dummy12[14]; /* 0x248 .. 0x27C */
- u32 dbpdlck;
- u32 dummy13[3]; /* 0x284 .. 0x28C */
- u32 dbpdrga;
- u32 dummy14[3]; /* 0x294 .. 0x29C */
- u32 dbpdrgd;
- u32 dummy15[24]; /* 0x2A4 .. 0x300 */
- u32 dbbs0cnt1;
- u32 dummy16[30]; /* 0x308 .. 0x37C */
- u32 dbwt0cnf0;
- u32 dbwt0cnf1;
- u32 dbwt0cnf2;
- u32 dbwt0cnf3;
- u32 dbwt0cnf4;
-};
-
-/* GPIO */
-struct r8a7790_gpio {
- u32 iointsel;
- u32 inoutsel;
- u32 outdt;
- u32 indt;
- u32 intdt;
- u32 intclr;
- u32 intmsk;
- u32 posneg;
- u32 edglevel;
- u32 filonoff;
- u32 intmsks;
- u32 mskclrs;
- u32 outdtsel;
- u32 outdth;
- u32 outdtl;
- u32 bothedge;
-};
-
-/* S3C(QoS) */
-struct r8a7790_s3c {
- u32 s3cexcladdmsk;
- u32 s3cexclidmsk;
- u32 s3cadsplcr;
- u32 s3cmaar;
- u32 s3carcr11;
- u32 s3crorr;
- u32 s3cworr;
- u32 s3carcr22;
- u32 dummy1[2]; /* 0x20 .. 0x24 */
- u32 s3cmctr;
- u32 dummy2; /* 0x2C */
- u32 cconf0;
- u32 cconf1;
- u32 cconf2;
- u32 cconf3;
-};
-
-struct r8a7790_s3c_qos {
- u32 s3cqos0;
- u32 s3cqos1;
- u32 s3cqos2;
- u32 s3cqos3;
- u32 s3cqos4;
- u32 s3cqos5;
- u32 s3cqos6;
- u32 s3cqos7;
- u32 s3cqos8;
-};
-
-/* DBSC(QoS) */
-struct r8a7790_dbsc3_qos {
- u32 dblgcnt;
- u32 dbtmval0;
- u32 dbtmval1;
- u32 dbtmval2;
- u32 dbtmval3;
- u32 dbrqctr;
- u32 dbthres0;
- u32 dbthres1;
- u32 dbthres2;
- u32 dummy0; /* 0x24 */
- u32 dblgqon;
-};
-
-/* MXI(QoS) */
-struct r8a7790_mxi {
- u32 mxsaar0;
- u32 mxsaar1;
- u32 dummy0[7]; /* 0x08 .. 0x20 */
- u32 mxaxiracr;
- u32 mxs3cracr;
- u32 dummy1[2]; /* 0x2C .. 0x30 */
- u32 mxaxiwacr;
- u32 mxs3cwacr;
- u32 dummy2; /* 0x3C */
- u32 mxrtcr;
- u32 mxwtcr;
-};
-
-struct r8a7790_mxi_qos {
- u32 vspdu0;
- u32 vspdu1;
- u32 du0;
- u32 du1;
-};
-
-/* AXI(QoS) */
-struct r8a7790_axi_qos {
- u32 qosconf;
- u32 qosctset0;
- u32 qosctset1;
- u32 qosctset2;
- u32 qosctset3;
- u32 qosreqctr;
- u32 qosthres0;
- u32 qosthres1;
- u32 qosthres2;
- u32 qosqon;
-};
-
-#endif
+#define R8A7790_CUT_ES2X 2
+#define IS_R8A7790_ES2() \
+ (rmobile_get_cpu_rev_integer() == R8A7790_CUT_ES2X)
#endif /* __ASM_ARCH_R8A7790_H */
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7791.h b/arch/arm/include/asm/arch-rmobile/r8a7791.h
index ff30180..4791825 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7791.h
+++ b/arch/arm/include/asm/arch-rmobile/r8a7791.h
@@ -1,69 +1,18 @@
/*
* arch/arm/include/asm/arch-rmobile/r8a7791.h
*
- * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013,2014 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
- */
+*/
#ifndef __ASM_ARCH_R8A7791_H
#define __ASM_ARCH_R8A7791_H
+#include "rcar-base.h"
/*
- * R8A7791 I/O Addresses
+ * R-Car (R8A7791) I/O Addresses
*/
-#define RWDT_BASE 0xE6020000
-#define SWDT_BASE 0xE6030000
-#define LBSC_BASE 0xFEC00200
-#define DBSC3_0_BASE 0xE6790000
-#define DBSC3_1_BASE 0xE67A0000
-#define TMU_BASE 0xE61E0000
-#define GPIO5_BASE 0xE6055000
-#define SH_QSPI_BASE 0xE6B10000
-
-#define S3C_BASE 0xE6784000
-#define S3C_INT_BASE 0xE6784A00
-#define S3C_MEDIA_BASE 0xE6784B00
-
-#define S3C_QOS_DCACHE_BASE 0xE6784BDC
-#define S3C_QOS_CCI0_BASE 0xE6784C00
-#define S3C_QOS_CCI1_BASE 0xE6784C24
-#define S3C_QOS_MXI_BASE 0xE6784C48
-#define S3C_QOS_AXI_BASE 0xE6784C6C
-
-#define DBSC3_0_QOS_R0_BASE 0xE6791000
-#define DBSC3_0_QOS_R1_BASE 0xE6791100
-#define DBSC3_0_QOS_R2_BASE 0xE6791200
-#define DBSC3_0_QOS_R3_BASE 0xE6791300
-#define DBSC3_0_QOS_R4_BASE 0xE6791400
-#define DBSC3_0_QOS_R5_BASE 0xE6791500
-#define DBSC3_0_QOS_R6_BASE 0xE6791600
-#define DBSC3_0_QOS_R7_BASE 0xE6791700
-#define DBSC3_0_QOS_R8_BASE 0xE6791800
-#define DBSC3_0_QOS_R9_BASE 0xE6791900
-#define DBSC3_0_QOS_R10_BASE 0xE6791A00
-#define DBSC3_0_QOS_R11_BASE 0xE6791B00
-#define DBSC3_0_QOS_R12_BASE 0xE6791C00
-#define DBSC3_0_QOS_R13_BASE 0xE6791D00
-#define DBSC3_0_QOS_R14_BASE 0xE6791E00
-#define DBSC3_0_QOS_R15_BASE 0xE6791F00
-#define DBSC3_0_QOS_W0_BASE 0xE6792000
-#define DBSC3_0_QOS_W1_BASE 0xE6792100
-#define DBSC3_0_QOS_W2_BASE 0xE6792200
-#define DBSC3_0_QOS_W3_BASE 0xE6792300
-#define DBSC3_0_QOS_W4_BASE 0xE6792400
-#define DBSC3_0_QOS_W5_BASE 0xE6792500
-#define DBSC3_0_QOS_W6_BASE 0xE6792600
-#define DBSC3_0_QOS_W7_BASE 0xE6792700
-#define DBSC3_0_QOS_W8_BASE 0xE6792800
-#define DBSC3_0_QOS_W9_BASE 0xE6792900
-#define DBSC3_0_QOS_W10_BASE 0xE6792A00
-#define DBSC3_0_QOS_W11_BASE 0xE6792B00
-#define DBSC3_0_QOS_W12_BASE 0xE6792C00
-#define DBSC3_0_QOS_W13_BASE 0xE6792D00
-#define DBSC3_0_QOS_W14_BASE 0xE6792E00
-#define DBSC3_0_QOS_W15_BASE 0xE6792F00
-
#define DBSC3_1_QOS_R0_BASE 0xE67A1000
#define DBSC3_1_QOS_R1_BASE 0xE67A1100
#define DBSC3_1_QOS_R2_BASE 0xE67A1200
@@ -97,569 +46,8 @@
#define DBSC3_1_QOS_W14_BASE 0xE67A2E00
#define DBSC3_1_QOS_W15_BASE 0xE67A2F00
-#define DBSC3_0_DBADJ2 0xE67900C8
-
-#define CCI_400_MAXOT_1 0xF0091110
-#define CCI_400_MAXOT_2 0xF0092110
-#define CCI_400_QOSCNTL_1 0xF009110C
-#define CCI_400_QOSCNTL_2 0xF009210C
-
-#define MXI_BASE 0xFE960000
-#define MXI_QOS_BASE 0xFE960300
-
-#define SYS_AXI_SYX64TO128_BASE 0xFF800300
-#define SYS_AXI_AVB_BASE 0xFF800340
-#define SYS_AXI_G2D_BASE 0xFF800540
-#define SYS_AXI_IMP0_BASE 0xFF800580
-#define SYS_AXI_IMP1_BASE 0xFF8005C0
-#define SYS_AXI_IMUX0_BASE 0xFF800600
-#define SYS_AXI_IMUX1_BASE 0xFF800640
-#define SYS_AXI_IMUX2_BASE 0xFF800680
-#define SYS_AXI_LBS_BASE 0xFF8006C0
-#define SYS_AXI_MMUDS_BASE 0xFF800700
-#define SYS_AXI_MMUM_BASE 0xFF800740
-#define SYS_AXI_MMUR_BASE 0xFF800780
-#define SYS_AXI_MMUS0_BASE 0xFF8007C0
-#define SYS_AXI_MMUS1_BASE 0xFF800800
-#define SYS_AXI_MTSB0_BASE 0xFF800880
-#define SYS_AXI_MTSB1_BASE 0xFF8008C0
-#define SYS_AXI_PCI_BASE 0xFF800900
-#define SYS_AXI_RTX_BASE 0xFF800940
-#define SYS_AXI_SDS0_BASE 0xFF800A80
-#define SYS_AXI_SDS1_BASE 0xFF800AC0
-#define SYS_AXI_USB20_BASE 0xFF800C00
-#define SYS_AXI_USB21_BASE 0xFF800C40
-#define SYS_AXI_USB22_BASE 0xFF800C80
-#define SYS_AXI_USB30_BASE 0xFF800CC0
-#define SYS_AXI_AX2M_BASE 0xFF800380
-#define SYS_AXI_CC50_BASE 0xFF8003C0
-#define SYS_AXI_CCI_BASE 0xFF800440
-#define SYS_AXI_CS_BASE 0xFF800480
-#define SYS_AXI_DDM_BASE 0xFF8004C0
-#define SYS_AXI_ETH_BASE 0xFF800500
-#define SYS_AXI_MPXM_BASE 0xFF800840
-#define SYS_AXI_SAT0_BASE 0xFF800980
-#define SYS_AXI_SAT1_BASE 0xFF8009C0
-#define SYS_AXI_SDM0_BASE 0xFF800A00
-#define SYS_AXI_SDM1_BASE 0xFF800A40
-#define SYS_AXI_TRAB_BASE 0xFF800B00
-#define SYS_AXI_UDM0_BASE 0xFF800B80
-#define SYS_AXI_UDM1_BASE 0xFF800BC0
-
-#define RT_AXI_SHX_BASE 0xFF810100
-#define RT_AXI_DBG_BASE 0xFF810140
-#define RT_AXI_RDM_BASE 0xFF810180
-#define RT_AXI_RDS_BASE 0xFF8101C0
-#define RT_AXI_RTX64TO128_BASE 0xFF810200
-#define RT_AXI_STPRO_BASE 0xFF810240
-#define RT_AXI_SY2RT_BASE 0xFF810280
-
-#define MP_AXI_ADSP_BASE 0xFF820100
-#define MP_AXI_ASDS0_BASE 0xFF8201C0
-#define MP_AXI_ASDS1_BASE 0xFF820200
-#define MP_AXI_MLP_BASE 0xFF820240
-#define MP_AXI_MMUMP_BASE 0xFF820280
-#define MP_AXI_SPU_BASE 0xFF8202C0
-#define MP_AXI_SPUC_BASE 0xFF820300
-
-#define SYS_AXI256_AXI128TO256_BASE 0xFF860100
-#define SYS_AXI256_SYX_BASE 0xFF860140
-#define SYS_AXI256_MPX_BASE 0xFF860180
-#define SYS_AXI256_MXI_BASE 0xFF8601C0
-
-#define CCI_AXI_MMUS0_BASE 0xFF880100
-#define CCI_AXI_SYX2_BASE 0xFF880140
-#define CCI_AXI_MMUR_BASE 0xFF880180
-#define CCI_AXI_MMUDS_BASE 0xFF8801C0
-#define CCI_AXI_MMUM_BASE 0xFF880200
-#define CCI_AXI_MXI_BASE 0xFF880240
-#define CCI_AXI_MMUS1_BASE 0xFF880280
-#define CCI_AXI_MMUMP_BASE 0xFF8802C0
-
-#define MEDIA_AXI_MXR_BASE 0xFE960080
-#define MEDIA_AXI_MXW_BASE 0xFE9600C0
-#define MEDIA_AXI_JPR_BASE 0xFE964100
-#define MEDIA_AXI_JPW_BASE 0xFE966100
-#define MEDIA_AXI_GCU0R_BASE 0xFE964140
-#define MEDIA_AXI_GCU0W_BASE 0xFE966140
-#define MEDIA_AXI_GCU1R_BASE 0xFE964180
-#define MEDIA_AXI_GCU1W_BASE 0xFE966180
-#define MEDIA_AXI_TDMR_BASE 0xFE964500
-#define MEDIA_AXI_TDMW_BASE 0xFE966500
-#define MEDIA_AXI_VSP0CR_BASE 0xFE964540
-#define MEDIA_AXI_VSP0CW_BASE 0xFE966540
-#define MEDIA_AXI_VSP1CR_BASE 0xFE964580
-#define MEDIA_AXI_VSP1CW_BASE 0xFE966580
-#define MEDIA_AXI_VSPDU0CR_BASE 0xFE9645C0
-#define MEDIA_AXI_VSPDU0CW_BASE 0xFE9665C0
-#define MEDIA_AXI_VSPDU1CR_BASE 0xFE964600
-#define MEDIA_AXI_VSPDU1CW_BASE 0xFE966600
-#define MEDIA_AXI_VIN0W_BASE 0xFE966900
-#define MEDIA_AXI_VSP0R_BASE 0xFE964D00
-#define MEDIA_AXI_VSP0W_BASE 0xFE966D00
-#define MEDIA_AXI_FDP0R_BASE 0xFE964D40
-#define MEDIA_AXI_FDP0W_BASE 0xFE966D40
-#define MEDIA_AXI_IMSR_BASE 0xFE964D80
-#define MEDIA_AXI_IMSW_BASE 0xFE966D80
-#define MEDIA_AXI_VSP1R_BASE 0xFE965100
-#define MEDIA_AXI_VSP1W_BASE 0xFE967100
-#define MEDIA_AXI_FDP1R_BASE 0xFE965140
-#define MEDIA_AXI_FDP1W_BASE 0xFE967140
-#define MEDIA_AXI_IMRR_BASE 0xFE965180
-#define MEDIA_AXI_IMRW_BASE 0xFE967180
-#define MEDIA_AXI_FDP2R_BASE 0xFE9651C0
-#define MEDIA_AXI_FDP2W_BASE 0xFE966DC0
-#define MEDIA_AXI_VSPD0R_BASE 0xFE965500
-#define MEDIA_AXI_VSPD0W_BASE 0xFE967500
-#define MEDIA_AXI_VSPD1R_BASE 0xFE965540
-#define MEDIA_AXI_VSPD1W_BASE 0xFE967540
-#define MEDIA_AXI_DU0R_BASE 0xFE965580
-#define MEDIA_AXI_DU0W_BASE 0xFE967580
-#define MEDIA_AXI_DU1R_BASE 0xFE9655C0
-#define MEDIA_AXI_DU1W_BASE 0xFE9675C0
-#define MEDIA_AXI_VCP0CR_BASE 0xFE965900
-#define MEDIA_AXI_VCP0CW_BASE 0xFE967900
-#define MEDIA_AXI_VCP0VR_BASE 0xFE965940
-#define MEDIA_AXI_VCP0VW_BASE 0xFE967940
-#define MEDIA_AXI_VPC0R_BASE 0xFE965980
-#define MEDIA_AXI_VCP1CR_BASE 0xFE965D00
-#define MEDIA_AXI_VCP1CW_BASE 0xFE967D00
-#define MEDIA_AXI_VCP1VR_BASE 0xFE965D40
-#define MEDIA_AXI_VCP1VW_BASE 0xFE967D40
-#define MEDIA_AXI_VPC1R_BASE 0xFE965D80
-
-#define SYS_AXI_AVBDMSCR 0xFF802000
-#define SYS_AXI_SYX2DMSCR 0xFF802004
-#define SYS_AXI_CC50DMSCR 0xFF802008
-#define SYS_AXI_CC51DMSCR 0xFF80200C
-#define SYS_AXI_CCIDMSCR 0xFF802010
-#define SYS_AXI_CSDMSCR 0xFF802014
-#define SYS_AXI_DDMDMSCR 0xFF802018
-#define SYS_AXI_ETHDMSCR 0xFF80201C
-#define SYS_AXI_G2DDMSCR 0xFF802020
-#define SYS_AXI_IMP0DMSCR 0xFF802024
-#define SYS_AXI_IMP1DMSCR 0xFF802028
-#define SYS_AXI_LBSDMSCR 0xFF80202C
-#define SYS_AXI_MMUDSDMSCR 0xFF802030
-#define SYS_AXI_MMUMXDMSCR 0xFF802034
-#define SYS_AXI_MMURDDMSCR 0xFF802038
-#define SYS_AXI_MMUS0DMSCR 0xFF80203C
-#define SYS_AXI_MMUS1DMSCR 0xFF802040
-#define SYS_AXI_MPXDMSCR 0xFF802044
-#define SYS_AXI_MTSB0DMSCR 0xFF802048
-#define SYS_AXI_MTSB1DMSCR 0xFF80204C
-#define SYS_AXI_PCIDMSCR 0xFF802050
-#define SYS_AXI_RTXDMSCR 0xFF802054
-#define SYS_AXI_SAT0DMSCR 0xFF802058
-#define SYS_AXI_SAT1DMSCR 0xFF80205C
-#define SYS_AXI_SDM0DMSCR 0xFF802060
-#define SYS_AXI_SDM1DMSCR 0xFF802064
-#define SYS_AXI_SDS0DMSCR 0xFF802068
-#define SYS_AXI_SDS1DMSCR 0xFF80206C
-#define SYS_AXI_ETRABDMSCR 0xFF802070
-#define SYS_AXI_ETRKFDMSCR 0xFF802074
-#define SYS_AXI_UDM0DMSCR 0xFF802078
-#define SYS_AXI_UDM1DMSCR 0xFF80207C
-#define SYS_AXI_USB20DMSCR 0xFF802080
-#define SYS_AXI_USB21DMSCR 0xFF802084
-#define SYS_AXI_USB22DMSCR 0xFF802088
-#define SYS_AXI_USB30DMSCR 0xFF80208C
-#define SYS_AXI_X128TO64SLVDMSCR 0xFF802100
-#define SYS_AXI_X64TO128SLVDMSCR 0xFF802104
-#define SYS_AXI_AVBSLVDMSCR 0xFF802108
-#define SYS_AXI_SYX2SLVDMSCR 0xFF80210C
-#define SYS_AXI_ETHSLVDMSCR 0xFF802110
-#define SYS_AXI_GICSLVDMSCR 0xFF802114
-#define SYS_AXI_IMPSLVDMSCR 0xFF802118
-#define SYS_AXI_IMX0SLVDMSCR 0xFF80211C
-#define SYS_AXI_IMX1SLVDMSCR 0xFF802120
-#define SYS_AXI_IMX2SLVDMSCR 0xFF802124
-#define SYS_AXI_LBSSLVDMSCR 0xFF802128
-#define SYS_AXI_MMC0SLVDMSCR 0xFF80212C
-#define SYS_AXI_MMC1SLVDMSCR 0xFF802130
-#define SYS_AXI_MPXSLVDMSCR 0xFF802134
-#define SYS_AXI_MTSB0SLVDMSCR 0xFF802138
-#define SYS_AXI_MTSB1SLVDMSCR 0xFF80213C
-#define SYS_AXI_MXTSLVDMSCR 0xFF802140
-#define SYS_AXI_PCISLVDMSCR 0xFF802144
-#define SYS_AXI_SYAPBSLVDMSCR 0xFF802148
-#define SYS_AXI_QSAPBSLVDMSCR 0xFF80214C
-#define SYS_AXI_RTXSLVDMSCR 0xFF802150
-#define SYS_AXI_SAT0SLVDMSCR 0xFF802168
-#define SYS_AXI_SAT1SLVDMSCR 0xFF80216C
-#define SYS_AXI_SDAP0SLVDMSCR 0xFF802170
-#define SYS_AXI_SDAP1SLVDMSCR 0xFF802174
-#define SYS_AXI_SDAP2SLVDMSCR 0xFF802178
-#define SYS_AXI_SDAP3SLVDMSCR 0xFF80217C
-#define SYS_AXI_SGXSLVDMSCR 0xFF802180
-#define SYS_AXI_STBSLVDMSCR 0xFF802188
-#define SYS_AXI_STMSLVDMSCR 0xFF80218C
-#define SYS_AXI_TSPL0SLVDMSCR 0xFF802194
-#define SYS_AXI_TSPL1SLVDMSCR 0xFF802198
-#define SYS_AXI_TSPL2SLVDMSCR 0xFF80219C
-#define SYS_AXI_USB20SLVDMSCR 0xFF8021A0
-#define SYS_AXI_USB21SLVDMSCR 0xFF8021A4
-#define SYS_AXI_USB22SLVDMSCR 0xFF8021A8
-#define SYS_AXI_USB30SLVDMSCR 0xFF8021AC
-
-#define RT_AXI_CBMDMSCR 0xFF812000
-#define RT_AXI_DBDMSCR 0xFF812004
-#define RT_AXI_RDMDMSCR 0xFF812008
-#define RT_AXI_RDSDMSCR 0xFF81200C
-#define RT_AXI_STRDMSCR 0xFF812010
-#define RT_AXI_SY2RTDMSCR 0xFF812014
-#define RT_AXI_CBSSLVDMSCR 0xFF812100
-#define RT_AXI_DBSSLVDMSCR 0xFF812104
-#define RT_AXI_RTAP1SLVDMSCR 0xFF812108
-#define RT_AXI_RTAP2SLVDMSCR 0xFF81210C
-#define RT_AXI_RTAP3SLVDMSCR 0xFF812110
-#define RT_AXI_RT2SYSLVDMSCR 0xFF812114
-#define RT_AXI_A128TO64SLVDMSCR 0xFF812118
-#define RT_AXI_A64TO128SLVDMSCR 0xFF81211C
-#define RT_AXI_A64TO128CSLVDMSCR 0xFF812120
-#define RT_AXI_UTLBRSLVDMSCR 0xFF812128
-
-#define MP_AXI_ADSPDMSCR 0xFF822000
-#define MP_AXI_ASDM0DMSCR 0xFF822004
-#define MP_AXI_ASDM1DMSCR 0xFF822008
-#define MP_AXI_ASDS0DMSCR 0xFF82200C
-#define MP_AXI_ASDS1DMSCR 0xFF822010
-#define MP_AXI_MLPDMSCR 0xFF822014
-#define MP_AXI_MMUMPDMSCR 0xFF822018
-#define MP_AXI_SPUDMSCR 0xFF82201C
-#define MP_AXI_SPUCDMSCR 0xFF822020
-#define MP_AXI_SY2MPDMSCR 0xFF822024
-#define MP_AXI_ADSPSLVDMSCR 0xFF822100
-#define MP_AXI_MLMSLVDMSCR 0xFF822104
-#define MP_AXI_MPAP4SLVDMSCR 0xFF822108
-#define MP_AXI_MPAP5SLVDMSCR 0xFF82210C
-#define MP_AXI_MPAP6SLVDMSCR 0xFF822110
-#define MP_AXI_MPAP7SLVDMSCR 0xFF822114
-#define MP_AXI_MP2SYSLVDMSCR 0xFF822118
-#define MP_AXI_MP2SY2SLVDMSCR 0xFF82211C
-#define MP_AXI_MPXAPSLVDMSCR 0xFF822124
-#define MP_AXI_SPUSLVDMSCR 0xFF822128
-#define MP_AXI_UTLBMPSLVDMSCR 0xFF82212C
-
-#define ADM_AXI_ASDM0DMSCR 0xFF842000
-#define ADM_AXI_ASDM1DMSCR 0xFF842004
-#define ADM_AXI_MPAP1SLVDMSCR 0xFF842104
-#define ADM_AXI_MPAP2SLVDMSCR 0xFF842108
-#define ADM_AXI_MPAP3SLVDMSCR 0xFF84210C
-
-#define DM_AXI_RDMDMSCR 0xFF852000
-#define DM_AXI_SDM0DMSCR 0xFF852004
-#define DM_AXI_SDM1DMSCR 0xFF852008
-#define DM_AXI_MMAP0SLVDMSCR 0xFF852100
-#define DM_AXI_MMAP1SLVDMSCR 0xFF852104
-#define DM_AXI_QSPAPSLVDMSCR 0xFF852108
-#define DM_AXI_RAP4SLVDMSCR 0xFF85210C
-#define DM_AXI_RAP5SLVDMSCR 0xFF852110
-#define DM_AXI_SAP4SLVDMSCR 0xFF852114
-#define DM_AXI_SAP5SLVDMSCR 0xFF852118
-#define DM_AXI_SAP6SLVDMSCR 0xFF85211C
-#define DM_AXI_SAP65SLVDMSCR 0xFF852120
-#define DM_AXI_SDAP0SLVDMSCR 0xFF852124
-#define DM_AXI_SDAP1SLVDMSCR 0xFF852128
-#define DM_AXI_SDAP2SLVDMSCR 0xFF85212C
-#define DM_AXI_SDAP3SLVDMSCR 0xFF852130
-
-#define SYS_AXI256_SYXDMSCR 0xFF862000
-#define SYS_AXI256_MPXDMSCR 0xFF862004
-#define SYS_AXI256_MXIDMSCR 0xFF862008
-#define SYS_AXI256_X128TO256SLVDMSCR 0xFF862100
-#define SYS_AXI256_X256TO128SLVDMSCR 0xFF862104
-#define SYS_AXI256_SYXSLVDMSCR 0xFF862108
-#define SYS_AXI256_CCXSLVDMSCR 0xFF86210C
-#define SYS_AXI256_S3CSLVDMSCR 0xFF862110
-
-#define MXT_SYXDMSCR 0xFF872000
-#define MXT_CMM0SLVDMSCR 0xFF872100
-#define MXT_CMM1SLVDMSCR 0xFF872104
-#define MXT_CMM2SLVDMSCR 0xFF872108
-#define MXT_FDPSLVDMSCR 0xFF87210C
-#define MXT_IMRSLVDMSCR 0xFF872110
-#define MXT_VINSLVDMSCR 0xFF872114
-#define MXT_VPC0SLVDMSCR 0xFF872118
-#define MXT_VPC1SLVDMSCR 0xFF87211C
-#define MXT_VSP0SLVDMSCR 0xFF872120
-#define MXT_VSP1SLVDMSCR 0xFF872124
-#define MXT_VSPD0SLVDMSCR 0xFF872128
-#define MXT_VSPD1SLVDMSCR 0xFF87212C
-#define MXT_MAP1SLVDMSCR 0xFF872130
-#define MXT_MAP2SLVDMSCR 0xFF872134
-
-#define CCI_AXI_MMUS0DMSCR 0xFF882000
-#define CCI_AXI_SYX2DMSCR 0xFF882004
-#define CCI_AXI_MMURDMSCR 0xFF882008
-#define CCI_AXI_MMUDSDMSCR 0xFF88200C
-#define CCI_AXI_MMUMDMSCR 0xFF882010
-#define CCI_AXI_MXIDMSCR 0xFF882014
-#define CCI_AXI_MMUS1DMSCR 0xFF882018
-#define CCI_AXI_MMUMPDMSCR 0xFF88201C
-#define CCI_AXI_DVMDMSCR 0xFF882020
-#define CCI_AXI_CCISLVDMSCR 0xFF882100
-
-#define CCI_AXI_IPMMUIDVMCR 0xFF880400
-#define CCI_AXI_IPMMURDVMCR 0xFF880404
-#define CCI_AXI_IPMMUS0DVMCR 0xFF880408
-#define CCI_AXI_IPMMUS1DVMCR 0xFF88040C
-#define CCI_AXI_IPMMUMPDVMCR 0xFF880410
-#define CCI_AXI_IPMMUDSDVMCR 0xFF880414
-#define CCI_AXI_AX2ADDRMASK 0xFF88041C
-
-#ifndef __ASSEMBLY__
-#include <asm/types.h>
-
-/* RWDT */
-struct r8a7791_rwdt {
- u32 rwtcnt; /* 0x00 */
- u32 rwtcsra; /* 0x04 */
- u16 rwtcsrb; /* 0x08 */
-};
-
-/* SWDT */
-struct r8a7791_swdt {
- u32 swtcnt; /* 0x00 */
- u32 swtcsra; /* 0x04 */
- u16 swtcsrb; /* 0x08 */
-};
-
-/* LBSC */
-struct r8a7791_lbsc {
- u32 cs0ctrl;
- u32 cs1ctrl;
- u32 ecs0ctrl;
- u32 ecs1ctrl;
- u32 ecs2ctrl;
- u32 ecs3ctrl;
- u32 ecs4ctrl;
- u32 ecs5ctrl;
- u32 dummy0[4]; /* 0x20 .. 0x2C */
- u32 cswcr0;
- u32 cswcr1;
- u32 ecswcr0;
- u32 ecswcr1;
- u32 ecswcr2;
- u32 ecswcr3;
- u32 ecswcr4;
- u32 ecswcr5;
- u32 exdmawcr0;
- u32 exdmawcr1;
- u32 exdmawcr2;
- u32 dummy1[9]; /* 0x5C .. 0x7C */
- u32 cspwcr0;
- u32 cspwcr1;
- u32 ecspwcr0;
- u32 ecspwcr1;
- u32 ecspwcr2;
- u32 ecspwcr3;
- u32 ecspwcr4;
- u32 ecspwcr5;
- u32 exwtsync;
- u32 dummy2[3]; /* 0xA4 .. 0xAC */
- u32 cs0bstctl;
- u32 cs0btph;
- u32 dummy3[2]; /* 0xB8 .. 0xBC */
- u32 cs1gdst;
- u32 ecs0gdst;
- u32 ecs1gdst;
- u32 ecs2gdst;
- u32 ecs3gdst;
- u32 ecs4gdst;
- u32 ecs5gdst;
- u32 dummy4[5]; /* 0xDC .. 0xEC */
- u32 exdmaset0;
- u32 exdmaset1;
- u32 exdmaset2;
- u32 dummy5[5]; /* 0xFC .. 0x10C */
- u32 exdmcr0;
- u32 exdmcr1;
- u32 exdmcr2;
- u32 dummy6[5]; /* 0x11C .. 0x12C */
- u32 bcintsr;
- u32 bcintcr;
- u32 bcintmr;
- u32 dummy7; /* 0x13C */
- u32 exbatlv;
- u32 exwtsts;
- u32 dummy8[14]; /* 0x148 .. 0x17C */
- u32 atacsctrl;
- u32 dummy9[15]; /* 0x184 .. 0x1BC */
- u32 exbct;
- u32 extct;
-};
-
-/* DBSC3 */
-struct r8a7791_dbsc3 {
- u32 dummy0[3]; /* 0x00 .. 0x08 */
- u32 dbstate1;
- u32 dbacen;
- u32 dbrfen;
- u32 dbcmd;
- u32 dbwait;
- u32 dbkind;
- u32 dbconf0;
- u32 dummy1[2]; /* 0x28 .. 0x2C */
- u32 dbphytype;
- u32 dummy2[3]; /* 0x34 .. 0x3C */
- u32 dbtr0;
- u32 dbtr1;
- u32 dbtr2;
- u32 dummy3; /* 0x4C */
- u32 dbtr3;
- u32 dbtr4;
- u32 dbtr5;
- u32 dbtr6;
- u32 dbtr7;
- u32 dbtr8;
- u32 dbtr9;
- u32 dbtr10;
- u32 dbtr11;
- u32 dbtr12;
- u32 dbtr13;
- u32 dbtr14;
- u32 dbtr15;
- u32 dbtr16;
- u32 dbtr17;
- u32 dbtr18;
- u32 dbtr19;
- u32 dummy4[7]; /* 0x94 .. 0xAC */
- u32 dbbl;
- u32 dummy5[3]; /* 0xB4 .. 0xBC */
- u32 dbadj0;
- u32 dummy6; /* 0xC4 */
- u32 dbadj2;
- u32 dummy7[5]; /* 0xCC .. 0xDC */
- u32 dbrfcnf0;
- u32 dbrfcnf1;
- u32 dbrfcnf2;
- u32 dummy8[2]; /* 0xEC .. 0xF0 */
- u32 dbcalcnf;
- u32 dbcaltr;
- u32 dummy9; /* 0xFC */
- u32 dbrnk0;
- u32 dummy10[31]; /* 0x104 .. 0x17C */
- u32 dbpdncnf;
- u32 dummy11[47]; /* 0x184 ..0x23C */
- u32 dbdfistat;
- u32 dbdficnt;
- u32 dummy12[14]; /* 0x248 .. 0x27C */
- u32 dbpdlck;
- u32 dummy13[3]; /* 0x284 .. 0x28C */
- u32 dbpdrga;
- u32 dummy14[3]; /* 0x294 .. 0x29C */
- u32 dbpdrgd;
- u32 dummy15[24]; /* 0x2A4 .. 0x300 */
- u32 dbbs0cnt1;
- u32 dummy16[30]; /* 0x308 .. 0x37C */
- u32 dbwt0cnf0;
- u32 dbwt0cnf1;
- u32 dbwt0cnf2;
- u32 dbwt0cnf3;
- u32 dbwt0cnf4;
-};
-
-/* GPIO */
-struct r8a7791_gpio {
- u32 iointsel;
- u32 inoutsel;
- u32 outdt;
- u32 indt;
- u32 intdt;
- u32 intclr;
- u32 intmsk;
- u32 posneg;
- u32 edglevel;
- u32 filonoff;
- u32 intmsks;
- u32 mskclrs;
- u32 outdtsel;
- u32 outdth;
- u32 outdtl;
- u32 bothedge;
-};
-
-/* S3C(QoS) */
-struct r8a7791_s3c {
- u32 s3cexcladdmsk;
- u32 s3cexclidmsk;
- u32 s3cadsplcr;
- u32 s3cmaar;
- u32 dummy0; /* 0x10 */
- u32 s3crorr;
- u32 s3cworr;
- u32 s3carcr22;
- u32 dummy1[2]; /* 0x20 .. 0x24 */
- u32 s3cmctr;
- u32 dummy2; /* 0x2C */
- u32 cconf0;
- u32 cconf1;
- u32 cconf2;
- u32 cconf3;
-};
-
-struct r8a7791_s3c_qos {
- u32 s3cqos0;
- u32 s3cqos1;
- u32 s3cqos2;
- u32 s3cqos3;
- u32 s3cqos4;
- u32 s3cqos5;
- u32 s3cqos6;
- u32 s3cqos7;
- u32 s3cqos8;
-};
-
-/* DBSC(QoS) */
-struct r8a7791_dbsc3_qos {
- u32 dblgcnt;
- u32 dbtmval0;
- u32 dbtmval1;
- u32 dbtmval2;
- u32 dbtmval3;
- u32 dbrqctr;
- u32 dbthres0;
- u32 dbthres1;
- u32 dbthres2;
- u32 dummy0; /* 0x24 */
- u32 dblgqon;
-};
-
-/* MXI(QoS) */
-struct r8a7791_mxi {
- u32 mxsaar0;
- u32 mxsaar1;
- u32 dummy0[8]; /* 0x08 .. 0x24 */
- u32 mxs3cracr;
- u32 dummy1[3]; /* 0x2C .. 0x34 */
- u32 mxs3cwacr;
- u32 dummy2; /* 0x3C */
- u32 mxrtcr;
- u32 mxwtcr;
-};
-
-struct r8a7791_mxi_qos {
- u32 vspdu0;
- u32 vspdu1;
- u32 du0;
- u32 du1;
-};
-
-/* AXI(QoS) */
-struct r8a7791_axi_qos {
- u32 qosconf;
- u32 qosctset0;
- u32 qosctset1;
- u32 qosctset2;
- u32 qosctset3;
- u32 qosreqctr;
- u32 qosthres0;
- u32 qosthres1;
- u32 qosthres2;
- u32 qosqon;
-};
-
-#endif
+#define R8A7791_CUT_ES2X 2
+#define IS_R8A7791_ES2() \
+ (rmobile_get_cpu_rev_integer() == R8A7791_CUT_ES2X)
#endif /* __ASM_ARCH_R8A7791_H */
diff --git a/arch/arm/include/asm/arch-rmobile/rcar-base.h b/arch/arm/include/asm/arch-rmobile/rcar-base.h
new file mode 100644
index 0000000..4331d31
--- /dev/null
+++ b/arch/arm/include/asm/arch-rmobile/rcar-base.h
@@ -0,0 +1,637 @@
+/*
+ * arch/arm/include/asm/arch-rmobile/rcar-base.h
+ *
+ * Copyright (C) 2013,2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+*/
+
+#ifndef __ASM_ARCH_RCAR_BASE_H
+#define __ASM_ARCH_RCAR_BASE_H
+
+/*
+ * R-Car (R8A7790/R8A7791) I/O Addresses
+ */
+#define RWDT_BASE 0xE6020000
+#define SWDT_BASE 0xE6030000
+#define LBSC_BASE 0xFEC00200
+#define DBSC3_0_BASE 0xE6790000
+#define DBSC3_1_BASE 0xE67A0000
+#define TMU_BASE 0xE61E0000
+#define GPIO5_BASE 0xE6055000
+#define SH_QSPI_BASE 0xE6B10000
+
+#define S3C_BASE 0xE6784000
+#define S3C_INT_BASE 0xE6784A00
+#define S3C_MEDIA_BASE 0xE6784B00
+
+#define S3C_QOS_DCACHE_BASE 0xE6784BDC
+#define S3C_QOS_CCI0_BASE 0xE6784C00
+#define S3C_QOS_CCI1_BASE 0xE6784C24
+#define S3C_QOS_MXI_BASE 0xE6784C48
+#define S3C_QOS_AXI_BASE 0xE6784C6C
+
+#define DBSC3_0_QOS_R0_BASE 0xE6791000
+#define DBSC3_0_QOS_R1_BASE 0xE6791100
+#define DBSC3_0_QOS_R2_BASE 0xE6791200
+#define DBSC3_0_QOS_R3_BASE 0xE6791300
+#define DBSC3_0_QOS_R4_BASE 0xE6791400
+#define DBSC3_0_QOS_R5_BASE 0xE6791500
+#define DBSC3_0_QOS_R6_BASE 0xE6791600
+#define DBSC3_0_QOS_R7_BASE 0xE6791700
+#define DBSC3_0_QOS_R8_BASE 0xE6791800
+#define DBSC3_0_QOS_R9_BASE 0xE6791900
+#define DBSC3_0_QOS_R10_BASE 0xE6791A00
+#define DBSC3_0_QOS_R11_BASE 0xE6791B00
+#define DBSC3_0_QOS_R12_BASE 0xE6791C00
+#define DBSC3_0_QOS_R13_BASE 0xE6791D00
+#define DBSC3_0_QOS_R14_BASE 0xE6791E00
+#define DBSC3_0_QOS_R15_BASE 0xE6791F00
+#define DBSC3_0_QOS_W0_BASE 0xE6792000
+#define DBSC3_0_QOS_W1_BASE 0xE6792100
+#define DBSC3_0_QOS_W2_BASE 0xE6792200
+#define DBSC3_0_QOS_W3_BASE 0xE6792300
+#define DBSC3_0_QOS_W4_BASE 0xE6792400
+#define DBSC3_0_QOS_W5_BASE 0xE6792500
+#define DBSC3_0_QOS_W6_BASE 0xE6792600
+#define DBSC3_0_QOS_W7_BASE 0xE6792700
+#define DBSC3_0_QOS_W8_BASE 0xE6792800
+#define DBSC3_0_QOS_W9_BASE 0xE6792900
+#define DBSC3_0_QOS_W10_BASE 0xE6792A00
+#define DBSC3_0_QOS_W11_BASE 0xE6792B00
+#define DBSC3_0_QOS_W12_BASE 0xE6792C00
+#define DBSC3_0_QOS_W13_BASE 0xE6792D00
+#define DBSC3_0_QOS_W14_BASE 0xE6792E00
+#define DBSC3_0_QOS_W15_BASE 0xE6792F00
+#define DBSC3_0_DBADJ2 0xE67900C8
+
+#define CCI_400_MAXOT_1 0xF0091110
+#define CCI_400_MAXOT_2 0xF0092110
+#define CCI_400_QOSCNTL_1 0xF009110C
+#define CCI_400_QOSCNTL_2 0xF009210C
+
+#define MXI_BASE 0xFE960000
+#define MXI_QOS_BASE 0xFE960300
+
+#define SYS_AXI_SYX64TO128_BASE 0xFF800300
+#define SYS_AXI_AVB_BASE 0xFF800340
+#define SYS_AXI_G2D_BASE 0xFF800540
+#define SYS_AXI_IMP0_BASE 0xFF800580
+#define SYS_AXI_IMP1_BASE 0xFF8005C0
+#define SYS_AXI_IMUX0_BASE 0xFF800600
+#define SYS_AXI_IMUX1_BASE 0xFF800640
+#define SYS_AXI_IMUX2_BASE 0xFF800680
+#define SYS_AXI_LBS_BASE 0xFF8006C0
+#define SYS_AXI_MMUDS_BASE 0xFF800700
+#define SYS_AXI_MMUM_BASE 0xFF800740
+#define SYS_AXI_MMUR_BASE 0xFF800780
+#define SYS_AXI_MMUS0_BASE 0xFF8007C0
+#define SYS_AXI_MMUS1_BASE 0xFF800800
+#define SYS_AXI_MTSB0_BASE 0xFF800880
+#define SYS_AXI_MTSB1_BASE 0xFF8008C0
+#define SYS_AXI_PCI_BASE 0xFF800900
+#define SYS_AXI_RTX_BASE 0xFF800940
+#define SYS_AXI_SDS0_BASE 0xFF800A80
+#define SYS_AXI_SDS1_BASE 0xFF800AC0
+#define SYS_AXI_USB20_BASE 0xFF800C00
+#define SYS_AXI_USB21_BASE 0xFF800C40
+#define SYS_AXI_USB22_BASE 0xFF800C80
+#define SYS_AXI_USB30_BASE 0xFF800CC0
+#define SYS_AXI_AX2M_BASE 0xFF800380
+#define SYS_AXI_CC50_BASE 0xFF8003C0
+#define SYS_AXI_CCI_BASE 0xFF800440
+#define SYS_AXI_CS_BASE 0xFF800480
+#define SYS_AXI_DDM_BASE 0xFF8004C0
+#define SYS_AXI_ETH_BASE 0xFF800500
+#define SYS_AXI_MPXM_BASE 0xFF800840
+#define SYS_AXI_SAT0_BASE 0xFF800980
+#define SYS_AXI_SAT1_BASE 0xFF8009C0
+#define SYS_AXI_SDM0_BASE 0xFF800A00
+#define SYS_AXI_SDM1_BASE 0xFF800A40
+#define SYS_AXI_TRAB_BASE 0xFF800B00
+#define SYS_AXI_UDM0_BASE 0xFF800B80
+#define SYS_AXI_UDM1_BASE 0xFF800BC0
+
+#define RT_AXI_SHX_BASE 0xFF810100
+#define RT_AXI_DBG_BASE 0xFF810140 /* R8A7791 only */
+#define RT_AXI_RDM_BASE 0xFF810180 /* R8A7791 only */
+#define RT_AXI_RDS_BASE 0xFF8101C0
+#define RT_AXI_RTX64TO128_BASE 0xFF810200
+#define RT_AXI_STPRO_BASE 0xFF810240
+#define RT_AXI_SY2RT_BASE 0xFF810280 /* R8A7791 only */
+
+#define MP_AXI_ADSP_BASE 0xFF820100
+#define MP_AXI_ASDS0_BASE 0xFF8201C0
+#define MP_AXI_ASDS1_BASE 0xFF820200
+#define MP_AXI_MLP_BASE 0xFF820240
+#define MP_AXI_MMUMP_BASE 0xFF820280
+#define MP_AXI_SPU_BASE 0xFF8202C0
+#define MP_AXI_SPUC_BASE 0xFF820300
+
+#define SYS_AXI256_AXI128TO256_BASE 0xFF860100
+#define SYS_AXI256_SYX_BASE 0xFF860140
+#define SYS_AXI256_MPX_BASE 0xFF860180
+#define SYS_AXI256_MXI_BASE 0xFF8601C0
+
+#define CCI_AXI_MMUS0_BASE 0xFF880100
+#define CCI_AXI_SYX2_BASE 0xFF880140
+#define CCI_AXI_MMUR_BASE 0xFF880180
+#define CCI_AXI_MMUDS_BASE 0xFF8801C0
+#define CCI_AXI_MMUM_BASE 0xFF880200
+#define CCI_AXI_MXI_BASE 0xFF880240
+#define CCI_AXI_MMUS1_BASE 0xFF880280
+#define CCI_AXI_MMUMP_BASE 0xFF8802C0
+
+#define MEDIA_AXI_MXR_BASE 0xFE960080 /* R8A7791 only */
+#define MEDIA_AXI_MXW_BASE 0xFE9600C0 /* R8A7791 only */
+#define MEDIA_AXI_JPR_BASE 0xFE964100
+#define MEDIA_AXI_JPW_BASE 0xFE966100
+#define MEDIA_AXI_GCU0R_BASE 0xFE964140
+#define MEDIA_AXI_GCU0W_BASE 0xFE966140
+#define MEDIA_AXI_GCU1R_BASE 0xFE964180
+#define MEDIA_AXI_GCU1W_BASE 0xFE966180
+#define MEDIA_AXI_TDMR_BASE 0xFE964500
+#define MEDIA_AXI_TDMW_BASE 0xFE966500
+#define MEDIA_AXI_VSP0CR_BASE 0xFE964540
+#define MEDIA_AXI_VSP0CW_BASE 0xFE966540
+#define MEDIA_AXI_VSP1CR_BASE 0xFE964580
+#define MEDIA_AXI_VSP1CW_BASE 0xFE966580
+#define MEDIA_AXI_VSPDU0CR_BASE 0xFE9645C0
+#define MEDIA_AXI_VSPDU0CW_BASE 0xFE9665C0
+#define MEDIA_AXI_VSPDU1CR_BASE 0xFE964600
+#define MEDIA_AXI_VSPDU1CW_BASE 0xFE966600
+#define MEDIA_AXI_VIN0W_BASE 0xFE966900
+#define MEDIA_AXI_VSP0R_BASE 0xFE964D00
+#define MEDIA_AXI_VSP0W_BASE 0xFE966D00
+#define MEDIA_AXI_FDP0R_BASE 0xFE964D40
+#define MEDIA_AXI_FDP0W_BASE 0xFE966D40
+#define MEDIA_AXI_IMSR_BASE 0xFE964D80
+#define MEDIA_AXI_IMSW_BASE 0xFE966D80
+#define MEDIA_AXI_VSP1R_BASE 0xFE965100
+#define MEDIA_AXI_VSP1W_BASE 0xFE967100
+#define MEDIA_AXI_FDP1R_BASE 0xFE965140
+#define MEDIA_AXI_FDP1W_BASE 0xFE967140
+#define MEDIA_AXI_IMRR_BASE 0xFE965180
+#define MEDIA_AXI_IMRW_BASE 0xFE967180
+#define MEDIA_AXI_FDP2R_BASE 0xFE9651C0
+#define MEDIA_AXI_FDP2W_BASE 0xFE966DC0
+#define MEDIA_AXI_VSPD0R_BASE 0xFE965500
+#define MEDIA_AXI_VSPD0W_BASE 0xFE967500
+#define MEDIA_AXI_VSPD1R_BASE 0xFE965540
+#define MEDIA_AXI_VSPD1W_BASE 0xFE967540
+#define MEDIA_AXI_DU0R_BASE 0xFE965580
+#define MEDIA_AXI_DU0W_BASE 0xFE967580
+#define MEDIA_AXI_DU1R_BASE 0xFE9655C0
+#define MEDIA_AXI_DU1W_BASE 0xFE9675C0
+#define MEDIA_AXI_VCP0CR_BASE 0xFE965900
+#define MEDIA_AXI_VCP0CW_BASE 0xFE967900
+#define MEDIA_AXI_VCP0VR_BASE 0xFE965940
+#define MEDIA_AXI_VCP0VW_BASE 0xFE967940
+#define MEDIA_AXI_VPC0R_BASE 0xFE965980
+#define MEDIA_AXI_VCP1CR_BASE 0xFE965D00
+#define MEDIA_AXI_VCP1CW_BASE 0xFE967D00
+#define MEDIA_AXI_VCP1VR_BASE 0xFE965D40
+#define MEDIA_AXI_VCP1VW_BASE 0xFE967D40
+#define MEDIA_AXI_VPC1R_BASE 0xFE965D80
+
+#define SYS_AXI_AVBDMSCR 0xFF802000
+#define SYS_AXI_SYX2DMSCR 0xFF802004
+#define SYS_AXI_CC50DMSCR 0xFF802008
+#define SYS_AXI_CC51DMSCR 0xFF80200C
+#define SYS_AXI_CCIDMSCR 0xFF802010
+#define SYS_AXI_CSDMSCR 0xFF802014
+#define SYS_AXI_DDMDMSCR 0xFF802018
+#define SYS_AXI_ETHDMSCR 0xFF80201C
+#define SYS_AXI_G2DDMSCR 0xFF802020
+#define SYS_AXI_IMP0DMSCR 0xFF802024
+#define SYS_AXI_IMP1DMSCR 0xFF802028
+#define SYS_AXI_LBSDMSCR 0xFF80202C
+#define SYS_AXI_MMUDSDMSCR 0xFF802030
+#define SYS_AXI_MMUMXDMSCR 0xFF802034
+#define SYS_AXI_MMURDDMSCR 0xFF802038
+#define SYS_AXI_MMUS0DMSCR 0xFF80203C
+#define SYS_AXI_MMUS1DMSCR 0xFF802040
+#define SYS_AXI_MPXDMSCR 0xFF802044
+#define SYS_AXI_MTSB0DMSCR 0xFF802048
+#define SYS_AXI_MTSB1DMSCR 0xFF80204C
+#define SYS_AXI_PCIDMSCR 0xFF802050
+#define SYS_AXI_RTXDMSCR 0xFF802054
+#define SYS_AXI_SAT0DMSCR 0xFF802058
+#define SYS_AXI_SAT1DMSCR 0xFF80205C
+#define SYS_AXI_SDM0DMSCR 0xFF802060
+#define SYS_AXI_SDM1DMSCR 0xFF802064
+#define SYS_AXI_SDS0DMSCR 0xFF802068
+#define SYS_AXI_SDS1DMSCR 0xFF80206C
+#define SYS_AXI_ETRABDMSCR 0xFF802070
+#define SYS_AXI_ETRKFDMSCR 0xFF802074
+#define SYS_AXI_UDM0DMSCR 0xFF802078
+#define SYS_AXI_UDM1DMSCR 0xFF80207C
+#define SYS_AXI_USB20DMSCR 0xFF802080
+#define SYS_AXI_USB21DMSCR 0xFF802084
+#define SYS_AXI_USB22DMSCR 0xFF802088
+#define SYS_AXI_USB30DMSCR 0xFF80208C
+#define SYS_AXI_X128TO64SLVDMSCR 0xFF802100
+#define SYS_AXI_X64TO128SLVDMSCR 0xFF802104
+#define SYS_AXI_AVBSLVDMSCR 0xFF802108
+#define SYS_AXI_SYX2SLVDMSCR 0xFF80210C
+#define SYS_AXI_ETHSLVDMSCR 0xFF802110
+#define SYS_AXI_GICSLVDMSCR 0xFF802114
+#define SYS_AXI_IMPSLVDMSCR 0xFF802118
+#define SYS_AXI_IMX0SLVDMSCR 0xFF80211C
+#define SYS_AXI_IMX1SLVDMSCR 0xFF802120
+#define SYS_AXI_IMX2SLVDMSCR 0xFF802124
+#define SYS_AXI_LBSSLVDMSCR 0xFF802128
+#define SYS_AXI_MMC0SLVDMSCR 0xFF80212C
+#define SYS_AXI_MMC1SLVDMSCR 0xFF802130
+#define SYS_AXI_MPXSLVDMSCR 0xFF802134
+#define SYS_AXI_MTSB0SLVDMSCR 0xFF802138
+#define SYS_AXI_MTSB1SLVDMSCR 0xFF80213C
+#define SYS_AXI_MXTSLVDMSCR 0xFF802140
+#define SYS_AXI_PCISLVDMSCR 0xFF802144
+#define SYS_AXI_SYAPBSLVDMSCR 0xFF802148
+#define SYS_AXI_QSAPBSLVDMSCR 0xFF80214C
+#define SYS_AXI_RTXSLVDMSCR 0xFF802150
+#define SYS_AXI_SAT0SLVDMSCR 0xFF802168
+#define SYS_AXI_SAT1SLVDMSCR 0xFF80216C
+#define SYS_AXI_SDAP0SLVDMSCR 0xFF802170
+#define SYS_AXI_SDAP1SLVDMSCR 0xFF802174
+#define SYS_AXI_SDAP2SLVDMSCR 0xFF802178
+#define SYS_AXI_SDAP3SLVDMSCR 0xFF80217C
+#define SYS_AXI_SGXSLVDMSCR 0xFF802180
+#define SYS_AXI_STBSLVDMSCR 0xFF802188
+#define SYS_AXI_STMSLVDMSCR 0xFF80218C
+#define SYS_AXI_TSPL0SLVDMSCR 0xFF802194
+#define SYS_AXI_TSPL1SLVDMSCR 0xFF802198
+#define SYS_AXI_TSPL2SLVDMSCR 0xFF80219C
+#define SYS_AXI_USB20SLVDMSCR 0xFF8021A0
+#define SYS_AXI_USB21SLVDMSCR 0xFF8021A4
+#define SYS_AXI_USB22SLVDMSCR 0xFF8021A8
+#define SYS_AXI_USB30SLVDMSCR 0xFF8021AC
+
+#define RT_AXI_CBMDMSCR 0xFF812000
+#define RT_AXI_DBDMSCR 0xFF812004
+#define RT_AXI_RDMDMSCR 0xFF812008
+#define RT_AXI_RDSDMSCR 0xFF81200C
+#define RT_AXI_STRDMSCR 0xFF812010
+#define RT_AXI_SY2RTDMSCR 0xFF812014
+#define RT_AXI_CBSSLVDMSCR 0xFF812100
+#define RT_AXI_DBSSLVDMSCR 0xFF812104
+#define RT_AXI_RTAP1SLVDMSCR 0xFF812108
+#define RT_AXI_RTAP2SLVDMSCR 0xFF81210C
+#define RT_AXI_RTAP3SLVDMSCR 0xFF812110
+#define RT_AXI_RT2SYSLVDMSCR 0xFF812114
+#define RT_AXI_A128TO64SLVDMSCR 0xFF812118
+#define RT_AXI_A64TO128SLVDMSCR 0xFF81211C
+#define RT_AXI_A64TO128CSLVDMSCR 0xFF812120
+#define RT_AXI_UTLBRSLVDMSCR 0xFF812128
+
+#define MP_AXI_ADSPDMSCR 0xFF822000
+#define MP_AXI_ASDM0DMSCR 0xFF822004
+#define MP_AXI_ASDM1DMSCR 0xFF822008
+#define MP_AXI_ASDS0DMSCR 0xFF82200C
+#define MP_AXI_ASDS1DMSCR 0xFF822010
+#define MP_AXI_MLPDMSCR 0xFF822014
+#define MP_AXI_MMUMPDMSCR 0xFF822018
+#define MP_AXI_SPUDMSCR 0xFF82201C
+#define MP_AXI_SPUCDMSCR 0xFF822020
+#define MP_AXI_SY2MPDMSCR 0xFF822024
+#define MP_AXI_ADSPSLVDMSCR 0xFF822100
+#define MP_AXI_MLMSLVDMSCR 0xFF822104
+#define MP_AXI_MPAP4SLVDMSCR 0xFF822108
+#define MP_AXI_MPAP5SLVDMSCR 0xFF82210C
+#define MP_AXI_MPAP6SLVDMSCR 0xFF822110
+#define MP_AXI_MPAP7SLVDMSCR 0xFF822114
+#define MP_AXI_MP2SYSLVDMSCR 0xFF822118
+#define MP_AXI_MP2SY2SLVDMSCR 0xFF82211C
+#define MP_AXI_MPXAPSLVDMSCR 0xFF822124
+#define MP_AXI_SPUSLVDMSCR 0xFF822128
+#define MP_AXI_UTLBMPSLVDMSCR 0xFF82212C
+
+#define ADM_AXI_ASDM0DMSCR 0xFF842000
+#define ADM_AXI_ASDM1DMSCR 0xFF842004
+#define ADM_AXI_MPAP1SLVDMSCR 0xFF842104
+#define ADM_AXI_MPAP2SLVDMSCR 0xFF842108
+#define ADM_AXI_MPAP3SLVDMSCR 0xFF84210C
+
+#define DM_AXI_RDMDMSCR 0xFF852000
+#define DM_AXI_SDM0DMSCR 0xFF852004
+#define DM_AXI_SDM1DMSCR 0xFF852008
+#define DM_AXI_MMAP0SLVDMSCR 0xFF852100
+#define DM_AXI_MMAP1SLVDMSCR 0xFF852104
+#define DM_AXI_QSPAPSLVDMSCR 0xFF852108
+#define DM_AXI_RAP4SLVDMSCR 0xFF85210C
+#define DM_AXI_RAP5SLVDMSCR 0xFF852110
+#define DM_AXI_SAP4SLVDMSCR 0xFF852114
+#define DM_AXI_SAP5SLVDMSCR 0xFF852118
+#define DM_AXI_SAP6SLVDMSCR 0xFF85211C
+#define DM_AXI_SAP65SLVDMSCR 0xFF852120
+#define DM_AXI_SDAP0SLVDMSCR 0xFF852124
+#define DM_AXI_SDAP1SLVDMSCR 0xFF852128
+#define DM_AXI_SDAP2SLVDMSCR 0xFF85212C
+#define DM_AXI_SDAP3SLVDMSCR 0xFF852130
+
+#define SYS_AXI256_SYXDMSCR 0xFF862000
+#define SYS_AXI256_MPXDMSCR 0xFF862004
+#define SYS_AXI256_MXIDMSCR 0xFF862008
+#define SYS_AXI256_X128TO256SLVDMSCR 0xFF862100
+#define SYS_AXI256_X256TO128SLVDMSCR 0xFF862104
+#define SYS_AXI256_SYXSLVDMSCR 0xFF862108
+#define SYS_AXI256_CCXSLVDMSCR 0xFF86210C
+#define SYS_AXI256_S3CSLVDMSCR 0xFF862110
+
+#define MXT_SYXDMSCR 0xFF872000
+#define MXT_CMM0SLVDMSCR 0xFF872100
+#define MXT_CMM1SLVDMSCR 0xFF872104
+#define MXT_CMM2SLVDMSCR 0xFF872108
+#define MXT_FDPSLVDMSCR 0xFF87210C
+#define MXT_IMRSLVDMSCR 0xFF872110
+#define MXT_VINSLVDMSCR 0xFF872114
+#define MXT_VPC0SLVDMSCR 0xFF872118
+#define MXT_VPC1SLVDMSCR 0xFF87211C
+#define MXT_VSP0SLVDMSCR 0xFF872120
+#define MXT_VSP1SLVDMSCR 0xFF872124
+#define MXT_VSPD0SLVDMSCR 0xFF872128
+#define MXT_VSPD1SLVDMSCR 0xFF87212C
+#define MXT_MAP1SLVDMSCR 0xFF872130
+#define MXT_MAP2SLVDMSCR 0xFF872134
+
+#define CCI_AXI_MMUS0DMSCR 0xFF882000
+#define CCI_AXI_SYX2DMSCR 0xFF882004
+#define CCI_AXI_MMURDMSCR 0xFF882008
+#define CCI_AXI_MMUDSDMSCR 0xFF88200C
+#define CCI_AXI_MMUMDMSCR 0xFF882010
+#define CCI_AXI_MXIDMSCR 0xFF882014
+#define CCI_AXI_MMUS1DMSCR 0xFF882018
+#define CCI_AXI_MMUMPDMSCR 0xFF88201C
+#define CCI_AXI_DVMDMSCR 0xFF882020
+#define CCI_AXI_CCISLVDMSCR 0xFF882100
+
+#define CCI_AXI_IPMMUIDVMCR 0xFF880400
+#define CCI_AXI_IPMMURDVMCR 0xFF880404
+#define CCI_AXI_IPMMUS0DVMCR 0xFF880408
+#define CCI_AXI_IPMMUS1DVMCR 0xFF88040C
+#define CCI_AXI_IPMMUMPDVMCR 0xFF880410
+#define CCI_AXI_IPMMUDSDVMCR 0xFF880414
+#define CCI_AXI_AX2ADDRMASK 0xFF88041C
+
+#define PLL0CR 0xE61500D8
+#define PLL0_STC_MASK 0x7F000000
+#define PLL0_STC_BIT 24
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+
+/* RWDT */
+struct rcar_rwdt {
+ u32 rwtcnt; /* 0x00 */
+ u32 rwtcsra; /* 0x04 */
+ u16 rwtcsrb; /* 0x08 */
+};
+
+/* SWDT */
+struct rcar_swdt {
+ u32 swtcnt; /* 0x00 */
+ u32 swtcsra; /* 0x04 */
+ u16 swtcsrb; /* 0x08 */
+};
+
+/* LBSC */
+struct rcar_lbsc {
+ u32 cs0ctrl;
+ u32 cs1ctrl;
+ u32 ecs0ctrl;
+ u32 ecs1ctrl;
+ u32 ecs2ctrl;
+ u32 ecs3ctrl;
+ u32 ecs4ctrl;
+ u32 ecs5ctrl;
+ u32 dummy0[4]; /* 0x20 .. 0x2C */
+ u32 cswcr0;
+ u32 cswcr1;
+ u32 ecswcr0;
+ u32 ecswcr1;
+ u32 ecswcr2;
+ u32 ecswcr3;
+ u32 ecswcr4;
+ u32 ecswcr5;
+ u32 exdmawcr0;
+ u32 exdmawcr1;
+ u32 exdmawcr2;
+ u32 dummy1[9]; /* 0x5C .. 0x7C */
+ u32 cspwcr0;
+ u32 cspwcr1;
+ u32 ecspwcr0;
+ u32 ecspwcr1;
+ u32 ecspwcr2;
+ u32 ecspwcr3;
+ u32 ecspwcr4;
+ u32 ecspwcr5;
+ u32 exwtsync;
+ u32 dummy2[3]; /* 0xA4 .. 0xAC */
+ u32 cs0bstctl;
+ u32 cs0btph;
+ u32 dummy3[2]; /* 0xB8 .. 0xBC */
+ u32 cs1gdst;
+ u32 ecs0gdst;
+ u32 ecs1gdst;
+ u32 ecs2gdst;
+ u32 ecs3gdst;
+ u32 ecs4gdst;
+ u32 ecs5gdst;
+ u32 dummy4[5]; /* 0xDC .. 0xEC */
+ u32 exdmaset0;
+ u32 exdmaset1;
+ u32 exdmaset2;
+ u32 dummy5[5]; /* 0xFC .. 0x10C */
+ u32 exdmcr0;
+ u32 exdmcr1;
+ u32 exdmcr2;
+ u32 dummy6[5]; /* 0x11C .. 0x12C */
+ u32 bcintsr;
+ u32 bcintcr;
+ u32 bcintmr;
+ u32 dummy7; /* 0x13C */
+ u32 exbatlv;
+ u32 exwtsts;
+ u32 dummy8[14]; /* 0x148 .. 0x17C */
+ u32 atacsctrl;
+ u32 dummy9[15]; /* 0x184 .. 0x1BC */
+ u32 exbct;
+ u32 extct;
+};
+
+/* DBSC3 */
+struct rcar_dbsc3 {
+ u32 dummy0[3]; /* 0x00 .. 0x08 */
+ u32 dbstate1;
+ u32 dbacen;
+ u32 dbrfen;
+ u32 dbcmd;
+ u32 dbwait;
+ u32 dbkind;
+ u32 dbconf0;
+ u32 dummy1[2]; /* 0x28 .. 0x2C */
+ u32 dbphytype;
+ u32 dummy2[3]; /* 0x34 .. 0x3C */
+ u32 dbtr0;
+ u32 dbtr1;
+ u32 dbtr2;
+ u32 dummy3; /* 0x4C */
+ u32 dbtr3;
+ u32 dbtr4;
+ u32 dbtr5;
+ u32 dbtr6;
+ u32 dbtr7;
+ u32 dbtr8;
+ u32 dbtr9;
+ u32 dbtr10;
+ u32 dbtr11;
+ u32 dbtr12;
+ u32 dbtr13;
+ u32 dbtr14;
+ u32 dbtr15;
+ u32 dbtr16;
+ u32 dbtr17;
+ u32 dbtr18;
+ u32 dbtr19;
+ u32 dummy4[7]; /* 0x94 .. 0xAC */
+ u32 dbbl;
+ u32 dummy5[3]; /* 0xB4 .. 0xBC */
+ u32 dbadj0;
+ u32 dummy6; /* 0xC4 */
+ u32 dbadj2;
+ u32 dummy7[5]; /* 0xCC .. 0xDC */
+ u32 dbrfcnf0;
+ u32 dbrfcnf1;
+ u32 dbrfcnf2;
+ u32 dummy8[2]; /* 0xEC .. 0xF0 */
+ u32 dbcalcnf;
+ u32 dbcaltr;
+ u32 dummy9; /* 0xFC */
+ u32 dbrnk0;
+ u32 dummy10[31]; /* 0x104 .. 0x17C */
+ u32 dbpdncnf;
+ u32 dummy11[47]; /* 0x184 ..0x23C */
+ u32 dbdfistat;
+ u32 dbdficnt;
+ u32 dummy12[14]; /* 0x248 .. 0x27C */
+ u32 dbpdlck;
+ u32 dummy13[3]; /* 0x284 .. 0x28C */
+ u32 dbpdrga;
+ u32 dummy14[3]; /* 0x294 .. 0x29C */
+ u32 dbpdrgd;
+ u32 dummy15[24]; /* 0x2A4 .. 0x300 */
+ u32 dbbs0cnt1;
+ u32 dummy16[30]; /* 0x308 .. 0x37C */
+ u32 dbwt0cnf0;
+ u32 dbwt0cnf1;
+ u32 dbwt0cnf2;
+ u32 dbwt0cnf3;
+ u32 dbwt0cnf4;
+};
+
+/* GPIO */
+struct rcar_gpio {
+ u32 iointsel;
+ u32 inoutsel;
+ u32 outdt;
+ u32 indt;
+ u32 intdt;
+ u32 intclr;
+ u32 intmsk;
+ u32 posneg;
+ u32 edglevel;
+ u32 filonoff;
+ u32 intmsks;
+ u32 mskclrs;
+ u32 outdtsel;
+ u32 outdth;
+ u32 outdtl;
+ u32 bothedge;
+};
+
+/* S3C(QoS) */
+struct rcar_s3c {
+ u32 s3cexcladdmsk;
+ u32 s3cexclidmsk;
+ u32 s3cadsplcr;
+ u32 s3cmaar;
+ u32 s3carcr11;
+ u32 s3crorr;
+ u32 s3cworr;
+ u32 s3carcr22;
+ u32 dummy1[2]; /* 0x20 .. 0x24 */
+ u32 s3cmctr;
+ u32 dummy2; /* 0x2C */
+ u32 cconf0;
+ u32 cconf1;
+ u32 cconf2;
+ u32 cconf3;
+};
+
+struct rcar_s3c_qos {
+ u32 s3cqos0;
+ u32 s3cqos1;
+ u32 s3cqos2;
+ u32 s3cqos3;
+ u32 s3cqos4;
+ u32 s3cqos5;
+ u32 s3cqos6;
+ u32 s3cqos7;
+ u32 s3cqos8;
+};
+
+/* DBSC(QoS) */
+struct rcar_dbsc3_qos {
+ u32 dblgcnt;
+ u32 dbtmval0;
+ u32 dbtmval1;
+ u32 dbtmval2;
+ u32 dbtmval3;
+ u32 dbrqctr;
+ u32 dbthres0;
+ u32 dbthres1;
+ u32 dbthres2;
+ u32 dummy0; /* 0x24 */
+ u32 dblgqon;
+};
+
+/* MXI(QoS) */
+struct rcar_mxi {
+ u32 mxsaar0;
+ u32 mxsaar1;
+ u32 dummy0[7]; /* 0x08 .. 0x20 */
+ u32 mxaxiracr; /* R8a7790 only */
+ u32 mxs3cracr;
+ u32 dummy1[2]; /* 0x2C .. 0x30 */
+ u32 mxaxiwacr; /* R8a7790 only */
+ u32 mxs3cwacr;
+ u32 dummy2; /* 0x3C */
+ u32 mxrtcr;
+ u32 mxwtcr;
+};
+
+struct rcar_mxi_qos {
+ u32 vspdu0;
+ u32 vspdu1;
+ u32 du0;
+ u32 du1;
+};
+
+/* AXI(QoS) */
+struct rcar_axi_qos {
+ u32 qosconf;
+ u32 qosctset0;
+ u32 qosctset1;
+ u32 qosctset2;
+ u32 qosctset3;
+ u32 qosreqctr;
+ u32 qosthres0;
+ u32 qosthres1;
+ u32 qosthres2;
+ u32 qosqon;
+};
+
+#endif
+
+#endif /* __ASM_ARCH_RCAR_BASE_H */
diff --git a/arch/arm/include/asm/arch-rmobile/rmobile.h b/arch/arm/include/asm/arch-rmobile/rmobile.h
index 2382565..ebddd7a 100644
--- a/arch/arm/include/asm/arch-rmobile/rmobile.h
+++ b/arch/arm/include/asm/arch-rmobile/rmobile.h
@@ -15,4 +15,10 @@
#endif
#endif /* CONFIG_RMOBILE */
+#ifndef __ASSEMBLY__
+u32 rmobile_get_cpu_type(void);
+u32 rmobile_get_cpu_rev_integer(void);
+u32 rmobile_get_cpu_rev_fraction(void);
+#endif /* __ASSEMBLY__ */
+
#endif /* __ASM_ARCH_RMOBILE_H */
diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c
index 32d3b58..bfd0cc6 100644
--- a/board/renesas/koelsch/koelsch.c
+++ b/board/renesas/koelsch/koelsch.c
@@ -19,186 +19,28 @@
#include <netdev.h>
#include <miiphy.h>
#include <i2c.h>
+#include <div64.h>
#include "qos.h"
DECLARE_GLOBAL_DATA_PTR;
-#define s_init_wait(cnt) \
- ({ \
- u32 i = 0x10000 * cnt; \
- while (i > 0) \
- i--; \
- })
-
-
-#define dbpdrgd_check(bsc) \
- ({ \
- while ((readl(&bsc->dbpdrgd) & 0x1) != 0x1) \
- ; \
- })
-
-#if defined(CONFIG_NORFLASH)
-static void bsc_init(void)
-{
- struct r8a7791_lbsc *lbsc = (struct r8a7791_lbsc *)LBSC_BASE;
- struct r8a7791_dbsc3 *dbsc3_0 = (struct r8a7791_dbsc3 *)DBSC3_0_BASE;
-
- /* LBSC */
- writel(0x00000020, &lbsc->cs0ctrl);
- writel(0x00000020, &lbsc->cs1ctrl);
- writel(0x00002020, &lbsc->ecs0ctrl);
- writel(0x00002020, &lbsc->ecs1ctrl);
-
- writel(0x077F077F, &lbsc->cswcr0);
- writel(0x077F077F, &lbsc->cswcr1);
- writel(0x077F077F, &lbsc->ecswcr0);
- writel(0x077F077F, &lbsc->ecswcr1);
-
- /* DBSC3 */
- s_init_wait(10);
-
- writel(0x0000A55A, &dbsc3_0->dbpdlck);
- writel(0x00000001, &dbsc3_0->dbpdrga);
- writel(0x80000000, &dbsc3_0->dbpdrgd);
- writel(0x00000004, &dbsc3_0->dbpdrga);
- dbpdrgd_check(dbsc3_0);
-
- writel(0x00000006, &dbsc3_0->dbpdrga);
- writel(0x0001C000, &dbsc3_0->dbpdrgd);
-
- writel(0x00000023, &dbsc3_0->dbpdrga);
- writel(0x00FD2480, &dbsc3_0->dbpdrgd);
-
- writel(0x00000010, &dbsc3_0->dbpdrga);
- writel(0xF004649B, &dbsc3_0->dbpdrgd);
-
- writel(0x0000000F, &dbsc3_0->dbpdrga);
- writel(0x00181EE4, &dbsc3_0->dbpdrgd);
-
- writel(0x0000000E, &dbsc3_0->dbpdrga);
- writel(0x33C03812, &dbsc3_0->dbpdrgd);
-
- writel(0x00000003, &dbsc3_0->dbpdrga);
- writel(0x0300C481, &dbsc3_0->dbpdrgd);
-
- writel(0x00000007, &dbsc3_0->dbkind);
- writel(0x10030A02, &dbsc3_0->dbconf0);
- writel(0x00000001, &dbsc3_0->dbphytype);
- writel(0x00000000, &dbsc3_0->dbbl);
- writel(0x0000000B, &dbsc3_0->dbtr0);
- writel(0x00000008, &dbsc3_0->dbtr1);
- writel(0x00000000, &dbsc3_0->dbtr2);
- writel(0x0000000B, &dbsc3_0->dbtr3);
- writel(0x000C000B, &dbsc3_0->dbtr4);
- writel(0x00000027, &dbsc3_0->dbtr5);
- writel(0x0000001C, &dbsc3_0->dbtr6);
- writel(0x00000005, &dbsc3_0->dbtr7);
- writel(0x00000018, &dbsc3_0->dbtr8);
- writel(0x00000008, &dbsc3_0->dbtr9);
- writel(0x0000000C, &dbsc3_0->dbtr10);
- writel(0x00000009, &dbsc3_0->dbtr11);
- writel(0x00000012, &dbsc3_0->dbtr12);
- writel(0x000000D0, &dbsc3_0->dbtr13);
- writel(0x00140005, &dbsc3_0->dbtr14);
- writel(0x00050004, &dbsc3_0->dbtr15);
- writel(0x70233005, &dbsc3_0->dbtr16);
- writel(0x000C0000, &dbsc3_0->dbtr17);
- writel(0x00000300, &dbsc3_0->dbtr18);
- writel(0x00000040, &dbsc3_0->dbtr19);
- writel(0x00000001, &dbsc3_0->dbrnk0);
- writel(0x00020001, &dbsc3_0->dbadj0);
- writel(0x20082008, &dbsc3_0->dbadj2);
- writel(0x00020002, &dbsc3_0->dbwt0cnf0);
- writel(0x0000000F, &dbsc3_0->dbwt0cnf4);
-
- writel(0x00000015, &dbsc3_0->dbpdrga);
- writel(0x00000D70, &dbsc3_0->dbpdrgd);
-
- writel(0x00000016, &dbsc3_0->dbpdrga);
- writel(0x00000006, &dbsc3_0->dbpdrgd);
-
- writel(0x00000017, &dbsc3_0->dbpdrga);
- writel(0x00000018, &dbsc3_0->dbpdrgd);
-
- writel(0x00000012, &dbsc3_0->dbpdrga);
- writel(0x9D5CBB66, &dbsc3_0->dbpdrgd);
-
- writel(0x00000013, &dbsc3_0->dbpdrga);
- writel(0x1A868300, &dbsc3_0->dbpdrgd);
-
- writel(0x00000023, &dbsc3_0->dbpdrga);
- writel(0x00FDB6C0, &dbsc3_0->dbpdrgd);
-
- writel(0x00000014, &dbsc3_0->dbpdrga);
- writel(0x300214D8, &dbsc3_0->dbpdrgd);
-
- writel(0x0000001A, &dbsc3_0->dbpdrga);
- writel(0x930035C7, &dbsc3_0->dbpdrgd);
-
- writel(0x00000060, &dbsc3_0->dbpdrga);
- writel(0x330657B2, &dbsc3_0->dbpdrgd);
-
- writel(0x00000011, &dbsc3_0->dbpdrga);
- writel(0x1000040B, &dbsc3_0->dbpdrgd);
-
- writel(0x0000FA00, &dbsc3_0->dbcmd);
- writel(0x00000001, &dbsc3_0->dbpdrga);
- writel(0x00000071, &dbsc3_0->dbpdrgd);
-
- writel(0x00000004, &dbsc3_0->dbpdrga);
- dbpdrgd_check(dbsc3_0);
-
- writel(0x0000FA00, &dbsc3_0->dbcmd);
- writel(0x2100FA00, &dbsc3_0->dbcmd);
- writel(0x0000FA00, &dbsc3_0->dbcmd);
- writel(0x0000FA00, &dbsc3_0->dbcmd);
- writel(0x0000FA00, &dbsc3_0->dbcmd);
- writel(0x0000FA00, &dbsc3_0->dbcmd);
- writel(0x0000FA00, &dbsc3_0->dbcmd);
- writel(0x0000FA00, &dbsc3_0->dbcmd);
- writel(0x0000FA00, &dbsc3_0->dbcmd);
-
- writel(0x110000DB, &dbsc3_0->dbcmd);
-
- writel(0x00000001, &dbsc3_0->dbpdrga);
- writel(0x00000181, &dbsc3_0->dbpdrgd);
-
- writel(0x00000004, &dbsc3_0->dbpdrga);
- dbpdrgd_check(dbsc3_0);
-
- writel(0x00000001, &dbsc3_0->dbpdrga);
- writel(0x0000FE01, &dbsc3_0->dbpdrgd);
-
- writel(0x00000004, &dbsc3_0->dbpdrga);
- dbpdrgd_check(dbsc3_0);
-
- writel(0x00000000, &dbsc3_0->dbbs0cnt1);
- writel(0x01004C20, &dbsc3_0->dbcalcnf);
- writel(0x014000AA, &dbsc3_0->dbcaltr);
- writel(0x00000140, &dbsc3_0->dbrfcnf0);
- writel(0x00081860, &dbsc3_0->dbrfcnf1);
- writel(0x00010000, &dbsc3_0->dbrfcnf2);
- writel(0x00000001, &dbsc3_0->dbrfen);
- writel(0x00000001, &dbsc3_0->dbacen);
-}
-#else
-#define bsc_init() do {} while (0)
-#endif /* CONFIG_NORFLASH */
-
+#define CLK2MHZ(clk) (clk / 1000 / 1000)
void s_init(void)
{
- struct r8a7791_rwdt *rwdt = (struct r8a7791_rwdt *)RWDT_BASE;
- struct r8a7791_swdt *swdt = (struct r8a7791_swdt *)SWDT_BASE;
+ struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+ struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+ u32 stc;
/* Watchdog init */
writel(0xA5A5A500, &rwdt->rwtcsra);
writel(0xA5A5A500, &swdt->swtcsra);
+ /* CPU frequency setting. Set to 1.5GHz */
+ stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
+ clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
+
/* QoS */
qos_init();
-
- /* BSC */
- bsc_init();
}
#define MSTPSR1 0xE6150038
@@ -213,18 +55,6 @@
#define SMSTPCR8 0xE6150990
#define ETHER_MSTP813 (1 << 13)
-#define PMMR 0xE6060000
-#define GPSR4 0xE6060014
-#define IPSR14 0xE6060058
-
-#define set_guard_reg(addr, mask, value) \
-{ \
- u32 val; \
- val = (readl(addr) & ~(mask)) | (value); \
- writel(~val, PMMR); \
- writel(val, addr); \
-}
-
#define mstp_setbits(type, addr, saddr, set) \
out_##type((saddr), in_##type(addr) | (set))
#define mstp_clrbits(type, addr, saddr, clear) \
@@ -238,13 +68,7 @@
{
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
-#if defined(CONFIG_NORFLASH)
/* SCIF0 */
- set_guard_reg(GPSR4, 0x34000000, 0x00000000);
- set_guard_reg(IPSR14, 0x00000FC7, 0x00000481);
- set_guard_reg(GPSR4, 0x00000000, 0x34000000);
-#endif
-
mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
/* ETHER */
diff --git a/board/renesas/koelsch/qos.c b/board/renesas/koelsch/qos.c
index 7f88f7d..e6c5e48 100644
--- a/board/renesas/koelsch/qos.c
+++ b/board/renesas/koelsch/qos.c
@@ -1,7 +1,7 @@
/*
* board/renesas/koelsch/qos.c
*
- * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013,2014 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*
@@ -13,7 +13,7 @@
#include <asm/io.h>
#include <asm/arch/rmobile.h>
-/* QoS version 0.23 */
+/* QoS version 0.240 for ES1 and version 0.310 for ES2 */
enum {
DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
@@ -102,24 +102,30 @@
void qos_init(void)
{
int i;
- struct r8a7791_s3c *s3c;
- struct r8a7791_s3c_qos *s3c_qos;
- struct r8a7791_dbsc3_qos *qos_addr;
- struct r8a7791_mxi *mxi;
- struct r8a7791_mxi_qos *mxi_qos;
- struct r8a7791_axi_qos *axi_qos;
+ struct rcar_s3c *s3c;
+ struct rcar_s3c_qos *s3c_qos;
+ struct rcar_dbsc3_qos *qos_addr;
+ struct rcar_mxi *mxi;
+ struct rcar_mxi_qos *mxi_qos;
+ struct rcar_axi_qos *axi_qos;
/* DBSC DBADJ2 */
writel(0x20042004, DBSC3_0_DBADJ2);
/* S3C -QoS */
- s3c = (struct r8a7791_s3c *)S3C_BASE;
- writel(0x00FF1B1D, &s3c->s3cadsplcr);
- writel(0x1F0D0C0C, &s3c->s3crorr);
- writel(0x1F0D0C0A, &s3c->s3cworr);
-
+ s3c = (struct rcar_s3c *)S3C_BASE;
+ if (IS_R8A7791_ES2()) {
+ writel(0x00FF1B0D, &s3c->s3cadsplcr);
+ writel(0x1F0D0B0A, &s3c->s3crorr);
+ writel(0x1F0D0B09, &s3c->s3cworr);
+ writel(0x00200808, &s3c->s3carcr11);
+ } else {
+ writel(0x00FF1B1D, &s3c->s3cadsplcr);
+ writel(0x1F0D0C0C, &s3c->s3crorr);
+ writel(0x1F0D0C0A, &s3c->s3cworr);
+ }
/* QoS Control Registers */
- s3c_qos = (struct r8a7791_s3c_qos *)S3C_QOS_CCI0_BASE;
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
writel(0x00890089, &s3c_qos->s3cqos0);
writel(0x20960010, &s3c_qos->s3cqos1);
writel(0x20302030, &s3c_qos->s3cqos2);
@@ -130,7 +136,7 @@
writel(0x20AA2200, &s3c_qos->s3cqos7);
writel(0x00002032, &s3c_qos->s3cqos8);
- s3c_qos = (struct r8a7791_s3c_qos *)S3C_QOS_CCI1_BASE;
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
writel(0x00890089, &s3c_qos->s3cqos0);
writel(0x20960010, &s3c_qos->s3cqos1);
writel(0x20302030, &s3c_qos->s3cqos2);
@@ -141,8 +147,11 @@
writel(0x20AA2200, &s3c_qos->s3cqos7);
writel(0x00002032, &s3c_qos->s3cqos8);
- s3c_qos = (struct r8a7791_s3c_qos *)S3C_QOS_MXI_BASE;
- writel(0x00820082, &s3c_qos->s3cqos0);
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
+ if (IS_R8A7791_ES2())
+ writel(0x80928092, &s3c_qos->s3cqos0);
+ else
+ writel(0x00820082, &s3c_qos->s3cqos0);
writel(0x20960020, &s3c_qos->s3cqos1);
writel(0x20302030, &s3c_qos->s3cqos2);
writel(0x20AA20DC, &s3c_qos->s3cqos3);
@@ -152,7 +161,7 @@
writel(0x20AA20DC, &s3c_qos->s3cqos7);
writel(0x00002032, &s3c_qos->s3cqos8);
- s3c_qos = (struct r8a7791_s3c_qos *)S3C_QOS_AXI_BASE;
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
writel(0x00820082, &s3c_qos->s3cqos0);
writel(0x20960020, &s3c_qos->s3cqos1);
writel(0x20302030, &s3c_qos->s3cqos2);
@@ -166,7 +175,7 @@
/* DBSC -QoS */
/* DBSC0 - Read */
for (i = DBSC3_00; i < DBSC3_NR; i++) {
- qos_addr = (struct r8a7791_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
+ qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
writel(0x00000002, &qos_addr->dblgcnt);
writel(0x00002096, &qos_addr->dbtmval0);
writel(0x00002064, &qos_addr->dbtmval1);
@@ -181,7 +190,7 @@
/* DBSC0 - Write */
for (i = DBSC3_00; i < DBSC3_NR; i++) {
- qos_addr = (struct r8a7791_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
+ qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
writel(0x00000002, &qos_addr->dblgcnt);
writel(0x000020EB, &qos_addr->dbtmval0);
writel(0x0000206E, &qos_addr->dbtmval1);
@@ -196,7 +205,7 @@
/* DBSC1 - Read */
for (i = DBSC3_00; i < DBSC3_NR; i++) {
- qos_addr = (struct r8a7791_dbsc3_qos *)dbsc3_1_r_qos_addr[i];
+ qos_addr = (struct rcar_dbsc3_qos *)dbsc3_1_r_qos_addr[i];
writel(0x00000002, &qos_addr->dblgcnt);
writel(0x00002096, &qos_addr->dbtmval0);
writel(0x00002064, &qos_addr->dbtmval1);
@@ -211,7 +220,7 @@
/* DBSC1 - Write */
for (i = DBSC3_00; i < DBSC3_NR; i++) {
- qos_addr = (struct r8a7791_dbsc3_qos *)dbsc3_1_w_qos_addr[i];
+ qos_addr = (struct rcar_dbsc3_qos *)dbsc3_1_w_qos_addr[i];
writel(0x00000002, &qos_addr->dblgcnt);
writel(0x000020EB, &qos_addr->dbtmval0);
writel(0x0000206E, &qos_addr->dbtmval1);
@@ -232,14 +241,14 @@
/* MXI -QoS */
/* Transaction Control (MXI) */
- mxi = (struct r8a7791_mxi *)MXI_BASE;
+ mxi = (struct rcar_mxi *)MXI_BASE;
writel(0x00000013, &mxi->mxrtcr);
writel(0x00000013, &mxi->mxwtcr);
writel(0x00780080, &mxi->mxsaar0);
writel(0x02000800, &mxi->mxsaar1);
/* QoS Control (MXI) */
- mxi_qos = (struct r8a7791_mxi_qos *)MXI_QOS_BASE;
+ mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
writel(0x0000000C, &mxi_qos->vspdu0);
writel(0x0000000C, &mxi_qos->vspdu1);
writel(0x0000000D, &mxi_qos->du0);
@@ -247,7 +256,7 @@
/* AXI -QoS */
/* Transaction Control (MXI) */
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x00002245, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
@@ -259,7 +268,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_AVB_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x000020A6, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -268,7 +277,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_G2D_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x000020A6, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -277,7 +286,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_IMP0_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP0_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002021, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -286,7 +295,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_IMP1_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002037, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -295,7 +304,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_IMUX0_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x00002245, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
@@ -307,7 +316,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_IMUX1_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x00002245, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
@@ -319,7 +328,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_IMUX2_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x00002245, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
@@ -331,7 +340,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_LBS_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000214C, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -340,7 +349,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MMUDS_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002004, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
@@ -352,7 +361,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MMUM_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002004, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
@@ -364,7 +373,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MMUR_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002004, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
@@ -376,7 +385,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MMUS0_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002004, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
@@ -388,7 +397,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MMUS1_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002004, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
@@ -400,7 +409,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MTSB0_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB0_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002021, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -409,7 +418,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MTSB1_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB1_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002021, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -418,7 +427,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_PCI_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_PCI_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000214C, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -427,7 +436,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_RTX_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x00002245, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
@@ -439,7 +448,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SDS0_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x000020A6, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -448,7 +457,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SDS1_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x000020A6, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -457,7 +466,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_USB20_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002053, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -466,7 +475,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_USB21_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB21_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002053, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -475,7 +484,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_USB22_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002053, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -484,7 +493,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_USB30_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB30_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000214C, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -493,7 +502,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_AX2M_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x00002245, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -502,7 +511,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_CC50_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002029, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -511,7 +520,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_CCI_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x00002245, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -520,7 +529,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_CS_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002053, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -529,7 +538,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_DDM_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x000020A6, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -538,7 +547,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_ETH_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002053, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -547,7 +556,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MPXM_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x00002245, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -556,7 +565,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SAT0_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT0_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002053, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -565,7 +574,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SAT1_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT1_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002053, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -574,7 +583,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SDM0_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000214C, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -583,7 +592,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SDM1_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000214C, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -592,7 +601,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_TRAB_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x000020A6, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -601,7 +610,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_UDM0_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002053, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -610,7 +619,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_UDM1_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002053, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -620,7 +629,7 @@
writel(0x00000001, &axi_qos->qosqon);
/* QoS Register (RT-AXI) */
- axi_qos = (struct r8a7791_axi_qos *)RT_AXI_SHX_BASE;
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002053, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
@@ -632,7 +641,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)RT_AXI_DBG_BASE;
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002053, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
@@ -644,7 +653,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)RT_AXI_RDM_BASE;
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_RDM_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002299, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -653,7 +662,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)RT_AXI_RDS_BASE;
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_RDS_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002029, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -662,7 +671,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)RT_AXI_RTX64TO128_BASE;
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x00002245, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
@@ -674,7 +683,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)RT_AXI_STPRO_BASE;
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_STPRO_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002029, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
@@ -686,12 +695,9 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)RT_AXI_SY2RT_BASE;
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x00002245, &axi_qos->qosctset0);
- writel(0x00002096, &axi_qos->qosctset1);
- writel(0x00002030, &axi_qos->qosctset2);
- writel(0x00002030, &axi_qos->qosctset3);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
@@ -699,7 +705,7 @@
writel(0x00000001, &axi_qos->qosqon);
/* QoS Register (MP-AXI) */
- axi_qos = (struct r8a7791_axi_qos *)MP_AXI_ADSP_BASE;
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002037, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -708,34 +714,34 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MP_AXI_ASDS0_BASE;
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002014, &axi_qos->qosctset0);
- writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00000040, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MP_AXI_ASDS1_BASE;
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002014, &axi_qos->qosctset0);
- writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00000040, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MP_AXI_MLP_BASE;
- writel(0x00000000, &axi_qos->qosconf);
- writel(0x00002014, &axi_qos->qosctset0);
- writel(0x00000001, &axi_qos->qosreqctr);
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00001FF0, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
- writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00002001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MP_AXI_MMUMP_BASE;
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002004, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
@@ -747,7 +753,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MP_AXI_SPU_BASE;
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002053, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -756,7 +762,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MP_AXI_SPUC_BASE;
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000206E, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -766,9 +772,12 @@
writel(0x00000001, &axi_qos->qosqon);
/* QoS Register (SYS-AXI256) */
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
writel(0x00000002, &axi_qos->qosconf);
- writel(0x00002245, &axi_qos->qosctset0);
+ if (IS_R8A7791_ES2())
+ writel(0x000020EB, &axi_qos->qosctset0);
+ else
+ writel(0x00002245, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002030, &axi_qos->qosctset2);
writel(0x00002030, &axi_qos->qosctset3);
@@ -778,9 +787,12 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI256_SYX_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE;
writel(0x00000002, &axi_qos->qosconf);
- writel(0x00002245, &axi_qos->qosctset0);
+ if (IS_R8A7791_ES2())
+ writel(0x000020EB, &axi_qos->qosctset0);
+ else
+ writel(0x00002245, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002030, &axi_qos->qosctset2);
writel(0x00002030, &axi_qos->qosctset3);
@@ -790,9 +802,12 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI256_MPX_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE;
writel(0x00000002, &axi_qos->qosconf);
- writel(0x00002245, &axi_qos->qosctset0);
+ if (IS_R8A7791_ES2())
+ writel(0x000020EB, &axi_qos->qosctset0);
+ else
+ writel(0x00002245, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
writel(0x00002030, &axi_qos->qosctset2);
writel(0x00002030, &axi_qos->qosctset3);
@@ -802,7 +817,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)SYS_AXI256_MXI_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x00002245, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
@@ -815,7 +830,7 @@
writel(0x00000001, &axi_qos->qosqon);
/* QoS Register (CCI-AXI) */
- axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUS0_BASE;
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002004, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
@@ -827,7 +842,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_SYX2_BASE;
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x00002245, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
@@ -839,7 +854,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUR_BASE;
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002004, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
@@ -851,7 +866,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUDS_BASE;
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002004, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
@@ -863,7 +878,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUM_BASE;
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002004, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
@@ -875,7 +890,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MXI_BASE;
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x00002245, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
@@ -887,7 +902,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUS1_BASE;
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002004, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
@@ -899,7 +914,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUMP_BASE;
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002004, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
@@ -912,7 +927,7 @@
writel(0x00000001, &axi_qos->qosqon);
/* QoS Register (Media-AXI) */
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_MXR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x000020DC, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
@@ -923,7 +938,7 @@
writel(0x00002032, &axi_qos->qosthres1);
writel(0x00000001, &axi_qos->qosthres2);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_MXW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x000020DC, &axi_qos->qosctset0);
writel(0x00002096, &axi_qos->qosctset1);
@@ -934,7 +949,7 @@
writel(0x00002032, &axi_qos->qosthres1);
writel(0x00000001, &axi_qos->qosthres2);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_JPR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002190, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -943,7 +958,21 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_JPW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ if (IS_R8A7791_ES2()) {
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ } else {
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ }
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002190, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -952,7 +981,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_TDMR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002190, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -961,7 +990,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_TDMW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002190, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -970,7 +999,21 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ if (IS_R8A7791_ES2()) {
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ } else {
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ }
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002190, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -979,7 +1022,21 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002190, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ if (IS_R8A7791_ES2()) {
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ } else {
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ }
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002190, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -988,43 +1045,36 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002190, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
- writel(0x00002064, &axi_qos->qosthres0);
- writel(0x00002004, &axi_qos->qosthres1);
+ if (IS_R8A7791_ES2()) {
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ } else {
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ }
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
writel(0x00000001, &axi_qos->qosconf);
- writel(0x00002190, &axi_qos->qosctset0);
+ if (IS_R8A7791_ES2())
+ writel(0x00001FF0, &axi_qos->qosctset0);
+ else
+ writel(0x000020C8, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
- writel(0x00000001, &axi_qos->qosthres2);
+ if (IS_R8A7791_ES2())
+ writel(0x00002001, &axi_qos->qosthres2);
+ else
+ writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE;
- writel(0x00000001, &axi_qos->qosconf);
- writel(0x00002190, &axi_qos->qosctset0);
- writel(0x00000020, &axi_qos->qosreqctr);
- writel(0x00002064, &axi_qos->qosthres0);
- writel(0x00002004, &axi_qos->qosthres1);
- writel(0x00000001, &axi_qos->qosthres2);
- writel(0x00000001, &axi_qos->qosqon);
-
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE;
- writel(0x00000001, &axi_qos->qosconf);
- writel(0x00002190, &axi_qos->qosctset0);
- writel(0x00000020, &axi_qos->qosreqctr);
- writel(0x00002064, &axi_qos->qosthres0);
- writel(0x00002004, &axi_qos->qosthres1);
- writel(0x00000001, &axi_qos->qosthres2);
- writel(0x00000001, &axi_qos->qosqon);
-
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x000020C8, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -1033,7 +1083,21 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_FDP0R_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ if (IS_R8A7791_ES2()) {
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ } else {
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ }
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x000020C8, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -1042,7 +1106,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_FDP0W_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x000020C8, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -1051,7 +1115,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_IMSR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x000020C8, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -1060,7 +1124,21 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_IMSW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ if (IS_R8A7791_ES2()) {
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ } else {
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ }
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1R_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x000020C8, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -1069,7 +1147,21 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSP1R_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1W_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x000020C8, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ if (IS_R8A7791_ES2()) {
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ } else {
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ }
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x000020C8, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -1078,7 +1170,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSP1W_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x000020C8, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -1087,76 +1179,55 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_FDP1R_BASE;
- writel(0x00000001, &axi_qos->qosconf);
- writel(0x000020C8, &axi_qos->qosctset0);
- writel(0x00000020, &axi_qos->qosreqctr);
- writel(0x00002064, &axi_qos->qosthres0);
- writel(0x00002004, &axi_qos->qosthres1);
- writel(0x00000001, &axi_qos->qosthres2);
- writel(0x00000001, &axi_qos->qosqon);
-
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_FDP1W_BASE;
- writel(0x00000001, &axi_qos->qosconf);
- writel(0x000020C8, &axi_qos->qosctset0);
- writel(0x00000020, &axi_qos->qosreqctr);
- writel(0x00002064, &axi_qos->qosthres0);
- writel(0x00002004, &axi_qos->qosthres1);
- writel(0x00000001, &axi_qos->qosthres2);
- writel(0x00000001, &axi_qos->qosqon);
-
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_IMRR_BASE;
- writel(0x00000001, &axi_qos->qosconf);
- writel(0x000020C8, &axi_qos->qosctset0);
- writel(0x00000020, &axi_qos->qosreqctr);
- writel(0x00002064, &axi_qos->qosthres0);
- writel(0x00002004, &axi_qos->qosthres1);
- writel(0x00000001, &axi_qos->qosthres2);
- writel(0x00000001, &axi_qos->qosqon);
-
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_IMRW_BASE;
- writel(0x00000001, &axi_qos->qosconf);
- writel(0x000020C8, &axi_qos->qosctset0);
- writel(0x00000020, &axi_qos->qosreqctr);
- writel(0x00002064, &axi_qos->qosthres0);
- writel(0x00002004, &axi_qos->qosthres1);
- writel(0x00000001, &axi_qos->qosthres2);
- writel(0x00000001, &axi_qos->qosqon);
-
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
- writel(0x00000000, &axi_qos->qosconf);
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+ if (IS_R8A7791_ES2())
+ writel(0x00000003, &axi_qos->qosconf);
+ else
+ writel(0x00000000, &axi_qos->qosconf);
writel(0x000020C8, &axi_qos->qosctset0);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
- writel(0x00000000, &axi_qos->qosconf);
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+ if (IS_R8A7791_ES2())
+ writel(0x00000003, &axi_qos->qosconf);
+ else
+ writel(0x00000000, &axi_qos->qosconf);
writel(0x000020C8, &axi_qos->qosctset0);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
- writel(0x00000000, &axi_qos->qosconf);
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
+ if (IS_R8A7791_ES2())
+ writel(0x00000003, &axi_qos->qosconf);
+ else
+ writel(0x00000000, &axi_qos->qosconf);
writel(0x000020C8, &axi_qos->qosctset0);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
- writel(0x00000000, &axi_qos->qosconf);
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
+ if (IS_R8A7791_ES2())
+ writel(0x00000003, &axi_qos->qosconf);
+ else
+ writel(0x00000000, &axi_qos->qosconf);
writel(0x000020C8, &axi_qos->qosctset0);
writel(0x00002064, &axi_qos->qosthres0);
writel(0x00002004, &axi_qos->qosthres1);
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_DU0R_BASE;
- writel(0x00000000, &axi_qos->qosconf);
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
+ if (IS_R8A7791_ES2())
+ writel(0x00000003, &axi_qos->qosconf);
+ else
+ writel(0x00000000, &axi_qos->qosconf);
writel(0x00002063, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
@@ -1164,8 +1235,11 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_DU0W_BASE;
- writel(0x00000000, &axi_qos->qosconf);
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
+ if (IS_R8A7791_ES2())
+ writel(0x00000000, &axi_qos->qosconf);
+ else
+ writel(0x00000000, &axi_qos->qosconf);
writel(0x00002063, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
writel(0x00002064, &axi_qos->qosthres0);
@@ -1173,7 +1247,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002073, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -1182,7 +1256,21 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00002073, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
+ if (IS_R8A7791_ES2()) {
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ } else {
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ }
+ writel(0x00000001, &axi_qos->qosthres2);
+ writel(0x00000001, &axi_qos->qosqon);
+
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002073, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -1191,25 +1279,21 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002073, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
- writel(0x00002064, &axi_qos->qosthres0);
- writel(0x00002004, &axi_qos->qosthres1);
+ if (IS_R8A7791_ES2()) {
+ writel(0x00000001, &axi_qos->qosthres0);
+ writel(0x00000001, &axi_qos->qosthres1);
+ } else {
+ writel(0x00002064, &axi_qos->qosthres0);
+ writel(0x00002004, &axi_qos->qosthres1);
+ }
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
- writel(0x00000001, &axi_qos->qosconf);
- writel(0x00002073, &axi_qos->qosctset0);
- writel(0x00000020, &axi_qos->qosreqctr);
- writel(0x00002064, &axi_qos->qosthres0);
- writel(0x00002004, &axi_qos->qosthres1);
- writel(0x00000001, &axi_qos->qosthres2);
- writel(0x00000001, &axi_qos->qosqon);
-
- axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VPC0R_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002073, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c
index ad5289a..a5a0474 100644
--- a/board/renesas/lager/lager.c
+++ b/board/renesas/lager/lager.c
@@ -24,181 +24,23 @@
DECLARE_GLOBAL_DATA_PTR;
-#define s_init_wait(cnt) \
- ({ \
- u32 i = 0x10000 * cnt; \
- while (i > 0) \
- i--; \
- })
-
-#define dbpdrgd_check(bsc) \
- ({ \
- while ((readl(&bsc->dbpdrgd) & 0x1) != 0x1) \
- ; \
- })
-
-#if defined(CONFIG_NORFLASH)
-static void bsc_init(void)
-{
- struct r8a7790_lbsc *lbsc = (struct r8a7790_lbsc *)LBSC_BASE;
- struct r8a7790_dbsc3 *dbsc3_0 = (struct r8a7790_dbsc3 *)DBSC3_0_BASE;
-
- /* LBSC */
- writel(0x00000020, &lbsc->cs0ctrl);
- writel(0x00000020, &lbsc->cs1ctrl);
- writel(0x00002020, &lbsc->ecs0ctrl);
- writel(0x00002020, &lbsc->ecs1ctrl);
-
- writel(0x077F077F, &lbsc->cswcr0);
- writel(0x077F077F, &lbsc->cswcr1);
- writel(0x077F077F, &lbsc->ecswcr0);
- writel(0x077F077F, &lbsc->ecswcr1);
-
- /* DBSC3 */
- s_init_wait(10);
-
- writel(0x0000A55A, &dbsc3_0->dbpdlck);
- writel(0x00000001, &dbsc3_0->dbpdrga);
- writel(0x80000000, &dbsc3_0->dbpdrgd);
- writel(0x00000004, &dbsc3_0->dbpdrga);
- dbpdrgd_check(dbsc3_0);
-
- writel(0x00000006, &dbsc3_0->dbpdrga);
- writel(0x0001C000, &dbsc3_0->dbpdrgd);
-
- writel(0x00000023, &dbsc3_0->dbpdrga);
- writel(0x00FD2480, &dbsc3_0->dbpdrgd);
-
- writel(0x00000010, &dbsc3_0->dbpdrga);
- writel(0xF004649B, &dbsc3_0->dbpdrgd);
-
- writel(0x0000000F, &dbsc3_0->dbpdrga);
- writel(0x00181EE4, &dbsc3_0->dbpdrgd);
-
- writel(0x0000000E, &dbsc3_0->dbpdrga);
- writel(0x33C03812, &dbsc3_0->dbpdrgd);
-
- writel(0x00000003, &dbsc3_0->dbpdrga);
- writel(0x0300C481, &dbsc3_0->dbpdrgd);
-
- writel(0x00000007, &dbsc3_0->dbkind);
- writel(0x10030A02, &dbsc3_0->dbconf0);
- writel(0x00000001, &dbsc3_0->dbphytype);
- writel(0x00000000, &dbsc3_0->dbbl);
- writel(0x0000000B, &dbsc3_0->dbtr0);
- writel(0x00000008, &dbsc3_0->dbtr1);
- writel(0x00000000, &dbsc3_0->dbtr2);
- writel(0x0000000B, &dbsc3_0->dbtr3);
- writel(0x000C000B, &dbsc3_0->dbtr4);
- writel(0x00000027, &dbsc3_0->dbtr5);
- writel(0x0000001C, &dbsc3_0->dbtr6);
- writel(0x00000005, &dbsc3_0->dbtr7);
- writel(0x00000018, &dbsc3_0->dbtr8);
- writel(0x00000008, &dbsc3_0->dbtr9);
- writel(0x0000000C, &dbsc3_0->dbtr10);
- writel(0x00000009, &dbsc3_0->dbtr11);
- writel(0x00000012, &dbsc3_0->dbtr12);
- writel(0x000000D0, &dbsc3_0->dbtr13);
- writel(0x00140005, &dbsc3_0->dbtr14);
- writel(0x00050004, &dbsc3_0->dbtr15);
- writel(0x70233005, &dbsc3_0->dbtr16);
- writel(0x000C0000, &dbsc3_0->dbtr17);
- writel(0x00000300, &dbsc3_0->dbtr18);
- writel(0x00000040, &dbsc3_0->dbtr19);
- writel(0x00000001, &dbsc3_0->dbrnk0);
- writel(0x00020001, &dbsc3_0->dbadj0);
- writel(0x20082008, &dbsc3_0->dbadj2);
- writel(0x00020002, &dbsc3_0->dbwt0cnf0);
- writel(0x0000000F, &dbsc3_0->dbwt0cnf4);
-
- writel(0x00000015, &dbsc3_0->dbpdrga);
- writel(0x00000D70, &dbsc3_0->dbpdrgd);
-
- writel(0x00000016, &dbsc3_0->dbpdrga);
- writel(0x00000006, &dbsc3_0->dbpdrgd);
-
- writel(0x00000017, &dbsc3_0->dbpdrga);
- writel(0x00000018, &dbsc3_0->dbpdrgd);
-
- writel(0x00000012, &dbsc3_0->dbpdrga);
- writel(0x9D5CBB66, &dbsc3_0->dbpdrgd);
-
- writel(0x00000013, &dbsc3_0->dbpdrga);
- writel(0x1A868300, &dbsc3_0->dbpdrgd);
-
- writel(0x00000023, &dbsc3_0->dbpdrga);
- writel(0x00FDB6C0, &dbsc3_0->dbpdrgd);
-
- writel(0x00000014, &dbsc3_0->dbpdrga);
- writel(0x300214D8, &dbsc3_0->dbpdrgd);
-
- writel(0x0000001A, &dbsc3_0->dbpdrga);
- writel(0x930035C7, &dbsc3_0->dbpdrgd);
-
- writel(0x00000060, &dbsc3_0->dbpdrga);
- writel(0x330657B2, &dbsc3_0->dbpdrgd);
-
- writel(0x00000011, &dbsc3_0->dbpdrga);
- writel(0x1000040B, &dbsc3_0->dbpdrgd);
-
- writel(0x0000FA00, &dbsc3_0->dbcmd);
- writel(0x00000001, &dbsc3_0->dbpdrga);
- writel(0x00000071, &dbsc3_0->dbpdrgd);
-
- writel(0x00000004, &dbsc3_0->dbpdrga);
- dbpdrgd_check(dbsc3_0);
-
- writel(0x0000FA00, &dbsc3_0->dbcmd);
- writel(0x2100FA00, &dbsc3_0->dbcmd);
- writel(0x0000FA00, &dbsc3_0->dbcmd);
- writel(0x0000FA00, &dbsc3_0->dbcmd);
- writel(0x0000FA00, &dbsc3_0->dbcmd);
- writel(0x0000FA00, &dbsc3_0->dbcmd);
- writel(0x0000FA00, &dbsc3_0->dbcmd);
- writel(0x0000FA00, &dbsc3_0->dbcmd);
- writel(0x0000FA00, &dbsc3_0->dbcmd);
-
- writel(0x110000DB, &dbsc3_0->dbcmd);
-
- writel(0x00000001, &dbsc3_0->dbpdrga);
- writel(0x00000181, &dbsc3_0->dbpdrgd);
-
- writel(0x00000004, &dbsc3_0->dbpdrga);
- dbpdrgd_check(dbsc3_0);
-
- writel(0x00000001, &dbsc3_0->dbpdrga);
- writel(0x0000FE01, &dbsc3_0->dbpdrgd);
-
- writel(0x00000004, &dbsc3_0->dbpdrga);
- dbpdrgd_check(dbsc3_0);
-
- writel(0x00000000, &dbsc3_0->dbbs0cnt1);
- writel(0x01004C20, &dbsc3_0->dbcalcnf);
- writel(0x014000AA, &dbsc3_0->dbcaltr);
- writel(0x00000140, &dbsc3_0->dbrfcnf0);
- writel(0x00081860, &dbsc3_0->dbrfcnf1);
- writel(0x00010000, &dbsc3_0->dbrfcnf2);
- writel(0x00000001, &dbsc3_0->dbrfen);
- writel(0x00000001, &dbsc3_0->dbacen);
-}
-#else
-#define bsc_init() do {} while (0)
-#endif /* CONFIG_NORFLASH */
-
+#define CLK2MHZ(clk) (clk / 1000 / 1000)
void s_init(void)
{
- struct r8a7790_rwdt *rwdt = (struct r8a7790_rwdt *)RWDT_BASE;
- struct r8a7790_swdt *swdt = (struct r8a7790_swdt *)SWDT_BASE;
+ struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+ struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+ u32 stc;
/* Watchdog init */
writel(0xA5A5A500, &rwdt->rwtcsra);
writel(0xA5A5A500, &swdt->swtcsra);
+ /* CPU frequency setting. Set to 1.4GHz */
+ stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
+ clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
+
/* QoS(Quality-of-Service) Init */
qos_init();
-
- /* BSC init */
- bsc_init();
}
#define MSTPSR1 0xE6150038
@@ -213,18 +55,6 @@
#define SMSTPCR8 0xE6150990
#define ETHER_MSTP813 (1 << 13)
-#define PMMR 0xE6060000
-#define GPSR4 0xE6060014
-#define IPSR14 0xE6060058
-
-#define set_guard_reg(addr, mask, value) \
-{ \
- u32 val; \
- val = (readl(addr) & ~(mask)) | (value); \
- writel(~val, PMMR); \
- writel(val, addr); \
-}
-
#define mstp_setbits(type, addr, saddr, set) \
out_##type((saddr), in_##type(addr) | (set))
#define mstp_clrbits(type, addr, saddr, clear) \
@@ -238,16 +68,8 @@
{
/* TMU0 */
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
-
-#if defined(CONFIG_NORFLASH)
/* SCIF0 */
- set_guard_reg(GPSR4, 0x34000000, 0x00000000);
- set_guard_reg(IPSR14, 0x00000FC7, 0x00000481);
- set_guard_reg(GPSR4, 0x00000000, 0x34000000);
-#endif
-
mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
-
/* ETHER */
mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
@@ -263,8 +85,6 @@
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
- /* board id for linux */
- gd->bd->bi_arch_number = MACH_TYPE_LAGER;
/* adress of boot parameters */
gd->bd->bi_boot_params = LAGER_SDRAM_BASE + 0x100;
diff --git a/board/renesas/lager/qos.c b/board/renesas/lager/qos.c
index b88511a..3742757 100644
--- a/board/renesas/lager/qos.c
+++ b/board/renesas/lager/qos.c
@@ -1,7 +1,7 @@
/*
* board/renesas/lager/qos.c
*
- * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013,2014 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
@@ -12,7 +12,7 @@
#include <asm/io.h>
#include <asm/arch/rmobile.h>
-/* QoS version 0.954 */
+/* QoS version 0.955 */
enum {
DBSC3_R00, DBSC3_R01, DBSC3_R02, DBSC3_R03, DBSC3_R04,
@@ -64,24 +64,24 @@
void qos_init(void)
{
int i;
- struct r8a7790_s3c *s3c;
- struct r8a7790_s3c_qos *s3c_qos;
- struct r8a7790_dbsc3_qos *qos_addr;
- struct r8a7790_mxi *mxi;
- struct r8a7790_mxi_qos *mxi_qos;
- struct r8a7790_axi_qos *axi_qos;
+ struct rcar_s3c *s3c;
+ struct rcar_s3c_qos *s3c_qos;
+ struct rcar_dbsc3_qos *qos_addr;
+ struct rcar_mxi *mxi;
+ struct rcar_mxi_qos *mxi_qos;
+ struct rcar_axi_qos *axi_qos;
/* DBSC DBADJ2 */
writel(0x20042004, DBSC3_0_DBADJ2);
/* S3C -QoS */
- s3c = (struct r8a7790_s3c *)S3C_BASE;
+ s3c = (struct rcar_s3c *)S3C_BASE;
writel(0x80FF1C1E, &s3c->s3cadsplcr);
writel(0x1F060505, &s3c->s3crorr);
writel(0x1F020100, &s3c->s3cworr);
/* QoS Control Registers */
- s3c_qos = (struct r8a7790_s3c_qos *)S3C_QOS_CCI0_BASE;
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
writel(0x00800080, &s3c_qos->s3cqos0);
writel(0x22000010, &s3c_qos->s3cqos1);
writel(0x22002200, &s3c_qos->s3cqos2);
@@ -92,7 +92,7 @@
writel(0x2F002200, &s3c_qos->s3cqos7);
writel(0x2F002F00, &s3c_qos->s3cqos8);
- s3c_qos = (struct r8a7790_s3c_qos *)S3C_QOS_CCI1_BASE;
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
writel(0x00800080, &s3c_qos->s3cqos0);
writel(0x22000010, &s3c_qos->s3cqos1);
writel(0x22002200, &s3c_qos->s3cqos2);
@@ -103,7 +103,7 @@
writel(0x2F002200, &s3c_qos->s3cqos7);
writel(0x2F002F00, &s3c_qos->s3cqos8);
- s3c_qos = (struct r8a7790_s3c_qos *)S3C_QOS_MXI_BASE;
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
writel(0x80918099, &s3c_qos->s3cqos0);
writel(0x20410010, &s3c_qos->s3cqos1);
writel(0x200A2023, &s3c_qos->s3cqos2);
@@ -114,7 +114,7 @@
writel(0x20502001, &s3c_qos->s3cqos7);
writel(0x20142032, &s3c_qos->s3cqos8);
- s3c_qos = (struct r8a7790_s3c_qos *)S3C_QOS_AXI_BASE;
+ s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
writel(0x00810089, &s3c_qos->s3cqos0);
writel(0x20410001, &s3c_qos->s3cqos1);
@@ -131,7 +131,7 @@
/* DBSC -QoS */
/* DBSC0 - Read/Write */
for (i = DBSC3_R00; i < DBSC3_NR; i++) {
- qos_addr = (struct r8a7790_dbsc3_qos *)dbsc3_qos_addr[i];
+ qos_addr = (struct rcar_dbsc3_qos *)dbsc3_qos_addr[i];
writel(0x00000203, &qos_addr->dblgcnt);
writel(0x00002064, &qos_addr->dbtmval0);
writel(0x00002048, &qos_addr->dbtmval1);
@@ -151,7 +151,7 @@
/* MXI -QoS */
/* Transaction Control (MXI) */
- mxi = (struct r8a7790_mxi *)MXI_BASE;
+ mxi = (struct rcar_mxi *)MXI_BASE;
writel(0x00000013, &mxi->mxrtcr);
writel(0x00000013, &mxi->mxwtcr);
writel(0x00B800C0, &mxi->mxsaar0);
@@ -162,7 +162,7 @@
writel(0x00200000, &mxi->mxaxiwacr);
/* QoS Control (MXI) */
- mxi_qos = (struct r8a7790_mxi_qos *)MXI_QOS_BASE;
+ mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
writel(0x0000000C, &mxi_qos->vspdu0);
writel(0x0000000C, &mxi_qos->vspdu1);
writel(0x0000000D, &mxi_qos->du0);
@@ -170,7 +170,7 @@
/* AXI -QoS */
/* Transaction Control (MXI) */
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x0000200F, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@@ -182,7 +182,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_AVB_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200A, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -191,7 +191,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_G2D_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200A, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -200,7 +200,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMP0_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP0_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002002, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -209,7 +209,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMP1_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002004, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -218,7 +218,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMUX0_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x0000200F, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@@ -230,7 +230,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMUX1_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x0000200F, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@@ -242,7 +242,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMUX2_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x0000200F, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@@ -254,7 +254,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_LBS_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002014, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -263,7 +263,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUDS_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002001, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@@ -275,7 +275,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUM_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002001, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@@ -287,7 +287,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUR_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002001, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@@ -299,7 +299,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUS0_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002001, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@@ -311,7 +311,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUS1_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002001, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@@ -323,7 +323,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MTSB0_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB0_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002002, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -332,7 +332,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MTSB1_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB1_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002002, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -341,7 +341,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_PCI_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_PCI_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002014, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -350,7 +350,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_RTX_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x0000200F, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@@ -362,7 +362,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_SDS0_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200A, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -371,7 +371,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_SDS1_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200A, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -380,7 +380,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_USB20_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002005, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -389,7 +389,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_USB21_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB21_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002005, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -398,7 +398,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_USB22_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002005, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -407,7 +407,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_USB30_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB30_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002014, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -417,7 +417,7 @@
writel(0x00000001, &axi_qos->qosqon);
/* QoS Register (RT-AXI) */
- axi_qos = (struct r8a7790_axi_qos *)RT_AXI_SHX_BASE;
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002005, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@@ -429,7 +429,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)RT_AXI_RDS_BASE;
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_RDS_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002007, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -438,7 +438,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)RT_AXI_RTX64TO128_BASE;
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x0000200F, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@@ -450,7 +450,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)RT_AXI_STPRO_BASE;
+ axi_qos = (struct rcar_axi_qos *)RT_AXI_STPRO_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002003, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@@ -463,7 +463,7 @@
writel(0x00000001, &axi_qos->qosqon);
/* QoS Register (MP-AXI) */
- axi_qos = (struct r8a7790_axi_qos *)MP_AXI_ADSP_BASE;
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002007, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -472,34 +472,34 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MP_AXI_ASDS0_BASE;
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002014, &axi_qos->qosctset0);
- writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00000040, &axi_qos->qosreqctr);
writel(0x00002006, &axi_qos->qosthres0);
writel(0x00002001, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MP_AXI_ASDS1_BASE;
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002014, &axi_qos->qosctset0);
- writel(0x00000001, &axi_qos->qosreqctr);
+ writel(0x00000040, &axi_qos->qosreqctr);
writel(0x00002006, &axi_qos->qosthres0);
writel(0x00002001, &axi_qos->qosthres1);
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MP_AXI_MLP_BASE;
- writel(0x00000000, &axi_qos->qosconf);
- writel(0x00002002, &axi_qos->qosctset0);
- writel(0x00000001, &axi_qos->qosreqctr);
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE;
+ writel(0x00000001, &axi_qos->qosconf);
+ writel(0x00001FF0, &axi_qos->qosctset0);
+ writel(0x00000020, &axi_qos->qosreqctr);
writel(0x00002006, &axi_qos->qosthres0);
writel(0x00002001, &axi_qos->qosthres1);
- writel(0x00000000, &axi_qos->qosthres2);
+ writel(0x00002001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MP_AXI_MMUMP_BASE;
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002001, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@@ -511,7 +511,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MP_AXI_SPU_BASE;
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -520,7 +520,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MP_AXI_SPUC_BASE;
+ axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200D, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -530,7 +530,7 @@
writel(0x00000001, &axi_qos->qosqon);
/* QoS Register (SYS-AXI256) */
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x0000200F, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@@ -542,7 +542,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI256_SYX_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x0000200F, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@@ -554,7 +554,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI256_MPX_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x0000200F, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@@ -566,7 +566,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)SYS_AXI256_MXI_BASE;
+ axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x0000200F, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@@ -579,7 +579,7 @@
writel(0x00000001, &axi_qos->qosqon);
/* QoS Register (CCI-AXI) */
- axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUS0_BASE;
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002001, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@@ -591,7 +591,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_SYX2_BASE;
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x0000200F, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@@ -603,7 +603,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUR_BASE;
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002001, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@@ -615,7 +615,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUDS_BASE;
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002001, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@@ -627,7 +627,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUM_BASE;
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002001, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@@ -639,7 +639,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MXI_BASE;
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
writel(0x00000002, &axi_qos->qosconf);
writel(0x0000200F, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@@ -651,7 +651,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUS1_BASE;
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002001, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@@ -663,7 +663,7 @@
writel(0x00000000, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUMP_BASE;
+ axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002001, &axi_qos->qosctset0);
writel(0x00002009, &axi_qos->qosctset1);
@@ -676,7 +676,7 @@
writel(0x00000001, &axi_qos->qosqon);
/* QoS Register (Media-AXI) */
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_JPR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -685,7 +685,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_JPW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -694,7 +694,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_GCU0R_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU0R_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -703,7 +703,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_GCU0W_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU0W_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -712,7 +712,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_GCU1R_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU1R_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -721,7 +721,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_GCU1W_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU1W_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -730,7 +730,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_TDMR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -739,7 +739,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_TDMW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -748,7 +748,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP0CR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0CR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -757,7 +757,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP0CW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0CW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -766,7 +766,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -775,7 +775,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -784,7 +784,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -793,7 +793,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -802,7 +802,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -811,7 +811,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002018, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -820,7 +820,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -829,7 +829,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP0R_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0R_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -838,7 +838,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP0W_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0W_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -847,7 +847,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP0R_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -856,7 +856,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP0W_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -865,7 +865,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_IMSR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -874,7 +874,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_IMSW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -883,7 +883,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP1R_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -892,7 +892,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP1W_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -901,7 +901,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP1R_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1R_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -910,7 +910,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP1W_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1W_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -919,7 +919,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_IMRR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -928,7 +928,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_IMRW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -937,7 +937,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP2R_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP2R_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -946,7 +946,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP2W_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP2W_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -955,7 +955,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -964,7 +964,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -973,7 +973,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -982,7 +982,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -991,7 +991,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_DU0R_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -1000,7 +1000,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_DU0W_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -1009,7 +1009,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_DU1R_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU1R_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -1018,7 +1018,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_DU1W_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU1W_BASE;
writel(0x00000000, &axi_qos->qosconf);
writel(0x0000200C, &axi_qos->qosctset0);
writel(0x00000001, &axi_qos->qosreqctr);
@@ -1027,7 +1027,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002007, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -1036,7 +1036,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002007, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -1045,7 +1045,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002007, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -1054,7 +1054,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002007, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -1063,7 +1063,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VPC0R_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002007, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -1072,7 +1072,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP1CR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1CR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002007, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -1081,7 +1081,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP1CW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1CW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002007, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -1090,7 +1090,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP1VR_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1VR_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002007, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -1099,7 +1099,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP1VW_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1VW_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002007, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
@@ -1108,7 +1108,7 @@
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
- axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VPC1R_BASE;
+ axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC1R_BASE;
writel(0x00000001, &axi_qos->qosconf);
writel(0x00002007, &axi_qos->qosctset0);
writel(0x00000020, &axi_qos->qosreqctr);
diff --git a/boards.cfg b/boards.cfg
index dcc2014..7e84b9b 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -371,7 +371,6 @@
Active arm armv7 rmobile atmark-techno armadillo-800eva armadillo-800eva - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Active arm armv7 rmobile kmc kzm9g kzm9g - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>:Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Active arm armv7 rmobile renesas koelsch koelsch - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
-Active arm armv7 rmobile renesas koelsch koelsch_nor koelsch:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Active arm armv7 rmobile renesas lager lager - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Active arm armv7 rmobile renesas lager lager_nor lager:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Active arm armv7 s5pc1xx samsung goni s5p_goni - Przemyslaw Marczak <p.marczak@samsung.com>
diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h
index 90e2d7a0..1a93d17 100644
--- a/include/configs/koelsch.h
+++ b/include/configs/koelsch.h
@@ -32,15 +32,9 @@
#define CONFIG_CMD_NFS
#define CONFIG_CMD_BOOTZ
-#if defined(CONFIG_SYS_USE_BOOT_NORFLASH)
-#define CONFIG_CMD_FLASH
-#define CONFIG_SYS_TEXT_BASE 0x00000000
-#else
-/* SPI flash boot is default. */
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_SYS_TEXT_BASE 0xE6304000
-#endif
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
@@ -109,29 +103,6 @@
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* FLASH */
-#if defined(CONFIG_SYS_USE_BOOT_NORFLASH)
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-#define CONFIG_FLASH_SHOW_PROGRESS 45
-#define CONFIG_SYS_FLASH_BASE 0x00000000
-#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) }
-#define CONFIG_SYS_FLASH_BANKS_SIZES { (CONFIG_SYS_FLASH_SIZE) }
-#define CONFIG_SYS_FLASH_ERASE_TOUT 3000
-#define CONFIG_SYS_FLASH_WRITE_TOUT 3000
-#define CONFIG_SYS_FLASH_LOCK_TOUT 3000
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT 3000
-/* ENV setting */
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
- CONFIG_SYS_MONITOR_LEN)
-
-#else /* CONFIG_SYS_USE_BOOT_NORFLASH */
-
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SPI
#define CONFIG_SH_QSPI
@@ -142,8 +113,6 @@
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_ADDR 0xC0000
-#endif /* CONFIG_SYS_USE_BOOT_NORFLASH */
-
/* Common ENV setting */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_SECT_SIZE (256 * 1024)
@@ -166,8 +135,9 @@
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ 10000000
-#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define RMOBILE_XTAL_CLK 20000000u
+#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
+#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
#define CONFIG_SH_SCIF_CLK_FREQ 14745600
#define CONFIG_SYS_TMU_CLK_DIV 4
diff --git a/include/configs/lager.h b/include/configs/lager.h
index b420e45..ac31128 100644
--- a/include/configs/lager.h
+++ b/include/configs/lager.h
@@ -16,8 +16,6 @@
#define CONFIG_RMOBILE
#define CONFIG_RMOBILE_BOARD_STRING "Lager"
#define CONFIG_SH_GPIO_PFC
-#define MACH_TYPE_LAGER 4538
-#define CONFIG_MACH_TYPE MACH_TYPE_LAGER
#include <asm/arch/rmobile.h>
@@ -35,14 +33,9 @@
#define CONFIG_CMD_NFS
#define CONFIG_CMD_BOOTZ
-#if defined(CONFIG_SYS_USE_BOOT_NORFLASH)
-#define CONFIG_CMD_FLASH
-#define CONFIG_SYS_TEXT_BASE 0x00000000
-#else
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_SYS_TEXT_BASE 0xE8080000
-#endif
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
@@ -111,31 +104,6 @@
#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
-#if defined(CONFIG_SYS_USE_BOOT_NORFLASH)
-/* USE NOR FLASH */
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
-#define CONFIG_FLASH_SHOW_PROGRESS 45
-#define CONFIG_SYS_FLASH_BASE 0x00000000
-#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) }
-#define CONFIG_SYS_FLASH_BANKS_SIZES { (CONFIG_SYS_FLASH_SIZE) }
-#define CONFIG_SYS_FLASH_ERASE_TOUT 3000
-#define CONFIG_SYS_FLASH_WRITE_TOUT 3000
-#define CONFIG_SYS_FLASH_LOCK_TOUT 3000
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT 3000
-
-/* ENV setting */
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
- CONFIG_SYS_MONITOR_LEN)
-
-#else /* CONFIG_SYS_USE_BOOT_NORFLASH */
-
/* USE SPI */
#define CONFIG_SPI
#define CONFIG_SPI_FLASH_BAR
@@ -147,7 +115,6 @@
/* ENV setting */
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_ADDR 0xC0000
-#endif
/* Common ENV setting */
#define CONFIG_ENV_OVERWRITE
@@ -186,9 +153,10 @@
#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
/* Board Clock */
-#define CONFIG_BASE_CLK_FREQ 20000000u
-#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_BASE_CLK_FREQ / 2) /* EXT / 2 */
-#define CONFIG_PLL1_CLK_FREQ (CONFIG_BASE_CLK_FREQ * 156 / 2)
+#define RMOBILE_XTAL_CLK 20000000u
+#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
+#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
+#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
#define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2)
#define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15)
#define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12)