blackfin: bf60x: Port blackfin core architecture code to boot on bf60x.
Set up clocks, DDR controller, Nor flash controller, reboot,
serial port. Add new SPI boot modes.
Signed-off-by: Bob Liu <lliubbo@gmail.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>
diff --git a/arch/blackfin/cpu/reset.c b/arch/blackfin/cpu/reset.c
index ff39035..b6718d3 100644
--- a/arch/blackfin/cpu/reset.c
+++ b/arch/blackfin/cpu/reset.c
@@ -23,6 +23,7 @@
__attribute__ ((__l1_text__, __noreturn__))
static void bfin_reset(void)
{
+#ifdef SWRST
/* Wait for completion of "system" events such as cache line
* line fills so that we avoid infinite stalls later on as
* much as possible. This code is in L1, so it won't trigger
@@ -66,10 +67,15 @@
: "a" (15 * 1)
: "LC1", "LB1", "LT1"
);
+#endif
while (1)
+#if defined(__ADSPBF60x__)
+ bfin_write_RCU0_CTL(0x1);
+#else
/* Issue core reset */
asm("raise 1");
+#endif
}
/* We need to trampoline ourselves up into L1 since our linker