| commit | a2c95a72247990dee9a03b26b4dc9fc0182c97ed | [log] [tgz] |
|---|---|---|
| author | Stefan Roese <sr@denx.de> | Fri Jul 28 18:34:58 2006 +0200 |
| committer | Stefan Roese <sr@denx.de> | Fri Jul 28 18:34:58 2006 +0200 |
| tree | cabdaa860480f895cccc6600f3454a751329c13c | |
| parent | fc6c4a67ae94adac02da6257a0f5adc3bd48ebec [diff] |
PPC440 DDR setup: Set SDRAM0_CFG0[PMU]=0 for best performance AMCC suggested to set the PMU bit to 0 for best performace on the PPC440 DDR controller. Please see doc/README.440-DDR-performance for details. Patch by Stefan Roese, 28 Jul 2006