x86: Add Intel Cougar Canyon 2 board
This adds basic support to Intel Cougar Canyon 2 board, a board
based on Chief River platform with an Ivy Bridge processor and
a Panther Point chipset.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig
index b9f290a..0819347 100644
--- a/arch/x86/cpu/ivybridge/Kconfig
+++ b/arch/x86/cpu/ivybridge/Kconfig
@@ -79,4 +79,8 @@
bool
default n
+config FSP_BROKEN_HOB
+ bool
+ default y
+
endif
diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
index 64e5694..84feb19 100644
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@@ -5,6 +5,7 @@
dtb-y += bayleybay.dtb \
chromebook_link.dtb \
chromebox_panther.dtb \
+ cougarcanyon2.dtb \
crownbay.dtb \
efi.dtb \
galileo.dtb \
diff --git a/arch/x86/dts/cougarcanyon2.dts b/arch/x86/dts/cougarcanyon2.dts
new file mode 100644
index 0000000..d415566
--- /dev/null
+++ b/arch/x86/dts/cougarcanyon2.dts
@@ -0,0 +1,104 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+/include/ "serial.dtsi"
+/include/ "keyboard.dtsi"
+/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"
+
+/ {
+ model = "Intel Cougar Canyon 2";
+ compatible = "intel,cougarcanyon2", "intel,chiefriver";
+
+ aliases {
+ spi0 = &spi0;
+ };
+
+ config {
+ silent_console = <0>;
+ };
+
+ chosen {
+ stdout-path = "/serial";
+ };
+
+ microcode {
+ update@0 {
+#include "microcode/m12306a2_00000008.dtsi"
+ };
+ update@1 {
+#include "microcode/m12306a4_00000007.dtsi"
+ };
+ update@2 {
+#include "microcode/m12306a5_00000007.dtsi"
+ };
+ update@3 {
+#include "microcode/m12306a8_00000010.dtsi"
+ };
+ update@4 {
+#include "microcode/m12306a9_0000001b.dtsi"
+ };
+ };
+
+ fsp {
+ compatible = "intel,ivybridge-fsp";
+ fsp,enable-ht;
+ };
+
+ pci {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ compatible = "pci-x86";
+ u-boot,dm-pre-reloc;
+ ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
+ 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
+ 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
+
+ pch@1f,0 {
+ reg = <0x0000f800 0 0 0 0>;
+ compatible = "intel,bd82x6x";
+ u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ spi0: spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "intel,ich9-spi";
+ spi-flash@0 {
+ reg = <0>;
+ compatible = "winbond,w25q64bv", "spi-flash";
+ memory-map = <0xff800000 0x00800000>;
+ };
+ };
+
+ gpioa {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0 0x10>;
+ bank-name = "A";
+ };
+
+ gpiob {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0x30 0x10>;
+ bank-name = "B";
+ };
+
+ gpioc {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0x40 0x10>;
+ bank-name = "C";
+ };
+ };
+ };
+
+};