imx:display5: Add support for LWN's DISPLAY5 board
This commit provides support for LWN's IMX6Q based DISPLAY5 board.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
diff --git a/board/liebherr/display5/Kconfig b/board/liebherr/display5/Kconfig
new file mode 100644
index 0000000..b096c89
--- /dev/null
+++ b/board/liebherr/display5/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_DISPLAY5
+
+config SYS_CPU
+ default "armv7"
+
+config SYS_BOARD
+ default "display5"
+
+config SYS_VENDOR
+ default "liebherr"
+
+config SYS_SOC
+ default "mx6"
+
+config SYS_CONFIG_NAME
+ default "display5"
+
+endif
diff --git a/board/liebherr/display5/MAINTAINERS b/board/liebherr/display5/MAINTAINERS
new file mode 100644
index 0000000..5217831
--- /dev/null
+++ b/board/liebherr/display5/MAINTAINERS
@@ -0,0 +1,7 @@
+DISPLAY5 BOARD
+M: Lukasz Majewski <lukma@denx.de>
+S: Maintained
+F: board/liebherr/display5/
+F: include/configs/display5.h
+F: configs/display5_defconfig
+F: configs/display5_factory_defconfig
diff --git a/board/liebherr/display5/Makefile b/board/liebherr/display5/Makefile
new file mode 100644
index 0000000..f934672
--- /dev/null
+++ b/board/liebherr/display5/Makefile
@@ -0,0 +1,11 @@
+#
+# Copyright (C) 2017, DENX Software Engineering
+# Lukasz Majewski <lukma@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+ifdef CONFIG_SPL_BUILD
+obj-y = common.o spl.o
+else
+obj-y := common.o display5.o
+endif
diff --git a/board/liebherr/display5/common.c b/board/liebherr/display5/common.c
new file mode 100644
index 0000000..03f585b
--- /dev/null
+++ b/board/liebherr/display5/common.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) 2017 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/arch/mx6-pins.h>
+#include "common.h"
+
+iomux_v3_cfg_t const uart_pads[] = {
+ /* UART4 */
+ MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT16__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT17__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const uart_console_pads[] = {
+ /* UART5 */
+ MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT18__UART5_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT19__UART5_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+void displ5_set_iomux_uart_spl(void)
+{
+ SETUP_IOMUX_PADS(uart_console_pads);
+}
+
+void displ5_set_iomux_uart(void)
+{
+ SETUP_IOMUX_PADS(uart_pads);
+}
+
+#ifdef CONFIG_MXC_SPI
+iomux_v3_cfg_t const ecspi_pads[] = {
+ /* SPI3 */
+ MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_DISP0_DAT3__ECSPI3_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT4__ECSPI3_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT5__ECSPI3_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT6__ECSPI3_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT7__ECSPI3_RDY | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const ecspi2_pads[] = {
+ /* SPI2, NOR Flash nWP, CS0 */
+ MX6_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_CSI0_DAT11__GPIO5_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
+{
+ if (bus != 1 || cs != (IMX_GPIO_NR(5, 29) << 8))
+ return -EINVAL;
+
+ return IMX_GPIO_NR(5, 29);
+}
+
+void displ5_set_iomux_ecspi_spl(void)
+{
+ SETUP_IOMUX_PADS(ecspi2_pads);
+}
+
+void displ5_set_iomux_ecspi(void)
+{
+ SETUP_IOMUX_PADS(ecspi_pads);
+}
+
+#else
+void displ5_set_iomux_ecspi_spl(void) {}
+void displ5_set_iomux_ecspi(void) {}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+iomux_v3_cfg_t const usdhc4_pads[] = {
+ MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_ALE__SD4_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+void displ5_set_iomux_usdhc_spl(void)
+{
+ SETUP_IOMUX_PADS(usdhc4_pads);
+}
+
+void displ5_set_iomux_usdhc(void)
+{
+ SETUP_IOMUX_PADS(usdhc4_pads);
+}
+
+#else
+void displ5_set_iomux_usdhc_spl(void) {}
+void displ5_set_iomux_usdhc(void) {}
+#endif
diff --git a/board/liebherr/display5/common.h b/board/liebherr/display5/common.h
new file mode 100644
index 0000000..6019e90
--- /dev/null
+++ b/board/liebherr/display5/common.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2017 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DISPL5_COMMON_H_
+#define __DISPL5_COMMON_H_
+
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | \
+ PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
+ PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+void displ5_set_iomux_uart_spl(void);
+void displ5_set_iomux_uart(void);
+void displ5_set_iomux_ecspi_spl(void);
+void displ5_set_iomux_ecspi(void);
+void displ5_set_iomux_usdhc_spl(void);
+void displ5_set_iomux_usdhc(void);
+
+#endif /* __DISPL5_COMMON_H_ */
diff --git a/board/liebherr/display5/display5.c b/board/liebherr/display5/display5.c
new file mode 100644
index 0000000..5414ef7
--- /dev/null
+++ b/board/liebherr/display5/display5.c
@@ -0,0 +1,384 @@
+/*
+ * Copyright (C) 2017 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/sys_proto.h>
+#include <errno.h>
+#include <asm/gpio.h>
+#include <malloc.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/spi.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <i2c.h>
+
+#include <dm.h>
+#include <dm/platform_data/serial_mxc.h>
+#include <dm/platdata.h>
+
+#ifndef CONFIG_MXC_SPI
+#error "CONFIG_SPI must be set for this board"
+#error "Please check your config file"
+#endif
+
+#include "common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static bool hw_ids_valid;
+static bool sw_ids_valid;
+static u32 cpu_id;
+static u32 unit_id;
+
+#define SW0 IMX_GPIO_NR(2, 4)
+#define SW1 IMX_GPIO_NR(2, 5)
+#define SW2 IMX_GPIO_NR(2, 6)
+#define SW3 IMX_GPIO_NR(2, 7)
+#define HW0 IMX_GPIO_NR(6, 7)
+#define HW1 IMX_GPIO_NR(6, 9)
+#define HW2 IMX_GPIO_NR(6, 10)
+#define HW3 IMX_GPIO_NR(6, 11)
+#define HW4 IMX_GPIO_NR(4, 7)
+#define HW5 IMX_GPIO_NR(4, 11)
+#define HW6 IMX_GPIO_NR(4, 13)
+#define HW7 IMX_GPIO_NR(4, 15)
+
+int gpio_table_sw_ids[] = {
+ SW0, SW1, SW2, SW3
+};
+
+const char *gpio_table_sw_ids_names[] = {
+ "sw0", "sw1", "sw2", "sw3"
+};
+
+int gpio_table_hw_ids[] = {
+ HW0, HW1, HW2, HW3, HW4, HW5, HW6, HW7
+};
+
+const char *gpio_table_hw_ids_names[] = {
+ "hw0", "hw1", "hw2", "hw3", "hw4", "hw5", "hw6", "hw7"
+};
+
+static int get_board_id(int *ids, const char **c, int size,
+ bool *valid, u32 *id)
+{
+ int i, ret, val;
+
+ *valid = false;
+
+ for (i = 0; i < size; i++) {
+ ret = gpio_request(ids[i], c[i]);
+ if (ret) {
+ printf("Can't request SWx gpios\n");
+ return ret;
+ }
+ }
+
+ for (i = 0; i < size; i++) {
+ ret = gpio_direction_input(ids[i]);
+ if (ret) {
+ printf("Can't set SWx gpios direction\n");
+ return ret;
+ }
+ }
+
+ for (i = 0; i < size; i++) {
+ val = gpio_get_value(ids[i]);
+ if (val < 0) {
+ printf("Can't get SW%d ID\n", i);
+ *id = 0;
+ return val;
+ }
+ *id |= val << i;
+ }
+ *valid = true;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+
+ return 0;
+}
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C1: TFA9879 */
+struct i2c_pads_info i2c_pad_info0 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
+ .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
+ .gp = IMX_GPIO_NR(3, 21)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
+ .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
+ .gp = IMX_GPIO_NR(3, 28)
+ }
+};
+
+/* I2C2: TIVO TM4C123 */
+struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
+ .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
+ .gp = IMX_GPIO_NR(2, 30)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC,
+ .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
+ .gp = IMX_GPIO_NR(3, 16)
+ }
+};
+
+/* I2C3: PMIC PF0100, EEPROM AT24C256C */
+struct i2c_pads_info i2c_pad_info2 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
+ .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
+ .gp = IMX_GPIO_NR(3, 17)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
+ .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
+ .gp = IMX_GPIO_NR(3, 18)
+ }
+};
+
+iomux_v3_cfg_t const misc_pads[] = {
+ /* Prod ID GPIO pins */
+ MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+ /* HW revision GPIO pins */
+ MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+ /* XTALOSC */
+ MX6_PAD_GPIO_3__XTALOSC_REF_CLK_24M | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg[1] = {
+ { USDHC4_BASE_ADDR, 0, 8, },
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ displ5_set_iomux_usdhc();
+
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif /* CONFIG_FSL_ESDHC */
+
+static void displ5_setup_ecspi(void)
+{
+ int ret;
+
+ displ5_set_iomux_ecspi();
+
+ ret = gpio_request(IMX_GPIO_NR(5, 29), "spi2_cs0");
+ if (!ret)
+ gpio_direction_output(IMX_GPIO_NR(5, 29), 1);
+
+ ret = gpio_request(IMX_GPIO_NR(7, 0), "spi2_#wp");
+ if (!ret)
+ gpio_direction_output(IMX_GPIO_NR(7, 0), 1);
+}
+
+#ifdef CONFIG_FEC_MXC
+iomux_v3_cfg_t const enet_pads[] = {
+ MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+
+ /* for old evalboard with R159 present and R160 not populated */
+ MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+ MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+
+ MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ /*INT#_GBE*/
+ MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_enet(void)
+{
+ SETUP_IOMUX_PADS(enet_pads);
+ gpio_direction_input(IMX_GPIO_NR(1, 28)); /*INT#_GBE*/
+}
+
+int board_eth_init(bd_t *bd)
+{
+ struct phy_device *phydev;
+ struct mii_dev *bus;
+ int ret;
+
+ setup_iomux_enet();
+
+ iomuxc_set_rgmii_io_voltage(DDR_SEL_1P5V_IO);
+
+ ret = enable_fec_anatop_clock(0, ENET_125MHZ);
+ if (ret)
+ return ret;
+
+ bus = fec_get_miibus(IMX_FEC_BASE, -1);
+ if (!bus)
+ return -ENODEV;
+
+ /*
+ * We use here the "rgmii-id" mode of operation and allow M88E1512
+ * PHY to use its internally callibrated RX/TX delays
+ */
+ phydev = phy_find_by_mask(bus, 0xffffffff /* (0xf << 4) */,
+ PHY_INTERFACE_MODE_RGMII_ID);
+ if (!phydev) {
+ ret = -ENODEV;
+ goto err_phy;
+ }
+
+ /* display5 due to PCB routing can only work with 100 Mbps */
+ phydev->advertising &= ~(ADVERTISED_1000baseX_Half |
+ ADVERTISED_1000baseX_Full |
+ SUPPORTED_1000baseT_Half |
+ SUPPORTED_1000baseT_Full);
+
+ ret = fec_probe(bd, -1, IMX_FEC_BASE, bus, phydev);
+ if (ret)
+ goto err_sw;
+
+ return 0;
+
+err_sw:
+ free(phydev);
+err_phy:
+ mdio_unregister(bus);
+ free(bus);
+ return ret;
+}
+#endif /* CONFIG_FEC_MXC */
+
+/*
+ * Do not overwrite the console
+ * Always use serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+ return 1;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ fdt_fixup_ethernet(blob);
+ return 0;
+}
+#endif
+
+int board_init(void)
+{
+ debug("board init\n");
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ /* Setup iomux for non console UARTS */
+ displ5_set_iomux_uart();
+
+ displ5_setup_ecspi();
+
+ SETUP_IOMUX_PADS(misc_pads);
+
+ get_board_id(gpio_table_sw_ids, &gpio_table_sw_ids_names[0],
+ ARRAY_SIZE(gpio_table_sw_ids), &sw_ids_valid, &unit_id);
+ debug("SWx unit_id 0x%x\n", unit_id);
+
+ get_board_id(gpio_table_hw_ids, &gpio_table_hw_ids_names[0],
+ ARRAY_SIZE(gpio_table_hw_ids), &hw_ids_valid, &cpu_id);
+ debug("HWx cpu_id 0x%x\n", cpu_id);
+
+ if (hw_ids_valid && sw_ids_valid)
+ printf("ID: unit type 0x%x rev 0x%x\n", unit_id, cpu_id);
+
+ udelay(25);
+
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ /* eMMC, USDHC-4, 8-bit bus width */
+ /* SPI-NOR, ECSPI-2 SS0, 3-bytes addressing */
+ {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
+ {"spinor", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x09)},
+ {NULL, 0},
+};
+
+static void setup_boot_modes(void)
+{
+ add_board_boot_modes(board_boot_modes);
+}
+#else
+static inline void setup_boot_modes(void) {}
+#endif
+
+int misc_init_r(void)
+{
+ setup_boot_modes();
+ return 0;
+}
+
+static struct mxc_serial_platdata mxc_serial_plat = {
+ .reg = (struct mxc_uart *)UART5_BASE,
+};
+
+U_BOOT_DEVICE(mxc_serial) = {
+ .name = "serial_mxc",
+ .platdata = &mxc_serial_plat,
+};
diff --git a/board/liebherr/display5/spl.c b/board/liebherr/display5/spl.c
new file mode 100644
index 0000000..0a36e65
--- /dev/null
+++ b/board/liebherr/display5/spl.c
@@ -0,0 +1,247 @@
+/*
+ * Copyright (C) 2017 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <libfdt.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include "asm/arch/crm_regs.h"
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/imx-regs.h>
+#include "asm/arch/iomux.h"
+#include <asm/mach-imx/iomux-v3.h>
+#include <environment.h>
+#include <fsl_esdhc.h>
+#include <netdev.h>
+#include "common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
+ .dram_sdclk_0 = 0x00000030,
+ .dram_sdclk_1 = 0x00000030,
+ .dram_cas = 0x00000030,
+ .dram_ras = 0x00000030,
+ .dram_reset = 0x00000030,
+ .dram_sdcke0 = 0x00003000,
+ .dram_sdcke1 = 0x00003000,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdodt0 = 0x00000030,
+ .dram_sdodt1 = 0x00000030,
+
+ .dram_sdqs0 = 0x00000030,
+ .dram_sdqs1 = 0x00000030,
+ .dram_sdqs2 = 0x00000030,
+ .dram_sdqs3 = 0x00000030,
+ .dram_sdqs4 = 0x00000030,
+ .dram_sdqs5 = 0x00000030,
+ .dram_sdqs6 = 0x00000030,
+ .dram_sdqs7 = 0x00000030,
+
+ .dram_dqm0 = 0x00000030,
+ .dram_dqm1 = 0x00000030,
+ .dram_dqm2 = 0x00000030,
+ .dram_dqm3 = 0x00000030,
+ .dram_dqm4 = 0x00000030,
+ .dram_dqm5 = 0x00000030,
+ .dram_dqm6 = 0x00000030,
+ .dram_dqm7 = 0x00000030,
+};
+
+static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
+ .grp_ddr_type = 0x000c0000,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_ddrpke = 0x00000000,
+ .grp_addds = 0x00000030,
+ .grp_ctlds = 0x00000030,
+ .grp_ddrmode = 0x00020000,
+ .grp_b0ds = 0x00000030,
+ .grp_b1ds = 0x00000030,
+ .grp_b2ds = 0x00000030,
+ .grp_b3ds = 0x00000030,
+ .grp_b4ds = 0x00000030,
+ .grp_b5ds = 0x00000030,
+ .grp_b6ds = 0x00000030,
+ .grp_b7ds = 0x00000030,
+};
+
+/* 4x128Mx16.cfg */
+static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = {
+ .p0_mpwldectrl0 = 0x002D0028,
+ .p0_mpwldectrl1 = 0x0032002D,
+ .p1_mpwldectrl0 = 0x00210036,
+ .p1_mpwldectrl1 = 0x0019002E,
+ .p0_mpdgctrl0 = 0x4349035C,
+ .p0_mpdgctrl1 = 0x0348033D,
+ .p1_mpdgctrl0 = 0x43550362,
+ .p1_mpdgctrl1 = 0x03520316,
+ .p0_mprddlctl = 0x41393940,
+ .p1_mprddlctl = 0x3F3A3C47,
+ .p0_mpwrdlctl = 0x413A423A,
+ .p1_mpwrdlctl = 0x4042483E,
+};
+
+/* MT41K128M16JT-125 (2Gb density) */
+static const struct mx6_ddr3_cfg mt41k128m16jt_125 = {
+ .mem_speed = 1600,
+ .density = 2,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 14,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+};
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0x00C03F3F, &ccm->CCGR0);
+ writel(0x0030FC3F, &ccm->CCGR1);
+ writel(0x0FFFCFC0, &ccm->CCGR2);
+ writel(0x3FF00000, &ccm->CCGR3);
+ writel(0x00FFF300, &ccm->CCGR4);
+ writel(0x0F0000C3, &ccm->CCGR5);
+ writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void spl_dram_init(void)
+{
+ struct mx6_ddr_sysinfo sysinfo = {
+ /* width of data bus:0=16,1=32,2=64 */
+ .dsize = 2,
+ /* config for full 4GB range so that get_mem_size() works */
+ .cs_density = 32, /* 32Gb per CS */
+ /* single chip select */
+ .ncs = 1,
+ .cs1_mirror = 0,
+ .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
+ .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
+ .walat = 1, /* Write additional latency */
+ .ralat = 5, /* Read additional latency */
+ .mif3_mode = 3, /* Command prediction working mode */
+ .bi_on = 1, /* Bank interleaving enabled */
+ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
+ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+ .pd_fast_exit = 1, /* enable precharge power-down fast exit */
+ .ddr_type = DDR_TYPE_DDR3,
+ .refsel = 1, /* Refresh cycles at 32KHz */
+ .refr = 7, /* 8 refresh commands per refresh cycle */
+ };
+
+ mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+ mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k128m16jt_125);
+}
+
+#ifdef CONFIG_SPL_SPI_SUPPORT
+static void displ5_init_ecspi(void)
+{
+ displ5_set_iomux_ecspi_spl();
+ enable_spi_clk(1, 1);
+}
+#else
+static inline void displ5_init_ecspi(void) { }
+#endif
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+static struct fsl_esdhc_cfg usdhc_cfg = {
+ .esdhc_base = USDHC4_BASE_ADDR,
+ .max_bus_width = 8,
+};
+
+int board_mmc_init(bd_t *bd)
+{
+ displ5_set_iomux_usdhc_spl();
+
+ usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+ gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
+
+ return fsl_esdhc_initialize(bd, &usdhc_cfg);
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+ ccgr_init();
+
+ arch_cpu_init();
+
+ gpr_init();
+
+ /* setup GP timer */
+ timer_init();
+
+ displ5_set_iomux_uart_spl();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ displ5_init_ecspi();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+ /* Default boot sequence SPI -> MMC */
+ spl_boot_list[0] = spl_boot_device();
+ spl_boot_list[1] = BOOT_DEVICE_MMC1;
+ spl_boot_list[2] = BOOT_DEVICE_UART;
+ spl_boot_list[3] = BOOT_DEVICE_NONE;
+
+#ifdef CONFIG_SPL_ENV_SUPPORT
+ /* 'fastboot' */
+ const char *s;
+
+ env_init();
+ env_load();
+
+ s = env_get("BOOT_FROM");
+ if (s && strcmp(s, "ACTIVE") == 0) {
+ spl_boot_list[0] = BOOT_DEVICE_MMC1;
+ spl_boot_list[1] = spl_boot_device();
+ }
+#endif
+}
+
+void reset_cpu(ulong addr) {}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_OS_BOOT
+/* Return: 1 - boot to U-Boot. 0 - boot OS (falcon mode) */
+int spl_start_uboot(void)
+{
+ /* break into full u-boot on 'c' */
+ if (serial_tstc() && serial_getc() == 'c')
+ return 1;
+
+#ifdef CONFIG_SPL_ENV_SUPPORT
+ if (env_get_yesno("boot_os") != 1)
+ return 1;
+#endif
+ return 0;
+}
+#endif