commit a4110eecf2944b2f8b47f38273cc3730ddd394a3
author Alison Wang <b18965@freescale.com> Mon Mar 26 21:49:07 2012 +0000
committer jason <jason@jason-ThinkPad-T61.(none)> Thu Sep 20 20:39:27 2012 +0800
tree db4abd654d8248d1c191e732c6e144abf86bd701
parent c6d88630158af79f5700c8bbc37972f511e84500

ColdFire: Clean up checkpatch warnings for MCF547x and MCF548x

Signed-off-by: Alison Wang <b18965@freescale.com>

board/freescale/m547xevb/m547xevb.c

diff --git a/board/freescale/m547xevb/m547xevb.c b/board/freescale/m547xevb/m547xevb.c
index 9f1ec38..fd9bddd 100644
--- a/board/freescale/m547xevb/m547xevb.c
+++ b/board/freescale/m547xevb/m547xevb.c
@@ -2,7 +2,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -28,6 +28,7 @@
 #include <common.h>
 #include <pci.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -40,14 +41,14 @@
 
 phys_size_t initdram(int board_type)
 {
-	volatile siu_t *siu = (siu_t *) (MMAP_SIU);
-	volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+	siu_t *siu = (siu_t *) (MMAP_SIU);
+	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
 	u32 dramsize, i;
 #ifdef CONFIG_SYS_DRAMSZ1
 	u32 temp;
 #endif
 
-	siu->drv = CONFIG_SYS_SDRAM_DRVSTRENGTH;
+	out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH);
 
 	dramsize = CONFIG_SYS_DRAMSZ * 0x100000;
 	for (i = 0x13; i < 0x20; i++) {
@@ -55,7 +56,7 @@
 			break;
 	}
 	i--;
-	siu->cs0cfg = (CONFIG_SYS_SDRAM_BASE | i);
+	out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE | i);
 
 #ifdef CONFIG_SYS_DRAMSZ1
 	temp = CONFIG_SYS_DRAMSZ1 * 0x100000;
@@ -65,31 +66,32 @@
 	}
 	i--;
 	dramsize += temp;
-	siu->cs1cfg = ((CONFIG_SYS_SDRAM_BASE + temp) | i);
+	out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) | i);
 #endif
 
-	sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
-	sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+	out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+	out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
 
 	/* Issue PALL */
-	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
 
 	/* Issue LEMR */
-	sdram->mode = CONFIG_SYS_SDRAM_EMOD;
-	sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
 
 	udelay(500);
 
 	/* Issue PALL */
-	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
 
 	/* Perform two refresh cycles */
-	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
-	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
 
-	sdram->mode = CONFIG_SYS_SDRAM_MODE;
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
 
-	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
+	out_be32(&sdram->ctrl,
+		(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
 
 	udelay(100);