| commit | a4aa9b7522dc67745795c1e2a76115a616da00ea | [log] [tgz] |
|---|---|---|
| author | Takahiro Kuwano <Takahiro.Kuwano@infineon.com> | Tue Jun 29 15:00:59 2021 +0900 |
| committer | Jagan Teki <jagan@amarulasolutions.com> | Tue Jun 29 19:16:54 2021 +0530 |
| tree | 537eb3eb31207ffe61a8f3d74cc1e21088b0ea8b | |
| parent | 2d20f344858265722452d06fe7a5f86ca736b86d [diff] |
mtd: spi-nor-core: Add support for volatile QE bit Some of Spansion/Cypress chips support volatile version of configuration registers and it is recommended to update volatile registers in the field application due to a risk of the non-volatile registers corruption by power interrupt. This patch adds a function to set Quad Enable bit in CFR1 volatile. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>