Merge tag 'rockchip-for-v2018.11-rc2' of git://git.denx.de/u-boot-rockchip
Rockchip-focused changes for v2018.11-rc2:
- fixes to rkimage for SPL boot via USB
- fixes to make_fit_atf.py, incl. entry-point calculation and python3
compatibility
- OP-TEE support for ARMv7-based SoCs
- fixes to RGMII/GMII selection on the RK3328
Signed-off-by: Tom Rini <trini@konsulko.com>
diff --git a/Makefile b/Makefile
index 73a080c..1d7d5f2 100644
--- a/Makefile
+++ b/Makefile
@@ -1074,7 +1074,10 @@
else
ifneq ($(CONFIG_SPL_FIT_GENERATOR),"")
U_BOOT_ITS := u-boot.its
-$(U_BOOT_ITS): FORCE
+ifeq ($(CONFIG_SPL_FIT_GENERATOR),"arch/arm/mach-rockchip/make_fit_atf.py")
+U_BOOT_ITS_DEPS += u-boot
+endif
+$(U_BOOT_ITS): $(U_BOOT_ITS_DEPS) FORCE
$(srctree)/$(CONFIG_SPL_FIT_GENERATOR) \
$(patsubst %,arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) > $@
endif
diff --git a/arch/arm/mach-rockchip/fit_spl_optee.its b/arch/arm/mach-rockchip/fit_spl_optee.its
new file mode 100644
index 0000000..9be4b3c
--- /dev/null
+++ b/arch/arm/mach-rockchip/fit_spl_optee.its
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2017 Rockchip Electronic Co.,Ltd
+ *
+ * Simple U-boot fit source file containing U-Boot, dtb and optee
+ */
+
+/dts-v1/;
+
+/ {
+ description = "Simple image with OP-TEE support";
+ #address-cells = <1>;
+
+ images {
+ uboot@1 {
+ description = "U-Boot";
+ data = /incbin/("../../../u-boot-nodtb.bin");
+ type = "standalone";
+ os = "U-Boot";
+ arch = "arm";
+ compression = "none";
+ load = <0x61000000>;
+ };
+ optee@1 {
+ description = "OP-TEE";
+ data = /incbin/("../../../tee.bin");
+ type = "firmware";
+ arch = "arm";
+ os = "tee";
+ compression = "none";
+ load = <0x68400000>;
+ entry = <0x68400000>;
+ };
+ fdt@1 {
+ description = "dtb";
+ data = /incbin/("../../../u-boot.dtb");
+ type = "flat_dt";
+ compression = "none";
+ };
+ };
+
+ configurations {
+ default = "conf@1";
+ conf@1 {
+ description = "Rockchip armv7 with OP-TEE";
+ firmware = "optee@1";
+ loadables = "uboot@1";
+ fdt = "fdt@1";
+ };
+ };
+};
diff --git a/arch/arm/mach-rockchip/make_fit_atf.py b/arch/arm/mach-rockchip/make_fit_atf.py
index 6b3d920..d1faff1 100755
--- a/arch/arm/mach-rockchip/make_fit_atf.py
+++ b/arch/arm/mach-rockchip/make_fit_atf.py
@@ -1,4 +1,4 @@
-#!/usr/bin/env python2
+#!/usr/bin/env python
"""
A script to generate FIT image source for rockchip boards
with ARM Trusted Firmware
@@ -34,7 +34,7 @@
#address-cells = <1>;
images {
- uboot@1 {
+ uboot {
description = "U-Boot (64-bit)";
data = /incbin/("u-boot-nodtb.bin");
type = "standalone";
@@ -43,6 +43,7 @@
compression = "none";
load = <0x%08x>;
};
+
"""
DT_IMAGES_NODE_END="""
@@ -53,23 +54,23 @@
};
"""
-def append_atf_node(file, atf_index, phy_addr):
+def append_atf_node(file, atf_index, phy_addr, elf_entry):
"""
Append ATF DT node to input FIT dts file.
"""
data = 'bl31_0x%08x.bin' % phy_addr
- print >> file, '\t\tatf@%d {' % atf_index
- print >> file, '\t\t\tdescription = \"ARM Trusted Firmware\";'
- print >> file, '\t\t\tdata = /incbin/("%s");' % data
- print >> file, '\t\t\ttype = "firmware";'
- print >> file, '\t\t\tarch = "arm64";'
- print >> file, '\t\t\tos = "arm-trusted-firmware";'
- print >> file, '\t\t\tcompression = "none";'
- print >> file, '\t\t\tload = <0x%08x>;' % phy_addr
+ file.write('\t\tatf_%d {\n' % atf_index)
+ file.write('\t\t\tdescription = \"ARM Trusted Firmware\";\n')
+ file.write('\t\t\tdata = /incbin/("%s");\n' % data)
+ file.write('\t\t\ttype = "firmware";\n')
+ file.write('\t\t\tarch = "arm64";\n')
+ file.write('\t\t\tos = "arm-trusted-firmware";\n')
+ file.write('\t\t\tcompression = "none";\n')
+ file.write('\t\t\tload = <0x%08x>;\n' % phy_addr)
if atf_index == 1:
- print >> file, '\t\t\tentry = <0x%08x>;' % phy_addr
- print >> file, '\t\t};'
- print >> file, ''
+ file.write('\t\t\tentry = <0x%08x>;\n' % elf_entry)
+ file.write('\t\t};\n')
+ file.write('\n')
def append_fdt_node(file, dtbs):
"""
@@ -78,43 +79,43 @@
cnt = 1
for dtb in dtbs:
dtname = os.path.basename(dtb)
- print >> file, '\t\tfdt@%d {' % cnt
- print >> file, '\t\t\tdescription = "%s";' % dtname
- print >> file, '\t\t\tdata = /incbin/("%s");' % dtb
- print >> file, '\t\t\ttype = "flat_dt";'
- print >> file, '\t\t\tcompression = "none";'
- print >> file, '\t\t};'
- print >> file, ''
+ file.write('\t\tfdt_%d {\n' % cnt)
+ file.write('\t\t\tdescription = "%s";\n' % dtname)
+ file.write('\t\t\tdata = /incbin/("%s");\n' % dtb)
+ file.write('\t\t\ttype = "flat_dt";\n')
+ file.write('\t\t\tcompression = "none";\n')
+ file.write('\t\t};\n')
+ file.write('\n')
cnt = cnt + 1
def append_conf_section(file, cnt, dtname, atf_cnt):
- print >> file, '\t\tconfig@%d {' % cnt
- print >> file, '\t\t\tdescription = "%s";' % dtname
- print >> file, '\t\t\tfirmware = "atf@1";'
- print >> file, '\t\t\tloadables = "uboot@1",',
+ file.write('\t\tconfig_%d {\n' % cnt)
+ file.write('\t\t\tdescription = "%s";\n' % dtname)
+ file.write('\t\t\tfirmware = "atf_1";\n')
+ file.write('\t\t\tloadables = "uboot",')
for i in range(1, atf_cnt):
- print >> file, '"atf@%d"' % (i+1),
+ file.write('"atf_%d"' % (i+1))
if i != (atf_cnt - 1):
- print >> file, ',',
+ file.write(',')
else:
- print >> file, ';'
- print >> file, '\t\t\tfdt = "fdt@1";'
- print >> file, '\t\t};'
- print >> file, ''
+ file.write(';\n')
+ file.write('\t\t\tfdt = "fdt_1";\n')
+ file.write('\t\t};\n')
+ file.write('\n')
def append_conf_node(file, dtbs, atf_cnt):
"""
Append configeration nodes.
"""
cnt = 1
- print >> file, '\tconfigurations {'
- print >> file, '\t\tdefault = "config@1";'
+ file.write('\tconfigurations {\n')
+ file.write('\t\tdefault = "config_1";\n')
for dtb in dtbs:
dtname = os.path.basename(dtb)
append_conf_section(file, cnt, dtname, atf_cnt)
cnt = cnt + 1
- print >> file, '\t};'
- print >> file, ''
+ file.write('\t};\n')
+ file.write('\n')
def generate_atf_fit_dts(fit_file_name, bl31_file_name, uboot_file_name, dtbs_file_name):
"""
@@ -127,7 +128,7 @@
num_load_seg = 0
p_paddr = 0xFFFFFFFF
- with open(uboot_file_name) as uboot_file:
+ with open(uboot_file_name, 'rb') as uboot_file:
uboot = ELFFile(uboot_file)
for i in range(uboot.num_segments()):
seg = uboot.get_segment(i)
@@ -137,27 +138,28 @@
assert (p_paddr != 0xFFFFFFFF and num_load_seg == 1)
- print >> fit_file, DT_HEADER % p_paddr
+ fit_file.write(DT_HEADER % p_paddr)
- with open(bl31_file_name) as bl31_file:
+ with open(bl31_file_name, 'rb') as bl31_file:
bl31 = ELFFile(bl31_file)
+ elf_entry = bl31.header['e_entry']
for i in range(bl31.num_segments()):
seg = bl31.get_segment(i)
if ('PT_LOAD' == seg.__getitem__(ELF_SEG_P_TYPE)):
paddr = seg.__getitem__(ELF_SEG_P_PADDR)
p= seg.__getitem__(ELF_SEG_P_PADDR)
- append_atf_node(fit_file, i+1, paddr)
+ append_atf_node(fit_file, i+1, paddr, elf_entry)
atf_cnt = i+1
append_fdt_node(fit_file, dtbs_file_name)
- print >> fit_file, '%s' % DT_IMAGES_NODE_END
+ fit_file.write('%s\n' % DT_IMAGES_NODE_END)
append_conf_node(fit_file, dtbs_file_name, atf_cnt)
- print >> fit_file, '%s' % DT_END
+ fit_file.write('%s\n' % DT_END)
if fit_file_name != sys.stdout:
fit_file.close()
def generate_atf_binary(bl31_file_name):
- with open(bl31_file_name) as bl31_file:
+ with open(bl31_file_name, 'rb') as bl31_file:
bl31 = ELFFile(bl31_file)
num = bl31.num_segments()
@@ -178,17 +180,17 @@
bl31 = ELFFile(bl31_file)
num = bl31.num_segments()
- print 'Number of Segments : %d' % bl31.num_segments()
+ print('Number of Segments : %d' % bl31.num_segments())
for i in range(num):
- print 'Segment %d' % i
+ print('Segment %d' % i)
seg = bl31.get_segment(i)
ptype = seg[ELF_SEG_P_TYPE]
poffset = seg[ELF_SEG_P_OFFSET]
pmemsz = seg[ELF_SEG_P_MEMSZ]
pfilesz = seg[ELF_SEG_P_FILESZ]
- print 'type: %s\nfilesz: %08x\nmemsz: %08x\noffset: %08x' % (ptype, pfilesz, pmemsz, poffset)
+ print('type: %s\nfilesz: %08x\nmemsz: %08x\noffset: %08x' % (ptype, pfilesz, pmemsz, poffset))
paddr = seg[ELF_SEG_P_PADDR]
- print 'paddr: %08x' % paddr
+ print('paddr: %08x' % paddr)
def main():
uboot_elf="./u-boot"
@@ -204,7 +206,7 @@
elif opt == "-b":
bl31_elf=val
elif opt == "-h":
- print __doc__
+ print(__doc__)
sys.exit(2)
dtbs = args
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 18dbc23..d056462 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -832,6 +832,13 @@
Enable access to the AM33xx RTC and select the external 32kHz clock
source.
+config SPL_OPTEE
+ bool "Support OP-TEE Trusted OS"
+ depends on ARM
+ help
+ OP-TEE is an open source Trusted OS which is loaded by SPL.
+ More detail at: https://github.com/OP-TEE/optee_os
+
config TPL
bool
depends on SUPPORT_TPL
diff --git a/common/spl/Makefile b/common/spl/Makefile
index 814081f..a130a5b 100644
--- a/common/spl/Makefile
+++ b/common/spl/Makefile
@@ -21,6 +21,7 @@
obj-$(CONFIG_$(SPL_TPL_)NET_SUPPORT) += spl_net.o
obj-$(CONFIG_$(SPL_TPL_)MMC_SUPPORT) += spl_mmc.o
obj-$(CONFIG_$(SPL_TPL_)ATF) += spl_atf.o
+obj-$(CONFIG_$(SPL_TPL_)OPTEE) += spl_optee.o
obj-$(CONFIG_$(SPL_TPL_)USB_SUPPORT) += spl_usb.o
obj-$(CONFIG_$(SPL_TPL_)FAT_SUPPORT) += spl_fat.o
obj-$(CONFIG_$(SPL_TPL_)EXT_SUPPORT) += spl_ext.o
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 038f2b0..292e659 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -536,6 +536,13 @@
spl_invoke_atf(&spl_image);
break;
#endif
+#if CONFIG_IS_ENABLED(OPTEE)
+ case IH_OS_TEE:
+ debug("Jumping to U-Boot via OP-TEE\n");
+ spl_optee_entry(NULL, NULL, spl_image.fdt_addr,
+ (void *)spl_image.entry_point);
+ break;
+#endif
#ifdef CONFIG_SPL_OS_BOOT
case IH_OS_LINUX:
debug("Jumping to Linux\n");
diff --git a/common/spl/spl_optee.S b/common/spl/spl_optee.S
new file mode 100644
index 0000000..8bd1949
--- /dev/null
+++ b/common/spl/spl_optee.S
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Rockchip Electronic Co.,Ltd
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+ENTRY(spl_optee_entry)
+ ldr lr, =CONFIG_SYS_TEXT_BASE
+ mov pc, r3
+ENDPROC(spl_optee_entry)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index 30a24d1..c01ae75 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -24,6 +24,11 @@
#include <dt-bindings/clock/rk3288-cru.h>
#include "designware.h"
+DECLARE_GLOBAL_DATA_PTR;
+#define DELAY_ENABLE(soc, tx, rx) \
+ (((tx) ? soc##_TXCLK_DLY_ENA_GMAC_ENABLE : soc##_TXCLK_DLY_ENA_GMAC_DISABLE) | \
+ ((rx) ? soc##_RXCLK_DLY_ENA_GMAC_ENABLE : soc##_RXCLK_DLY_ENA_GMAC_DISABLE))
+
/*
* Platform data for the gmac
*
@@ -286,8 +291,7 @@
RK3228_RXCLK_DLY_ENA_GMAC_MASK |
RK3228_TXCLK_DLY_ENA_GMAC_MASK,
RK3228_GMAC_PHY_INTF_SEL_RGMII |
- RK3228_RXCLK_DLY_ENA_GMAC_ENABLE |
- RK3228_TXCLK_DLY_ENA_GMAC_ENABLE);
+ DELAY_ENABLE(RK3228, pdata->tx_delay, pdata->rx_delay));
rk_clrsetreg(&grf->mac_con[0],
RK3228_CLK_RX_DL_CFG_GMAC_MASK |
@@ -310,8 +314,7 @@
RK3288_TXCLK_DLY_ENA_GMAC_MASK |
RK3288_CLK_RX_DL_CFG_GMAC_MASK |
RK3288_CLK_TX_DL_CFG_GMAC_MASK,
- RK3288_RXCLK_DLY_ENA_GMAC_ENABLE |
- RK3288_TXCLK_DLY_ENA_GMAC_ENABLE |
+ DELAY_ENABLE(RK3288, pdata->rx_delay, pdata->tx_delay) |
pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT |
pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
}
@@ -350,8 +353,7 @@
RK3328_RXCLK_DLY_ENA_GMAC_MASK |
RK3328_TXCLK_DLY_ENA_GMAC_MASK,
RK3328_GMAC_PHY_INTF_SEL_RGMII |
- RK3328_RXCLK_DLY_ENA_GMAC_MASK |
- RK3328_TXCLK_DLY_ENA_GMAC_ENABLE);
+ DELAY_ENABLE(RK3328, pdata->tx_delay, pdata->rx_delay));
rk_clrsetreg(&grf->mac_con[0],
RK3328_CLK_RX_DL_CFG_GMAC_MASK |
@@ -392,8 +394,7 @@
RK3368_TXCLK_DLY_ENA_GMAC_MASK |
RK3368_CLK_RX_DL_CFG_GMAC_MASK |
RK3368_CLK_TX_DL_CFG_GMAC_MASK,
- RK3368_RXCLK_DLY_ENA_GMAC_ENABLE |
- RK3368_TXCLK_DLY_ENA_GMAC_ENABLE |
+ DELAY_ENABLE(RK3368, pdata->tx_delay, pdata->rx_delay) |
pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT |
pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT);
}
@@ -413,8 +414,7 @@
RK3399_TXCLK_DLY_ENA_GMAC_MASK |
RK3399_CLK_RX_DL_CFG_GMAC_MASK |
RK3399_CLK_TX_DL_CFG_GMAC_MASK,
- RK3399_RXCLK_DLY_ENA_GMAC_ENABLE |
- RK3399_TXCLK_DLY_ENA_GMAC_ENABLE |
+ DELAY_ENABLE(RK3399, pdata->tx_delay, pdata->rx_delay) |
pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT |
pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT);
}
@@ -451,40 +451,86 @@
switch (eth_pdata->phy_interface) {
case PHY_INTERFACE_MODE_RGMII:
- /*
- * If the gmac clock is from internal pll, need to set and
- * check the return value for gmac clock at RGMII mode. If
- * the gmac clock is from external source, the clock rate
- * is not set, because of it is bypassed.
- */
- if (!pdata->clock_input) {
- rate = clk_set_rate(&clk, 125000000);
- if (rate != 125000000)
- return -EINVAL;
- }
-
/* Set to RGMII mode */
if (ops->set_to_rgmii)
ops->set_to_rgmii(pdata);
else
return -EPERM;
- break;
- case PHY_INTERFACE_MODE_RMII:
- /* The commet is the same as RGMII mode */
+ /*
+ * If the gmac clock is from internal pll, need to set and
+ * check the return value for gmac clock at RGMII mode. If
+ * the gmac clock is from external source, the clock rate
+ * is not set, because of it is bypassed.
+ */
+
if (!pdata->clock_input) {
- rate = clk_set_rate(&clk, 50000000);
- if (rate != 50000000)
+ rate = clk_set_rate(&clk, 125000000);
+ if (rate != 125000000)
return -EINVAL;
}
+ break;
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ /* Set to RGMII mode */
+ if (ops->set_to_rgmii) {
+ pdata->tx_delay = 0;
+ pdata->rx_delay = 0;
+ ops->set_to_rgmii(pdata);
+ } else
+ return -EPERM;
+
+ if (!pdata->clock_input) {
+ rate = clk_set_rate(&clk, 125000000);
+ if (rate != 125000000)
+ return -EINVAL;
+ }
+ break;
+
+ case PHY_INTERFACE_MODE_RMII:
/* Set to RMII mode */
if (ops->set_to_rmii)
ops->set_to_rmii(pdata);
else
return -EPERM;
+ if (!pdata->clock_input) {
+ rate = clk_set_rate(&clk, 50000000);
+ if (rate != 50000000)
+ return -EINVAL;
+ }
break;
+
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ /* Set to RGMII_RXID mode */
+ if (ops->set_to_rgmii) {
+ pdata->tx_delay = 0;
+ ops->set_to_rgmii(pdata);
+ } else
+ return -EPERM;
+
+ if (!pdata->clock_input) {
+ rate = clk_set_rate(&clk, 125000000);
+ if (rate != 125000000)
+ return -EINVAL;
+ }
+ break;
+
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ /* Set to RGMII_TXID mode */
+ if (ops->set_to_rgmii) {
+ pdata->rx_delay = 0;
+ ops->set_to_rgmii(pdata);
+ } else
+ return -EPERM;
+
+ if (!pdata->clock_input) {
+ rate = clk_set_rate(&clk, 125000000);
+ if (rate != 125000000)
+ return -EINVAL;
+ }
+ break;
+
default:
debug("NO interface defined!\n");
return -ENXIO;
diff --git a/include/spl.h b/include/spl.h
index b42683c..9a439f4 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -289,6 +289,19 @@
void spl_invoke_atf(struct spl_image_info *spl_image);
/**
+ * spl_optee_entry - entry function for optee
+ *
+ * args defind in op-tee project
+ * https://github.com/OP-TEE/optee_os/
+ * core/arch/arm/kernel/generic_entry_a32.S
+ * @arg0: pagestore
+ * @arg1: (ARMv7 standard bootarg #1)
+ * @arg2: device tree address, (ARMv7 standard bootarg #2)
+ * @arg3: non-secure entry address (ARMv7 bootarg #0)
+ */
+void spl_optee_entry(void *arg0, void *arg1, void *arg2, void *arg3);
+
+/**
* board_return_to_bootrom - allow for boards to continue with the boot ROM
*
* If a board (e.g. the Rockchip RK3368 boards) provide some
diff --git a/tools/rkimage.c b/tools/rkimage.c
index a0a3185..ae50de5 100644
--- a/tools/rkimage.c
+++ b/tools/rkimage.c
@@ -15,8 +15,7 @@
static void rkimage_set_header(void *buf, struct stat *sbuf, int ifd,
struct image_tool_params *params)
{
- memcpy(buf + RK_SPL_HDR_START, rkcommon_get_spl_hdr(params),
- RK_SPL_HDR_SIZE);
+ memcpy(buf, rkcommon_get_spl_hdr(params), RK_SPL_HDR_SIZE);
if (rkcommon_need_rc4_spl(params))
rkcommon_rc4_encode_spl(buf, 4, params->file_size);
@@ -36,7 +35,7 @@
U_BOOT_IMAGE_TYPE(
rkimage,
"Rockchip Boot Image support",
- 4,
+ 0,
&header,
rkcommon_check_params,
NULL,