| commit | a4bcd67c72aabfcc2153f4393cd9108b860d9040 | [log] [tgz] |
|---|---|---|
| author | Stephen Warren <swarren@nvidia.com> | Fri Jan 24 12:46:10 2014 -0700 |
| committer | Tom Warren <twarren@nvidia.com> | Mon Feb 03 09:46:46 2014 -0700 |
| tree | c7cfa7874568332256fe6e3c5e41c04f9e6f5bf0 | |
| parent | 41447fb2cf2fbeb448b1d606cb13ca1ae84f9737 [diff] |
ARM: tegra: remove a conditional for CSITE rate There's already an SoC-specific conditional in cpu.h to determine the PLLP rate. Define the CSITE clock rate inside the same conditional, so that we can remove a conditional from clock_enable_coresight(). This means one less place to update the code for new SoCs. Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>