| commit | a5eca322f4077d31fe32ddf8db060022cb5637a3 | [log] [tgz] |
|---|---|---|
| author | Enrico Leto <enrico.leto@siemens.com> | Sat Nov 23 17:53:03 2024 +0100 |
| committer | Fabio Estevam <festevam@gmail.com> | Mon Nov 25 23:07:37 2024 -0300 |
| tree | 9ca1487d740b2e7ea5528b5ef3ee6c00f908971a | |
| parent | 1d0239780385025ad9c9ca3c0a107d17960ede54 [diff] |
siemens: add ddr signal integrity test The signal integrity test generates pattern on DDR lines for certification. The signals must be as fast as possible and unidirectional. The test is required from our HW team. The available u-boot memory test doesn't full fill the our requirements. The test is planed to be used in all new siemens boards. Signed-off-by: Enrico Leto <enrico.leto@siemens.com> Signed-off-by: Heiko Schocher <hs@denx.de>