ARM: kirkwood: add SBx81LIFXCAT board
This is a series of line cards for Allied Telesis's SBx8100 chassis
switch. The CPU block is common to the SBx81GP24 and SBx81GT24 cards
cards collectively referred to as SBx81LIFXCAT in u-boot.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
diff --git a/board/alliedtelesis/SBx81LIFXCAT/Kconfig b/board/alliedtelesis/SBx81LIFXCAT/Kconfig
new file mode 100644
index 0000000..524c290
--- /dev/null
+++ b/board/alliedtelesis/SBx81LIFXCAT/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SBx81LIFXCAT
+
+config SYS_BOARD
+ default "SBx81LIFXCAT"
+
+config SYS_VENDOR
+ default "alliedtelesis"
+
+config SYS_CONFIG_NAME
+ default "SBx81LIFXCAT"
+
+endif
diff --git a/board/alliedtelesis/SBx81LIFXCAT/MAINTAINERS b/board/alliedtelesis/SBx81LIFXCAT/MAINTAINERS
new file mode 100644
index 0000000..6b722de
--- /dev/null
+++ b/board/alliedtelesis/SBx81LIFXCAT/MAINTAINERS
@@ -0,0 +1,7 @@
+SBx81LIFXCAT BOARD
+M: Chris Packham <chris.packham@alliedtelesis.co.nz>
+S: Maintained
+F: board/alliedtelesis/SBx81LIFXCAT/
+F: include/configs/SBx81LIFXCAT
+F: configs/SBx81LIFXCAT_defconfig
+F: arch/arm/dts/kirkwood-atl-sbx81lifxcat.dts
diff --git a/board/alliedtelesis/SBx81LIFXCAT/Makefile b/board/alliedtelesis/SBx81LIFXCAT/Makefile
new file mode 100644
index 0000000..f21c8ef
--- /dev/null
+++ b/board/alliedtelesis/SBx81LIFXCAT/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2010, 2018
+# Allied Telesis <www.alliedtelesis.com>
+#
+
+obj-y += sbx81lifxcat.o
diff --git a/board/alliedtelesis/SBx81LIFXCAT/kwbimage.cfg b/board/alliedtelesis/SBx81LIFXCAT/kwbimage.cfg
new file mode 100644
index 0000000..53d4812
--- /dev/null
+++ b/board/alliedtelesis/SBx81LIFXCAT/kwbimage.cfg
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2018 Allied Telesis
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM spi # Boot from SPI flash
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+DATA 0xffd100e0 0x1b1b1b1b
+DATA 0xffd20134 0xffffffff
+DATA 0xffd20138 0x009fffff
+DATA 0xffd20154 0x00000000
+DATA 0xffd2014c 0x00000000
+DATA 0xffd20148 0x00000001
+
+# Dram initalization for 1 x x16
+# DDR II Micron part number MT47H64M16HR-3
+# MClk 333MHz, Size 128MB, ECC disable
+#
+DATA 0xffd01400 0x43000618
+DATA 0xffd01404 0x38543000
+DATA 0xffd01408 0x23125441
+DATA 0xffd0140c 0x00000832
+DATA 0xffd01410 0x0000000D
+DATA 0xffd01414 0x00000000
+DATA 0xffd01418 0x00000000
+DATA 0xffd0141c 0x00000652
+DATA 0xffd01420 0x00000042
+DATA 0xffd01424 0x0000F0FF
+DATA 0xffd01428 0x00074410
+DATA 0xffd0147C 0x00007441
+DATA 0xffd01500 0x00000000 # SDRAM CS[0] Base address at 0x00000000
+DATA 0xffd01504 0x07FFFFF1 # SDRAM CS[0] Size 128MiB
+DATA 0xffd01508 0x10000000
+DATA 0xffd0150c 0x00FFFFF4 # SDRAM CS[1] Size, window disabled
+DATA 0xffd01514 0x00FFFFF8 # SDRAM CS[2] Size, window disabled
+DATA 0xffd0151c 0x00FFFFFC # SDRAM CS[3] Size, window disabled
+DATA 0xffd01494 0x84210000
+DATA 0xffd01498 0x00000000
+DATA 0xffd0149c 0x0000F80F
+DATA 0xffd01480 0x00000001
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/alliedtelesis/SBx81LIFXCAT/sbx81lifxcat.c b/board/alliedtelesis/SBx81LIFXCAT/sbx81lifxcat.c
new file mode 100644
index 0000000..c584fc0
--- /dev/null
+++ b/board/alliedtelesis/SBx81LIFXCAT/sbx81lifxcat.c
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2010, 2018
+ * Allied Telesis <www.alliedtelesis.com>
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <led.h>
+#include <linux/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/gpio.h>
+
+#define SBX81LIFXCAT_OE_LOW (~0)
+#define SBX81LIFXCAT_OE_HIGH (~BIT(11))
+#define SBX81LIFXCAT_OE_VAL_LOW (0)
+#define SBX81LIFXCAT_OE_VAL_HIGH (BIT(11))
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ mvebu_config_gpio(SBX81LIFXCAT_OE_VAL_LOW,
+ SBX81LIFXCAT_OE_VAL_HIGH,
+ SBX81LIFXCAT_OE_LOW, SBX81LIFXCAT_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
+ MPP0_SPI_SCn,
+ MPP1_SPI_MOSI,
+ MPP2_SPI_SCK,
+ MPP3_SPI_MISO,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_GPO,
+ MPP8_TW_SDA,
+ MPP9_TW_SCK,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_GPO,
+ MPP13_UART1_TXD,
+ MPP14_UART1_RXD,
+ MPP15_GPIO,
+ MPP16_GPIO,
+ MPP17_GPIO,
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_GE1_0,
+ MPP21_GE1_1,
+ MPP22_GE1_2,
+ MPP23_GE1_3,
+ MPP24_GE1_4,
+ MPP25_GE1_5,
+ MPP26_GE1_6,
+ MPP27_GE1_7,
+ MPP28_GE1_8,
+ MPP29_GE1_9,
+ MPP30_GE1_10,
+ MPP31_GE1_11,
+ MPP32_GE1_12,
+ MPP33_GE1_13,
+ MPP34_GPIO,
+ MPP35_GPIO,
+ MPP36_GPIO,
+ MPP37_GPIO,
+ MPP38_GPIO,
+ MPP39_GPIO,
+ MPP40_GPIO,
+ MPP41_GPIO,
+ MPP42_GPIO,
+ MPP43_GPIO,
+ MPP44_GPIO,
+ MPP45_GPIO,
+ MPP46_GPIO,
+ MPP47_GPIO,
+ MPP48_GPIO,
+ MPP49_GPIO,
+ 0
+ };
+
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* automatically defined by kirkwood config.h */
+void reset_phy(void)
+{
+}
+#endif
+
+#ifdef CONFIG_MV88E61XX_SWITCH
+int mv88e61xx_hw_reset(struct phy_device *phydev)
+{
+ phydev->advertising = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = led_get_by_label("status:ledp", &dev);
+ if (!ret)
+ led_set_state(dev, LEDST_ON);
+
+ ret = led_get_by_label("status:ledn", &dev);
+ if (!ret)
+ led_set_state(dev, LEDST_OFF);
+
+ return 0;
+}
+#endif