| commit | a72532fa194ed31b559bdd8b287854df0a4903f8 | [log] [tgz] |
|---|---|---|
| author | Nikhil M Jain <n-jain1@ti.com> | Tue Jul 18 14:27:35 2023 +0530 |
| committer | Tom Rini <trini@konsulko.com> | Fri Jul 21 15:32:12 2023 -0400 |
| tree | b6981028f79b40cc7a85b8bb615704edcb23d66f | |
| parent | 1f7682383f4334afc21ea62b072392955d201d62 [diff] |
doc: board: ti: am62x_sk: Add A53 SPL DDR layout To understand usage of DDR in A53 SPL stage, add a table showing region and space used by major components of SPL. Signed-off-by: Nikhil M Jain <n-jain1@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>