| commit | a942c0c3f5d454241cf2c1d61d06a42dcd6a14cc | [log] [tgz] |
|---|---|---|
| author | Christian Marangi <ansuelsmth@gmail.com> | Sat Aug 03 10:43:23 2024 +0200 |
| committer | Tom Rini <trini@konsulko.com> | Mon Aug 19 16:15:26 2024 -0600 |
| tree | a3a1f15b0b516f487ec929908cc501f4939d1626 | |
| parent | 6dfa991204a6fe033a5f0c49ff4f1d6e8af3ed7c [diff] |
clk: mediatek: mt7622: add missing clock MUX1_SEL Add missing infra clock MUX1_SEL needed for CPU clock. This is needed to match the upstream clk ID order in preparation for OF_UPSTREAM. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>