| commit | a94c9c809b26c9fbc58dcc2796ff879fc56b0c7e | [log] [tgz] |
|---|---|---|
| author | Andre Przywara <andre.przywara@arm.com> | Fri Dec 02 21:48:19 2022 +0000 |
| committer | Andre Przywara <andre.przywara@arm.com> | Sun Oct 22 23:41:51 2023 +0100 |
| tree | e8b1b9d98323b3d60daae37e1dd49ca3eea37ee8 | |
| parent | 39ba474698bb4bc3dc48fd0c024f7cf06b08077a [diff] |
sunxi: clock: support D1/R528 PLL6 clock The PLL_PERIPH0 clock changed a bit in the D1/R528/T113s SoCs: there is new P0 divider at bits [18:16], and the M divider is 1. Add code to support this version of "PLL6". Signed-off-by: Andre Przywara <andre.przywara@arm.com>